From nobody Sat Feb 7 01:53:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580342289874273.02890959161414; Wed, 29 Jan 2020 15:58:09 -0800 (PST) Received: from localhost ([::1]:53458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwxDk-0005hA-Jd for importer@patchew.org; Wed, 29 Jan 2020 18:58:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45291) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwxCG-0003m0-M4 for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwxCF-0007Sf-50 for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:36 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:33440) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iwxCE-0007Pm-Ue for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:35 -0500 Received: by mail-pg1-x543.google.com with SMTP id 6so662381pgk.0 for ; Wed, 29 Jan 2020 15:56:34 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4T1mZmgmBTKlXhJYUeO40nqlR1hCfBuX99d9bZ2+xfQ=; b=Qljf3ReGjrgROkLFeM2OtsBcXh115uwA9CWhSRbsPxgQLN11duW8byIlmmo0NyFUcR Bt358Zjd2ZmkSvijWvSNUnRCsC7+iomw7vTu+F6maFWzgaqouhlPsjN3C6a+4CKNhb6r Roc3kHXlXo79A39ERhrBxOo9gDjuTAVp1tWw8zlAlErtMd36q0RkVtx4FvIe7E+6Yrk9 QxLyFQiSrwtp08zlS9ilNX0oRxYbaaVaXlillRyV1hZabzaGaj+lH5IB46v3hiLL7IzC cVSX0jQtacBvGCw23Wgks7AbenctWNQsiukDILbWHa6fMyocwgtrprRSsjYBQWV76tn6 exig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4T1mZmgmBTKlXhJYUeO40nqlR1hCfBuX99d9bZ2+xfQ=; b=qBU71Uwo2z3cI4x7Z8QXA10l1CF9pEuvSa7IAMCoCtBiHjTbP4J3ZSrfJIuVkrOzz+ HPPiXZX85paDM4FQEoPIOOjk8d9ZC8+tbATcpQni7YZCqo92pwE/1drHWoNK0hKfi9J5 0qVnv5W94MpnmqRamlJHsuOKM0mMHLXN/3fgH7WN+Dk+WTX1QqNfbqiYkyQvB6EToGf8 xWYl23gFccjUgXA03ZdKsbkIpzm/mr+LRw+LZdfO+7EMJf56OwtmAljoBkhUKFY4E/Cu 65mqeMRjp/y1UHej8AcCKDi3wPNfqZXJ81pFZARGyuBAVWyYVaPe2tPVDROvbecYK2Wn 2f4g== X-Gm-Message-State: APjAAAU0RowQoA/PIh2oOgroUytReHU88LQSKSqUoPP9nlHpKBfkfxdx B01bRiWvLAPJreXJiSOfBtt6ON/Ojwc= X-Google-Smtp-Source: APXvYqyzunFdv0/5fjWx07Frwj5Dzz5jonY+7Tlmb0g6l8La8in0GcZ3as5FLProf5clzpnSmc4D2w== X-Received: by 2002:a62:f247:: with SMTP id y7mr2102969pfl.5.1580342193645; Wed, 29 Jan 2020 15:56:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Date: Wed, 29 Jan 2020 15:55:47 -0800 Message-Id: <20200129235614.29829-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 22 +++++++++++----------- target/arm/translate.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a5133b74c3..f984585225 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2900,7 +2900,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, @@ -2926,7 +2926,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_0 =3D 1 << 0, ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_S1E2 =3D 1 << 2, + ARMMMUIdxBit_E2 =3D 1 << 2, ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE10_0 =3D 1 << 4, ARMMMUIdxBit_SE10_1 =3D 1 << 5, diff --git a/target/arm/internals.h b/target/arm/internals.h index d8730fbbad..5b8b9c233f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_E10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index aac117db33..a06a3a187d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -728,7 +728,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -736,7 +736,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -745,7 +745,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -755,7 +755,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static const ARMCPRegInfo cp_reginfo[] =3D { @@ -3238,7 +3238,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -3266,7 +3266,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -4004,7 +4004,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4030,7 +4030,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4052,7 +4052,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4105,7 +4105,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -8710,7 +8710,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage2: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 75afcb03fb..91e2ca5515 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); --=20 2.20.1