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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uXSQmjNDRbErAOmFKI5Qlfxm6f2ogSCMY5BixEyGR9w=; b=TITT49m7M71pGk2e9s6LJpJdJ+UpJGVnsOt9ggXlzslLLpHArqzh4i0djhvCjThmIy e5rSg6a9MKuL36yAJ8Eyknj3rO9ZULwzczI31cuYzZfzdkERRPs6kLXTUfEb0t9MGNcK tGyaaNwpnJGH1vlTwnYKZjGywu2uJwAQZvOvFg5ALyveM14GYwy0j5GYnPo8JkQGRtXw IfZXUmzQ3gn+WXhzts3d3zjLMbRO8+brsVm8dDQVse5Qkj07MEGnAMfQ/SRV+dKzsia4 WyLRiuI+znErGgJJyFlxMYMU98DPXCuI1mdG6qiByKmuY6x50E57sZlJnwh8LYWnInS1 KFig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uXSQmjNDRbErAOmFKI5Qlfxm6f2ogSCMY5BixEyGR9w=; b=K6Vf2ZP0XZ1KJA0SO3r6oRuENojcmD+3ZHneT7D/LaztgId2b5neUFufhEmAo7vL3L kM9tmmEsBWoIxcBKHAe6MxX40y2uushH4G52ojFRm4Ryw162hX+t8Iu+WiaTbF08rpIn FWz72YK5pFw1sW/B4NkB87574rOI6Gq9qOukAsSvLVTz6STbSuetqgcMrZIivgl7acil qfHCkemZFombmA0IiJhMOE5LfVjsW061Q5Ifga6WUjex8mFhL06t5avyGy4oeep+uf6a 6LRDv8NgLIuLFKb/0w29FEcZk8Hfz1YQAW0/6pQTyhVh9UMDMY04Rl+mAMW6EAe62az+ zGKg== X-Gm-Message-State: APjAAAW7A/cp4hY2ETg0uh27GHAfxbRvW9iyKcwVw4oVLC8o68xpa6id StBFijWBRjnX47pJQWgVIqeduFmz9sQ= X-Google-Smtp-Source: APXvYqzGnnFwGQGVHK5OxTcksxf5jxne5Es97OwU9vU92ugzdv059NZ0mKeVcu1tQ0anRq0ITD5H7A== X-Received: by 2002:a17:902:502:: with SMTP id 2mr1885511plf.151.1580342189834; Wed, 29 Jan 2020 15:56:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Date: Wed, 29 Jan 2020 15:55:44 -0800 Message-Id: <20200129235614.29829-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v5: Adjust || indentation (ajb) --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/helper.c | 27 ++++++++++++++------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 532ea6ce09..ec422e1963 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2916,8 +2916,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* Bit macros for the core-mmu-index values for each index, diff --git a/target/arm/internals.h b/target/arm/internals.h index 1509e45e98..280b5b0c82 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_S1E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); #ifdef CONFIG_USER_ONLY static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { - return ARMMMUIdx_S1NSE0; + return ARMMMUIdx_Stage1_E0; } #else ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 6cf4baba44..15d7e48ca7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3041,7 +3041,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, bool take_exc =3D false; =20 if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) - && (mmu_idx =3D=3D ARMMMUIdx_S1NSE1 || mmu_idx =3D=3D ARMMMUId= x_S1NSE0)) { + && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 || + mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -3189,10 +3190,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1E3; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3205,10 +3206,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1SE0; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3262,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3275,7 +3276,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; @@ -8716,8 +8717,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_S1SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8775,7 +8776,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } =20 if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { + (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -8820,7 +8821,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0); + mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0); } return mmu_idx; } @@ -8855,7 +8856,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -9086,7 +9087,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && + if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.20.1