From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580207789615225.68169659622163; Tue, 28 Jan 2020 02:36:29 -0800 (PST) Received: from localhost ([::1]:56592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOEO-0008MF-1k for importer@patchew.org; Tue, 28 Jan 2020 05:36:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47978) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwODM-0006sc-Hq for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwODL-0000Fh-Lp for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:24 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:43045 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iwODL-0000FU-IR for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:23 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-226-60MnbJ6RNh6DWtQjzWJD4g-1; Tue, 28 Jan 2020 05:35:17 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 47B7B1005510; Tue, 28 Jan 2020 10:35:16 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id E70F91001B30; Tue, 28 Jan 2020 10:35:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207722; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g1Y7SAIkQ6YKL70iv+PevVOHVnPkk+5bW/+E3fVVoME=; b=bbPilG3naIr1ePcnMiUJ3aQKVM3AHb3amhlnB97UkX8XdnBPhT78yu0Mo/oQJY8n85x4Gu e6IL6Y0DX0+liZVzX5nsmgZ7wWvcCsbPK3zN2b9rBAa6V7759hBVInJhYge5pK3eH3qwxW bFTAacgfLNdbRAZIbKrb8FcAkxxhx8A= X-MC-Unique: 60MnbJ6RNh6DWtQjzWJD4g-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 01/14] libcflat: Add other size defines Date: Tue, 28 Jan 2020 11:34:46 +0100 Message-Id: <20200128103459.19413-2-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Introduce additional SZ_256, SZ_8K, SZ_16K macros that will be used by ITS tests. Signed-off-by: Eric Auger Reviewed-by: Thomas Huth --- lib/libcflat.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/libcflat.h b/lib/libcflat.h index ea19f61..7092af2 100644 --- a/lib/libcflat.h +++ b/lib/libcflat.h @@ -36,7 +36,10 @@ #define ALIGN(x, a) __ALIGN((x), (a)) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) =3D=3D 0) =20 +#define SZ_256 (1 << 8) #define SZ_4K (1 << 12) +#define SZ_8K (1 << 13) +#define SZ_16K (1 << 14) #define SZ_64K (1 << 16) #define SZ_2M (1 << 21) #define SZ_1G (1 << 30) --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580207885211594.054220904419; Tue, 28 Jan 2020 02:38:05 -0800 (PST) Received: from localhost ([::1]:56650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOFw-0003bN-6R for importer@patchew.org; Tue, 28 Jan 2020 05:38:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48005) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwODP-0006xX-Ew for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwODO-0000Gm-5s for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:27 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:27280 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iwODO-0000GZ-2e for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:26 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-221-CymzZg9NPg-7tVbWGeDa5g-1; Tue, 28 Jan 2020 05:35:23 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2CBB3DB60; Tue, 28 Jan 2020 10:35:22 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id D1BFF1001B08; Tue, 28 Jan 2020 10:35:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207725; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hksWhfx/qjqLBl2kwSG6HIa1DnV2Yh8CnWY4dayzAHc=; b=KAxGI6ROO/L68XdlNESrogr807MaG0fNXdZcxfzCOcSt2IhD9f7T5xu71oQ4lzSknGXbXG XBE3bX1TTVbvtCVjXA+8n+mlZnrKXMz0Rs35Sdc8S/sVKCgXelZ+rn7C8WHp9hq7UAho9b rDeN7phtd1G+vYn836oZOkSk+Y3p7jc= X-MC-Unique: CymzZg9NPg-7tVbWGeDa5g-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 02/14] arm: gic: Provide per-IRQ helper functions Date: Tue, 28 Jan 2020 11:34:47 +0100 Message-Id: <20200128103459.19413-3-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andre Przywara A common theme when accessing per-IRQ parameters in the GIC distributor is to set fields of a certain bit width in a range of MMIO registers. Examples are the enabled status (one bit per IRQ), the level/edge configuration (2 bits per IRQ) or the priority (8 bits per IRQ). Add a generic helper function which is able to mask and set the respective number of bits, given the IRQ number and the MMIO offset. Provide wrappers using this function to easily allow configuring an IRQ. For now assume that private IRQ numbers always refer to the current CPU. In a GICv2 accessing the "other" private IRQs is not easily doable (the registers are banked per CPU on the same MMIO address), so we impose the same limitation on GICv3, even though those registers are not banked there anymore. Signed-off-by: Andre Przywara --- initialize reg --- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 8 ++++ lib/arm/gic.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 0dc838b..6beeab6 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -23,6 +23,8 @@ #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) =20 +#define GICD_IROUTER 0x6000 + /* Re-Distributor registers, offsets from RD_base */ #define GICR_TYPER 0x0008 =20 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 09826fd..21cdb58 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -74,5 +74,13 @@ extern void gic_write_eoir(u32 irqstat); extern void gic_ipi_send_single(int irq, int cpu); extern void gic_ipi_send_mask(int irq, const cpumask_t *dest); =20 +void gic_set_irq_bit(int irq, int offset); +void gic_enable_irq(int irq); +void gic_disable_irq(int irq); +void gic_set_irq_priority(int irq, u8 prio); +void gic_set_irq_target(int irq, int cpu); +void gic_set_irq_group(int irq, int group); +int gic_get_irq_group(int irq); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 9430116..aa9cb86 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -146,3 +146,93 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest) assert(gic_common_ops && gic_common_ops->ipi_send_mask); gic_common_ops->ipi_send_mask(irq, dest); } + +enum gic_bit_access { + ACCESS_READ, + ACCESS_SET, + ACCESS_RMW +}; + +static u8 gic_masked_irq_bits(int irq, int offset, int bits, u8 value, + enum gic_bit_access access) +{ + void *base; + int split =3D 32 / bits; + int shift =3D (irq % split) * bits; + u32 reg =3D 0, mask =3D ((1U << bits) - 1) << shift; + + switch (gic_version()) { + case 2: + base =3D gicv2_dist_base(); + break; + case 3: + if (irq < 32) + base =3D gicv3_sgi_base(); + else + base =3D gicv3_dist_base(); + break; + default: + return 0; + } + base +=3D offset + (irq / split) * 4; + + switch (access) { + case ACCESS_READ: + return (readl(base) & mask) >> shift; + case ACCESS_SET: + reg =3D 0; + break; + case ACCESS_RMW: + reg =3D readl(base) & ~mask; + break; + } + + writel(reg | ((u32)value << shift), base); + + return 0; +} + +void gic_set_irq_bit(int irq, int offset) +{ + gic_masked_irq_bits(irq, offset, 1, 1, ACCESS_SET); +} + +void gic_enable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ISENABLER); +} + +void gic_disable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ICENABLER); +} + +void gic_set_irq_priority(int irq, u8 prio) +{ + gic_masked_irq_bits(irq, GICD_IPRIORITYR, 8, prio, ACCESS_RMW); +} + +void gic_set_irq_target(int irq, int cpu) +{ + if (irq < 32) + return; + + if (gic_version() =3D=3D 2) { + gic_masked_irq_bits(irq, GICD_ITARGETSR, 8, 1U << cpu, + ACCESS_RMW); + + return; + } + + writeq(cpus[cpu], gicv3_dist_base() + GICD_IROUTER + irq * 8); +} + +void gic_set_irq_group(int irq, int group) +{ + gic_masked_irq_bits(irq, GICD_IGROUPR, 1, group, ACCESS_RMW); +} + +int gic_get_irq_group(int irq) +{ + return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); +} --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580207807935578.9049349396957; Tue, 28 Jan 2020 02:36:47 -0800 (PST) Received: from localhost ([::1]:56610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOEg-0000Wb-LI for importer@patchew.org; Tue, 28 Jan 2020 05:36:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48096) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwODe-0007XE-SP for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwODd-0000Mg-U0 for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:42 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:41298 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iwODd-0000MO-Q7 for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:35:41 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-296-xHLUGjwBM7-GS3DpZpuesQ-1; Tue, 28 Jan 2020 05:35:33 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0BC38107ACC4; Tue, 28 Jan 2020 10:35:31 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id E637C1084194; Tue, 28 Jan 2020 10:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207741; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MvayPD2KrkjvVludp3nPmXgg5XhOf+bBUlyipWBvYKU=; b=O5zSv6vmzaCd+4T9V2SXKVvG/qpF+yg6mC/9JFeSspiZhgLDDfFvZcDJa9C+XJO3wlDHkQ ckOLJNfwx3J0H6Wlo4taduudtSBFx0aLMUexSDjwIi3jjgjkuELh7HkhzJGP9XeXcdMkxO n83cGD3H7tblQDkRZS4/T+suqkR/BFI= X-MC-Unique: xHLUGjwBM7-GS3DpZpuesQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 03/14] arm/arm64: gic: Introduce setup_irq() helper Date: Tue, 28 Jan 2020 11:34:48 +0100 Message-Id: <20200128103459.19413-4-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ipi_enable() code would be reusable for other interrupts than IPI. Let's rename it setup_irq() and pass an interrupt handler pointer. Signed-off-by: Eric Auger --- v2 -> v3: - do not export setup_irq anymore --- arm/gic.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index fcf4c1f..abf08c7 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -34,6 +34,7 @@ static struct gic *gic; static int acked[NR_CPUS], spurious[NR_CPUS]; static int bad_sender[NR_CPUS], bad_irq[NR_CPUS]; static cpumask_t ready; +typedef void (*handler_t)(struct pt_regs *regs __unused); =20 static void nr_cpu_check(int nr) { @@ -215,20 +216,20 @@ static void ipi_test_smp(void) report_prefix_pop(); } =20 -static void ipi_enable(void) +static void setup_irq(handler_t handler) { gic_enable_defaults(); #ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_handler); + install_exception_handler(EXCPTN_IRQ, handler); #else - install_irq_handler(EL1H_IRQ, ipi_handler); + install_irq_handler(EL1H_IRQ, handler); #endif local_irq_enable(); } =20 static void ipi_send(void) { - ipi_enable(); + setup_irq(ipi_handler); wait_on_ready(); ipi_test_self(); ipi_test_smp(); @@ -238,7 +239,7 @@ static void ipi_send(void) =20 static void ipi_recv(void) { - ipi_enable(); + setup_irq(ipi_handler); cpumask_set_cpu(smp_processor_id(), &ready); while (1) wfi(); @@ -295,14 +296,7 @@ static void ipi_clear_active_handler(struct pt_regs *r= egs __unused) static void run_active_clear_test(void) { report_prefix_push("active"); - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_clear_active_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_clear_active_handler); -#endif - local_irq_enable(); - + setup_irq(ipi_clear_active_handler); ipi_test_self(); report_prefix_pop(); } --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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bh=zRIDXBcFA1npKL3bY9kDF0a2tZ99w/hj73UnpskP22g=; b=NncEcveZ5rQ2pVAGg+JLS5BCNnelm7wULgNKz7JGRAreCpN46ieSu9DsJb8bHw4xqX4FZ6 sAmHvotCqkXntOLASEC84jg2mPLBeVsTZuAKe4A3PBNi7CBnktOQDESak04PojZT6VZNHs aFzg7tYZ1ddUio6CBDa02oCJGJyY4Jw= X-MC-Unique: BSGEQTgFPAW1HAu62B4BsA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 04/14] arm/arm64: gicv3: Add some re-distributor defines Date: Tue, 28 Jan 2020 11:34:49 +0100 Message-Id: <20200128103459.19413-5-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management. Signed-off-by: Eric Auger Reviewed-by: Zenghui Yu --- lib/arm/asm/gic-v3.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 6beeab6..ffb2e26 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -18,6 +18,7 @@ * We expect to be run in Non-secure mode, thus we define the * group1 enable bits with respect to that view. */ +#define GICD_CTLR 0x0000 #define GICD_CTLR_RWP (1U << 31) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) @@ -36,6 +37,11 @@ #define GICR_ICENABLER0 GICD_ICENABLER #define GICR_IPRIORITYR0 GICD_IPRIORITYR =20 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_CTLR GICD_CTLR +#define GICR_CTLR_ENABLE_LPIS (1UL << 0) + #define ICC_SGI1R_AFFINITY_1_SHIFT 16 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207750; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VjL/t3QoioTtZ5LfoHmXzGDxIVgZKCAFmG6Totk9p/U=; b=VBltZ0jzl6bMzgaofKUVUr896auaBxV4HFbBfUTtlUWj88ENXiQJxWS9vPC4oKzOJeVa2o vQJFuKrS7c1tnsB6fKs7dWwvh00pLyd/zbI+921t1U4J86yk+KsL3HrhckzZrs/8o9iqT4 17tqcS74QCOkFuO3ttTtkSrI9MVrW5E= X-MC-Unique: 7Vk1qhBXPy-ENJDGx-2adw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 05/14] arm/arm64: ITS: Introspection tests Date: Tue, 28 Jan 2020 11:34:50 +0100 Message-Id: <20200128103459.19413-6-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Detect the presence of an ITS as part of the GICv3 init routine, initialize its base address and read few registers the IIDR, the TYPER to store its dimensioning parameters. Also parse the BASER registers. This is our first ITS test, belonging to a new "its" group. Signed-off-by: Eric Auger --- v2 -> v3: - updated dates and changed author - squash "arm/arm64: ITS: Test BASER" into this patch but removes setup_baser which will be introduced later. - only compile on aarch64 - restrict the new test to aarch64 v1 -> v2: - clean GITS_TYPER macros and unused fields in typer struct - remove memory attribute related macros - remove everything related to memory attributes - s/dev_baser/coll_baser/ in report_info - add extra line - removed index filed in its_baser --- arm/Makefile.arm64 | 1 + arm/gic.c | 49 ++++++++++++++++++ arm/unittests.cfg | 7 +++ lib/arm/asm/gic-v3-its.h | 103 +++++++++++++++++++++++++++++++++++++ lib/arm/gic-v3-its.c | 88 +++++++++++++++++++++++++++++++ lib/arm/gic.c | 30 +++++++++-- lib/arm64/asm/gic-v3-its.h | 1 + 7 files changed, 274 insertions(+), 5 deletions(-) create mode 100644 lib/arm/asm/gic-v3-its.h create mode 100644 lib/arm/gic-v3-its.c create mode 100644 lib/arm64/asm/gic-v3-its.h diff --git a/arm/Makefile.arm64 b/arm/Makefile.arm64 index 6d3dc2c..2571ffb 100644 --- a/arm/Makefile.arm64 +++ b/arm/Makefile.arm64 @@ -19,6 +19,7 @@ endef cstart.o =3D $(TEST_DIR)/cstart64.o cflatobjs +=3D lib/arm64/processor.o cflatobjs +=3D lib/arm64/spinlock.o +cflatobjs +=3D lib/arm/gic-v3-its.o =20 OBJDIRS +=3D lib/arm64 =20 diff --git a/arm/gic.c b/arm/gic.c index abf08c7..4d7dd03 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -518,6 +519,50 @@ static void gic_test_mmio(void) test_targets(nr_irqs); } =20 +#if defined(__arm__) + +static void test_its_introspection(void) {} + +#else /* __arch64__ */ + +static void test_its_introspection(void) +{ + struct its_baser *dev_baser, *coll_baser; + struct its_typer *typer =3D &its_data.typer; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return; + } + + /* IIDR */ + report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false), + "GITS_IIDR is read-only"), + + /* TYPER */ + report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false), + "GITS_TYPER is read-only"); + + report(typer->phys_lpi, "ITS supports physical LPIs"); + report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no"); + report_info("ITT entry size =3D 0x%x", typer->ite_size); + report_info("Bit Count: EventID=3D%d DeviceId=3D%d CollId=3D%d", + typer->eventid_bits, typer->deviceid_bits, + typer->collid_bits); + report(typer->eventid_bits && typer->deviceid_bits && + typer->collid_bits, "ID spaces"); + report_info("Target address format %s", + typer->pta ? "Redist basse address" : "PE #"); + + dev_baser =3D its_lookup_baser(GITS_BASER_TYPE_DEVICE); + coll_baser =3D its_lookup_baser(GITS_BASER_TYPE_COLLECTION); + report(dev_baser && coll_baser, "detect device and collection BASER"); + report_info("device baser entry_size =3D 0x%x", dev_baser->esz); + report_info("collection baser entry_size =3D 0x%x", coll_baser->esz); +} + +#endif + int main(int argc, char **argv) { if (!gic_init()) { @@ -549,6 +594,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); gic_test_mmio(); report_prefix_pop(); + } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { + report_prefix_push(argv[1]); + test_its_introspection(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index daeb5a0..ba2b31b 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -122,6 +122,13 @@ smp =3D $MAX_SMP extra_params =3D -machine gic-version=3D3 -append 'active' groups =3D gic =20 +[its-introspection] +file =3D gic.flat +smp =3D $MAX_SMP +extra_params =3D -machine gic-version=3D3 -append 'its-introspection' +groups =3D its +arch =3D arm64 + # Test PSCI emulation [psci] file =3D psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h new file mode 100644 index 0000000..815c515 --- /dev/null +++ b/lib/arm/asm/gic-v3-its.h @@ -0,0 +1,103 @@ +/* + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h + * + * Copyright (C) 2020, Red Hat Inc, Eric Auger + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_V3_ITS_H_ +#define _ASMARM_GIC_V3_ITS_H_ + +#ifndef __ASSEMBLY__ + +struct its_typer { + unsigned int ite_size; + unsigned int eventid_bits; + unsigned int deviceid_bits; + unsigned int collid_bits; + bool pta; + bool phys_lpi; + bool virt_lpi; +}; + +struct its_baser { + int type; + size_t psz; + int nr_pages; + bool indirect; + phys_addr_t table_addr; + bool valid; + int esz; +}; + +#define GITS_BASER_NR_REGS 8 + +struct its_data { + void *base; + struct its_typer typer; + struct its_baser baser[GITS_BASER_NR_REGS]; +}; + +extern struct its_data its_data; + +#define gicv3_its_base() (its_data.base) + +#if defined(__aarch64__) + +#define GITS_CTLR 0x0000 +#define GITS_IIDR 0x0004 +#define GITS_TYPER 0x0008 +#define GITS_CBASER 0x0080 +#define GITS_CWRITER 0x0088 +#define GITS_CREADR 0x0090 +#define GITS_BASER 0x0100 + +#define GITS_TYPER_PLPIS BIT(0) +#define GITS_TYPER_VLPIS BIT(1) +#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) +#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 +#define GITS_TYPER_IDBITS GENMASK_ULL(8, 12) +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_DEVBITS GENMASK_ULL(13, 17) +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_PTA BIT(19) +#define GITS_TYPER_CIDBITS GENMASK_ULL(32, 35) +#define GITS_TYPER_CIDBITS_SHIFT 32 +#define GITS_TYPER_CIL BIT(36) + +#define GITS_CTLR_ENABLE (1U << 0) + +#define GITS_CBASER_VALID (1UL << 63) + +#define GITS_BASER_VALID BIT(63) +#define GITS_BASER_INDIRECT BIT(62) +#define GITS_BASER_TYPE_SHIFT (56) +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) +#define GITS_BASER_ENTRY_SIZE_SHIFT (48) +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & = 0x1f) + 1) +#define GITS_BASER_PAGE_SIZE_SHIFT (8) +#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGES_MAX 256 +#define GITS_BASER_PAGES_SHIFT (0) +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000 +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_COLLECTION 4 + +extern void its_parse_typer(void); +extern void its_init(void); +extern int its_parse_baser(int i, struct its_baser *baser); +extern struct its_baser *its_lookup_baser(int type); + +#else /* __arm__ */ + +static inline void its_init(void) {} + +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c new file mode 100644 index 0000000..2c0ce13 --- /dev/null +++ b/lib/arm/gic-v3-its.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2020, Red Hat Inc, Eric Auger + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include +#include + +void its_parse_typer(void) +{ + u64 typer =3D readq(gicv3_its_base() + GITS_TYPER); + + its_data.typer.ite_size =3D ((typer & GITS_TYPER_ITT_ENTRY_SIZE) >> + GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) + 1; + its_data.typer.pta =3D typer & GITS_TYPER_PTA; + its_data.typer.eventid_bits =3D ((typer & GITS_TYPER_IDBITS) >> + GITS_TYPER_IDBITS_SHIFT) + 1; + its_data.typer.deviceid_bits =3D ((typer & GITS_TYPER_DEVBITS) >> + GITS_TYPER_DEVBITS_SHIFT) + 1; + + if (typer & GITS_TYPER_CIL) + its_data.typer.collid_bits =3D ((typer & GITS_TYPER_CIDBITS) >> + GITS_TYPER_CIDBITS_SHIFT) + 1; + else + its_data.typer.collid_bits =3D 16; + + its_data.typer.virt_lpi =3D typer & GITS_TYPER_VLPIS; + its_data.typer.phys_lpi =3D typer & GITS_TYPER_PLPIS; +} + +int its_parse_baser(int i, struct its_baser *baser) +{ + void *reg_addr =3D gicv3_its_base() + GITS_BASER + i * 8; + u64 val =3D readq(reg_addr); + + if (!val) { + memset(baser, 0, sizeof(*baser)); + return -1; + } + + baser->valid =3D val & GITS_BASER_VALID; + baser->indirect =3D val & GITS_BASER_INDIRECT; + baser->type =3D GITS_BASER_TYPE(val); + baser->esz =3D GITS_BASER_ENTRY_SIZE(val); + baser->nr_pages =3D GITS_BASER_NR_PAGES(val); + baser->table_addr =3D val & GITS_BASER_PHYS_ADDR_MASK; + switch (val & GITS_BASER_PAGE_SIZE_MASK) { + case GITS_BASER_PAGE_SIZE_4K: + baser->psz =3D SZ_4K; + break; + case GITS_BASER_PAGE_SIZE_16K: + baser->psz =3D SZ_16K; + break; + case GITS_BASER_PAGE_SIZE_64K: + baser->psz =3D SZ_64K; + break; + default: + baser->psz =3D SZ_64K; + } + return 0; +} + +struct its_baser *its_lookup_baser(int type) +{ + int i; + + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser =3D &its_data.baser[i]; + + if (baser->type =3D=3D type) + return baser; + } + return NULL; +} + +void its_init(void) +{ + int i; + + if (!its_data.base) + return; + + its_parse_typer(); + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) + its_parse_baser(i, &its_data.baser[i]); +} + diff --git a/lib/arm/gic.c b/lib/arm/gic.c index aa9cb86..6b70b05 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -6,9 +6,11 @@ #include #include #include +#include =20 struct gicv2_data gicv2_data; struct gicv3_data gicv3_data; +struct its_data its_data; =20 struct gic_common_ops { void (*enable_defaults)(void); @@ -44,12 +46,13 @@ static const struct gic_common_ops gicv3_common_ops =3D= { * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt */ static bool -gic_get_dt_bases(const char *compatible, void **base1, void **base2) +gic_get_dt_bases(const char *compatible, void **base1, void **base2, void = **base3) { struct dt_pbus_reg reg; - struct dt_device gic; + struct dt_device gic, its; struct dt_bus bus; - int node, ret, i; + int node, subnode, ret, i, len; + const void *fdt =3D dt_fdt(); =20 dt_bus_init_defaults(&bus); dt_device_init(&gic, &bus, NULL); @@ -74,19 +77,35 @@ gic_get_dt_bases(const char *compatible, void **base1, = void **base2) base2[i] =3D ioremap(reg.addr, reg.size); } =20 + if (base3 && !strcmp(compatible, "arm,gic-v3")) { + dt_for_each_subnode(node, subnode) { + const struct fdt_property *prop; + + prop =3D fdt_get_property(fdt, subnode, "compatible", &len); + if (!strcmp((char *)prop->data, "arm,gic-v3-its")) { + dt_device_bind_node(&its, subnode); + ret =3D dt_pbus_translate(&its, 0, ®); + assert(ret =3D=3D 0); + *base3 =3D ioremap(reg.addr, reg.size); + break; + } + } + + } + return true; } =20 int gicv2_init(void) { return gic_get_dt_bases("arm,cortex-a15-gic", - &gicv2_data.dist_base, &gicv2_data.cpu_base); + &gicv2_data.dist_base, &gicv2_data.cpu_base, NULL); } =20 int gicv3_init(void) { return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base, - &gicv3_data.redist_bases[0]); + &gicv3_data.redist_bases[0], &its_data.base); } =20 int gic_version(void) @@ -104,6 +123,7 @@ int gic_init(void) gic_common_ops =3D &gicv2_common_ops; else if (gicv3_init()) gic_common_ops =3D &gicv3_common_ops; + its_init(); return gic_version(); } =20 diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h new file mode 100644 index 0000000..083cba4 --- /dev/null +++ b/lib/arm64/asm/gic-v3-its.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic-v3-its.h" --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580207879937609.1842440929609; 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Tue, 28 Jan 2020 05:35:59 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EB2C41005513; Tue, 28 Jan 2020 10:35:57 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1B9061001B08; Tue, 28 Jan 2020 10:35:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207761; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pu5G8euGek2YOgV/Xm7PleFVJneOrBcGo10vPoYLEG0=; b=hYRn4BGA8pXPK+kRH+gssLWINxQLJOM9vrCNLyEA/fjAaM4tEH2TkyvfQRuRORSUp+UGwJ RrxurqJvjlD0Us642doo5YtHqrWsi9KYgS9JLUXc/RjUyc1DOGZFMjxcBImDyYqvyrXBq4 MSAYpNbxqdzKhQwEgVdogZ79gLgoi/A= X-MC-Unique: jOExBHJ_PC2UojAYgGWC_g-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 06/14] arm/arm64: gicv3: Set the LPI config and pending tables Date: Tue, 28 Jan 2020 11:34:51 +0100 Message-Id: <20200128103459.19413-7-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table. Also introduce a helper routine that allows to set the pending table bit for a given LPI. Signed-off-by: Eric Auger --- v2 -> v3: - Move the helpers in lib/arm/gic-v3.c and prefix them with "gicv3_" and add _lpi prefix too v1 -> v2: - remove memory attributes --- lib/arm/asm/gic-v3.h | 16 +++++++++++ lib/arm/gic-v3.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index ffb2e26..ec2a6f0 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -48,6 +48,16 @@ #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level #= # _SHIFT) =20 +#define GICR_PROPBASER_IDBITS_MASK (0x1f) + +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define LPI_PROP_GROUP1 (1 << 1) +#define LPI_PROP_ENABLED (1 << 0) +#define LPI_PROP_DEFAULT_PRIO 0xa0 +#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | \ + LPI_PROP_ENABLED) + #include =20 #ifndef __ASSEMBLY__ @@ -64,6 +74,8 @@ struct gicv3_data { void *dist_base; void *redist_bases[GICV3_NR_REDISTS]; void *redist_base[NR_CPUS]; + void *lpi_prop; + void *lpi_pend[NR_CPUS]; unsigned int irq_nr; }; extern struct gicv3_data gicv3_data; @@ -80,6 +92,10 @@ extern void gicv3_write_eoir(u32 irqstat); extern void gicv3_ipi_send_single(int irq, int cpu); extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest); extern void gicv3_set_redist_base(size_t stride); +extern void gicv3_lpi_set_config(int n, u8 val); +extern u8 gicv3_lpi_get_config(int n); +extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set); +extern void gicv3_lpi_alloc_tables(void); =20 static inline void gicv3_do_wait_for_rwp(void *base) { diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index feecb5e..c33f883 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -5,6 +5,7 @@ */ #include #include +#include =20 void gicv3_set_redist_base(size_t stride) { @@ -147,3 +148,66 @@ void gicv3_ipi_send_single(int irq, int cpu) cpumask_set_cpu(cpu, &dest); gicv3_ipi_send_mask(irq, &dest); } + +#if defined(__aarch64__) +/* alloc_lpi_tables: Allocate LPI config and pending tables */ +void gicv3_lpi_alloc_tables(void) +{ + unsigned long n =3D SZ_64K >> PAGE_SHIFT; + unsigned long order =3D fls(n); + u64 prop_val; + int cpu; + + gicv3_data.lpi_prop =3D (void *)virt_to_phys(alloc_pages(order)); + + /* ID bits =3D 13, ie. up to 14b LPI INTID */ + prop_val =3D (u64)gicv3_data.lpi_prop | 13; + + /* + * Allocate pending tables for each redistributor + * and set PROPBASER and PENDBASER + */ + for_each_present_cpu(cpu) { + u64 pend_val; + void *ptr; + + ptr =3D gicv3_data.redist_base[cpu]; + + writeq(prop_val, ptr + GICR_PROPBASER); + + gicv3_data.lpi_pend[cpu] =3D (void *)virt_to_phys(alloc_pages(order)); + + pend_val =3D (u64)gicv3_data.lpi_pend[cpu]; + + writeq(pend_val, ptr + GICR_PENDBASER); + } +} + +void gicv3_lpi_set_config(int n, u8 value) +{ + u8 *entry =3D (u8 *)(gicv3_data.lpi_prop + (n - 8192)); + + *entry =3D value; +} + +u8 gicv3_lpi_get_config(int n) +{ + u8 *entry =3D (u8 *)(gicv3_data.lpi_prop + (n - 8192)); + + return *entry; +} + +void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set) +{ + u8 *ptr =3D phys_to_virt((phys_addr_t)gicv3_data.lpi_pend[rdist]); + u8 mask =3D 1 << (n % 8), byte; + + ptr +=3D (n / 8); + byte =3D *ptr; + if (set) + byte |=3D mask; + else + byte &=3D ~mask; + *ptr =3D byte; +} +#endif /* __aarch64__ */ --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580207851723998.5855012335005; Tue, 28 Jan 2020 02:37:31 -0800 (PST) Received: from localhost ([::1]:56642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOFO-000248-Nl for importer@patchew.org; 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Tue, 28 Jan 2020 10:36:05 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 50F401001DD8; Tue, 28 Jan 2020 10:35:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207781; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=78G0omYBZtnhpn3J/dduj+Q41/b0ahCr4I2teh8jw18=; b=Y8wufg168fsx2zz69IBuywVl65yAc3CR4GfPfE6tpMgYpRGUdGemsjNtMuZl8YvVugyWbM 9gZhEfUZd1PyVnqaWPi9Y1wStYRO1iVgp5zXCq3s5o4KMW/5WU1Hb9ztxAboU0PgrqzRhJ gNXcTk6u849euCuhUVo0eXbyBcj6Ip4= X-MC-Unique: QHcEkjAAPcSg6VQP7dxRFA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 07/14] arm/arm64: gicv3: Enable/Disable LPIs at re-distributor level Date: Tue, 28 Jan 2020 11:34:52 +0100 Message-Id: <20200128103459.19413-8-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This helper function controls the signaling of LPIs at redistributor level. Signed-off-by: Eric Auger --- v2 -> v3: - move the helper in lib/arm/gic-v3.c - rename the function with gicv3_lpi_ prefix - s/report_abort/assert --- lib/arm/asm/gic-v3.h | 1 + lib/arm/gic-v3.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index ec2a6f0..734c0c0 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -96,6 +96,7 @@ extern void gicv3_lpi_set_config(int n, u8 val); extern u8 gicv3_lpi_get_config(int n); extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set); extern void gicv3_lpi_alloc_tables(void); +extern void gicv3_lpi_rdist_ctrl(u32 redist, bool set); =20 static inline void gicv3_do_wait_for_rwp(void *base) { diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index c33f883..7865d01 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -210,4 +210,21 @@ void gicv3_lpi_set_pending_table_bit(int rdist, int n,= bool set) byte &=3D ~mask; *ptr =3D byte; } + +void gicv3_lpi_rdist_ctrl(u32 redist, bool set) +{ + void *ptr; + u64 val; + + assert(redist < nr_cpus); + + ptr =3D gicv3_data.redist_base[redist]; + val =3D readl(ptr + GICR_CTLR); + if (set) + val |=3D GICR_CTLR_ENABLE_LPIS; + else + val &=3D ~GICR_CTLR_ENABLE_LPIS; + writel(val, ptr + GICR_CTLR); +} #endif /* __aarch64__ */ + --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580208063299979.1684093756035; Tue, 28 Jan 2020 02:41:03 -0800 (PST) Received: from localhost ([::1]:56738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOIo-0001kd-8x for importer@patchew.org; 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Tue, 28 Jan 2020 10:36:15 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8F6981001B30; Tue, 28 Jan 2020 10:36:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207778; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=54NPiD/s7NhXdHaaTgCUqqDcRiDlHdCFtYHnxyYOpT4=; b=VfU4+uf0eGdW8Nsk1hU2aAaus7IH2Br4UmxWhIj22nxKG+nBUN+byu//5H/uG2B/c6Iw+I oPYRuWLp0DT5hdH6KLjzi8z6RZj92xrBTNaCAx3sla2wP40OgSaAJZpfvfLq5cMnlD8sQX bsq3pnktRa/p/FPblFKkjmbETIIZvK4= X-MC-Unique: rD51XNLdNO2IvgzW0-stYg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 08/14] arm/arm64: ITS: its_enable_defaults Date: Tue, 28 Jan 2020 11:34:53 +0100 Message-Id: <20200128103459.19413-9-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" its_enable_defaults() is the top init function that allocates the command queue and all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level. gicv3_enable_defaults must be called before. Signed-off-by: Eric Auger --- v2 -> v3: - introduce its_setup_baser in this patch - squash "arm/arm64: ITS: Init the command queue" in this patch. --- lib/arm/asm/gic-v3-its.h | 8 ++++ lib/arm/gic-v3-its.c | 89 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 815c515..fe73c04 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -36,6 +36,8 @@ struct its_data { void *base; struct its_typer typer; struct its_baser baser[GITS_BASER_NR_REGS]; + struct its_cmd_block *cmd_base; + struct its_cmd_block *cmd_write; }; =20 extern struct its_data its_data; @@ -88,10 +90,16 @@ extern struct its_data its_data; #define GITS_BASER_TYPE_DEVICE 1 #define GITS_BASER_TYPE_COLLECTION 4 =20 + +struct its_cmd_block { + u64 raw_cmd[4]; +}; + extern void its_parse_typer(void); extern void its_init(void); extern int its_parse_baser(int i, struct its_baser *baser); extern struct its_baser *its_lookup_baser(int type); +extern void its_enable_defaults(void); =20 #else /* __arm__ */ =20 diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 2c0ce13..d1e7e52 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -86,3 +86,92 @@ void its_init(void) its_parse_baser(i, &its_data.baser[i]); } =20 +static void its_setup_baser(int i, struct its_baser *baser) +{ + unsigned long n =3D (baser->nr_pages * baser->psz) >> PAGE_SHIFT; + unsigned long order =3D is_power_of_2(n) ? fls(n) : fls(n) + 1; + u64 val; + + baser->table_addr =3D (u64)virt_to_phys(alloc_pages(order)); + + val =3D ((u64)baser->table_addr | + ((u64)baser->type << GITS_BASER_TYPE_SHIFT) | + ((u64)(baser->esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | + ((baser->nr_pages - 1) << GITS_BASER_PAGES_SHIFT) | + (u64)baser->indirect << 62 | + (u64)baser->valid << 63); + + switch (baser->psz) { + case SZ_4K: + val |=3D GITS_BASER_PAGE_SIZE_4K; + break; + case SZ_16K: + val |=3D GITS_BASER_PAGE_SIZE_16K; + break; + case SZ_64K: + val |=3D GITS_BASER_PAGE_SIZE_64K; + break; + } + + writeq(val, gicv3_its_base() + GITS_BASER + i * 8); +} + +/** + * init_cmd_queue: Allocate the command queue and initialize + * CBASER, CREADR, CWRITER + */ +static void its_cmd_queue_init(void) +{ + unsigned long n =3D SZ_64K >> PAGE_SHIFT; + unsigned long order =3D fls(n); + u64 cbaser; + + its_data.cmd_base =3D (void *)virt_to_phys(alloc_pages(order)); + + cbaser =3D ((u64)its_data.cmd_base | (SZ_64K / SZ_4K - 1) | GITS_CBASER_V= ALID); + + writeq(cbaser, its_data.base + GITS_CBASER); + + its_data.cmd_write =3D its_data.cmd_base; + writeq(0, its_data.base + GITS_CWRITER); +} + +void its_enable_defaults(void) +{ + unsigned int i; + + its_parse_typer(); + + /* Allocate BASER tables (device and collection tables) */ + for (i =3D 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser =3D &its_data.baser[i]; + int ret; + + ret =3D its_parse_baser(i, baser); + if (ret) + continue; + + switch (baser->type) { + case GITS_BASER_TYPE_DEVICE: + baser->valid =3D true; + its_setup_baser(i, baser); + break; + case GITS_BASER_TYPE_COLLECTION: + baser->valid =3D true; + its_setup_baser(i, baser); + break; + default: + break; + } + } + + /* Allocate LPI config and pending tables */ + gicv3_lpi_alloc_tables(); + + its_cmd_queue_init(); + + for (i =3D 0; i < nr_cpus; i++) + gicv3_lpi_rdist_ctrl(i, true); + + writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); +} --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580207940252857.994994883173; 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Tue, 28 Jan 2020 05:36:23 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EF2DBDB60; Tue, 28 Jan 2020 10:36:21 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 362721001B30; Tue, 28 Jan 2020 10:36:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207784; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ubJcGFSByeAYXmA6ZsXY2QS9ypGCX/uJRAkeSeWnSn8=; b=VMiVe/VqFrKk6NmSlA40m/C+r/RWn0kCknQprKrxU2IR+66z1bZwwN3Nn/q5Y6kWXj2+xN PUYrKBWGZX9REw+8gJvRDV3nWIDoGqKhOQrnqsYd7gz6wi53+nHvaNuECAVZBsPHtfQKLF SjUjf2CLXbymAnaKLny8OU9Nhl0jQlU= X-MC-Unique: DQXSTh9CMxKCq8ZczajPmw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 09/14] arm/arm64: ITS: Device and collection Initialization Date: Tue, 28 Jan 2020 11:34:54 +0100 Message-Id: <20200128103459.19413-10-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Introduce an helper functions to register - a new device, characterized by its device id and the max number of event IDs that dimension its ITT (Interrupt Translation Table). The function allocates the ITT. - a new collection, characterized by its ID and the target processing engine (PE). Signed-off-by: Eric Auger --- v2 -> v3: - s/report_abort/assert v1 -> v2: - s/nb_/nr_ --- lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++- lib/arm/gic-v3-its.c | 44 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index fe73c04..acd97a9 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -31,6 +31,19 @@ struct its_baser { }; =20 #define GITS_BASER_NR_REGS 8 +#define GITS_MAX_DEVICES 8 +#define GITS_MAX_COLLECTIONS 8 + +struct its_device { + u32 device_id; /* device ID */ + u32 nr_ites; /* Max Interrupt Translation Entries */ + void *itt; /* Interrupt Translation Table GPA */ +}; + +struct its_collection { + u64 target_address; + u16 col_id; +}; =20 struct its_data { void *base; @@ -38,6 +51,10 @@ struct its_data { struct its_baser baser[GITS_BASER_NR_REGS]; struct its_cmd_block *cmd_base; struct its_cmd_block *cmd_write; + struct its_device devices[GITS_MAX_DEVICES]; + u32 nr_devices; /* Allocated Devices */ + struct its_collection collections[GITS_MAX_COLLECTIONS]; + u32 nr_collections; /* Allocated Collections */ }; =20 extern struct its_data its_data; @@ -90,7 +107,6 @@ extern struct its_data its_data; #define GITS_BASER_TYPE_DEVICE 1 #define GITS_BASER_TYPE_COLLECTION 4 =20 - struct its_cmd_block { u64 raw_cmd[4]; }; @@ -100,6 +116,8 @@ extern void its_init(void); extern int its_parse_baser(int i, struct its_baser *baser); extern struct its_baser *its_lookup_baser(int type); extern void its_enable_defaults(void); +extern struct its_device *its_create_device(u32 dev_id, int nr_ites); +extern struct its_collection *its_create_collection(u32 col_id, u32 target= _pe); =20 #else /* __arm__ */ =20 diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index d1e7e52..c2dcd01 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -175,3 +175,47 @@ void its_enable_defaults(void) =20 writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); } + +struct its_device *its_create_device(u32 device_id, int nr_ites) +{ + struct its_baser *baser; + struct its_device *new; + unsigned long n, order; + + assert(its_data.nr_devices < GITS_MAX_DEVICES); + + baser =3D its_lookup_baser(GITS_BASER_TYPE_DEVICE); + if (!baser) + return NULL; + + new =3D &its_data.devices[its_data.nr_devices]; + + new->device_id =3D device_id; + new->nr_ites =3D nr_ites; + + n =3D (its_data.typer.ite_size * nr_ites) >> PAGE_SHIFT; + order =3D is_power_of_2(n) ? fls(n) : fls(n) + 1; + new->itt =3D (void *)virt_to_phys(alloc_pages(order)); + + its_data.nr_devices++; + return new; +} + +struct its_collection *its_create_collection(u32 col_id, u32 pe) +{ + struct its_collection *new; + + assert(its_data.nr_collections < GITS_MAX_COLLECTIONS); + + new =3D &its_data.collections[its_data.nr_collections]; + + new->col_id =3D col_id; + + if (its_data.typer.pta) + new->target_address =3D (u64)gicv3_data.redist_base[pe]; + else + new->target_address =3D pe << 16; + + its_data.nr_collections++; + return new; +} --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580208152411590.1025910887142; Tue, 28 Jan 2020 02:42:32 -0800 (PST) Received: from localhost ([::1]:56776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOKF-0004Qr-A9 for importer@patchew.org; Tue, 28 Jan 2020 05:42:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48375) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOEV-0000nY-3n for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwOET-0000jk-10 for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:35 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:45222 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iwOES-0000jX-TI for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:32 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-9-U2jGCtRmO8iAIYcIG8p_xg-1; Tue, 28 Jan 2020 05:36:30 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A0EED107ACC5; Tue, 28 Jan 2020 10:36:28 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id AD7B01001B30; Tue, 28 Jan 2020 10:36:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207792; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AMnFoycaRqVR3q3J7wrgsZqqrGsLu5esjXYok9mZrus=; b=TZpmxGltZt4HxLtBuMjN5qrT3eOxMsIB56eLvj+xSJhe1Gkghays+uUFkC7I/7wjIeFCRu 3pF50oQXRzuWqdd8CW79lHwl2VU8Uao+/ucsGNKlbFhHHBIDLoE4kReOKNywhULp3fmsNo eaFhTQbgv8OMSso7QvpSTij76yBJI+8= X-MC-Unique: U2jGCtRmO8iAIYcIG8p_xg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 10/14] arm/arm64: ITS: commands Date: Tue, 28 Jan 2020 11:34:55 +0100 Message-Id: <20200128103459.19413-11-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Implement main ITS commands. The code is largely inherited from the ITS driver. Signed-off-by: Eric Auger --- v2 -> v3: - do not use report() anymore - assert if cmd_write exceeds the queue capacity v1 -> v2: - removed its_print_cmd_state --- arm/Makefile.arm64 | 2 +- lib/arm/asm/gic-v3-its.h | 38 +++- lib/arm/gic-v3-its-cmd.c | 454 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 492 insertions(+), 2 deletions(-) create mode 100644 lib/arm/gic-v3-its-cmd.c diff --git a/arm/Makefile.arm64 b/arm/Makefile.arm64 index 2571ffb..d12aea5 100644 --- a/arm/Makefile.arm64 +++ b/arm/Makefile.arm64 @@ -19,7 +19,7 @@ endef cstart.o =3D $(TEST_DIR)/cstart64.o cflatobjs +=3D lib/arm64/processor.o cflatobjs +=3D lib/arm64/spinlock.o -cflatobjs +=3D lib/arm/gic-v3-its.o +cflatobjs +=3D lib/arm/gic-v3-its.o lib/arm/gic-v3-its-cmd.o =20 OBJDIRS +=3D lib/arm64 =20 diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index acd97a9..0e5c5b6 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -45,6 +45,8 @@ struct its_collection { u16 col_id; }; =20 +struct its_cmd_block; + struct its_data { void *base; struct its_typer typer; @@ -107,6 +109,24 @@ extern struct its_data its_data; #define GITS_BASER_TYPE_DEVICE 1 #define GITS_BASER_TYPE_COLLECTION 4 =20 +/* + * ITS commands + */ +#define GITS_CMD_MAPD 0x08 +#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_MAPTI 0x0a +/* older GIC documentation used MAPVI for this command */ +#define GITS_CMD_MAPVI GITS_CMD_MAPTI +#define GITS_CMD_MAPI 0x0b +#define GITS_CMD_MOVI 0x01 +#define GITS_CMD_DISCARD 0x0f +#define GITS_CMD_INV 0x0c +#define GITS_CMD_MOVALL 0x0e +#define GITS_CMD_INVALL 0x0d +#define GITS_CMD_INT 0x03 +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_SYNC 0x05 + struct its_cmd_block { u64 raw_cmd[4]; }; @@ -119,11 +139,27 @@ extern void its_enable_defaults(void); extern struct its_device *its_create_device(u32 dev_id, int nr_ites); extern struct its_collection *its_create_collection(u32 col_id, u32 target= _pe); =20 +extern void its_send_mapd(struct its_device *dev, int valid); +extern void its_send_mapc(struct its_collection *col, int valid); +extern void its_send_mapti(struct its_device *dev, u32 irq_id, + u32 event_id, struct its_collection *col); +extern void its_send_int(struct its_device *dev, u32 event_id); +extern void its_send_inv(struct its_device *dev, u32 event_id); +extern void its_send_discard(struct its_device *dev, u32 event_id); +extern void its_send_clear(struct its_device *dev, u32 event_id); +extern void its_send_invall(struct its_collection *col); +extern void its_send_movi(struct its_device *dev, + struct its_collection *col, u32 id); +extern void its_send_sync(struct its_collection *col); + +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) +#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) +#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) + #else /* __arm__ */ =20 static inline void its_init(void) {} =20 #endif - #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its-cmd.c b/lib/arm/gic-v3-its-cmd.c new file mode 100644 index 0000000..fb4364c --- /dev/null +++ b/lib/arm/gic-v3-its-cmd.c @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2020, Red Hat Inc, Eric Auger + * + * Most of the code is copy-pasted from: + * drivers/irqchip/irq-gic-v3-its.c + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include +#include + +#define ITS_ITT_ALIGN SZ_256 + +static const char * const its_cmd_string[] =3D { + [GITS_CMD_MAPD] =3D "MAPD", + [GITS_CMD_MAPC] =3D "MAPC", + [GITS_CMD_MAPTI] =3D "MAPTI", + [GITS_CMD_MAPI] =3D "MAPI", + [GITS_CMD_MOVI] =3D "MOVI", + [GITS_CMD_DISCARD] =3D "DISCARD", + [GITS_CMD_INV] =3D "INV", + [GITS_CMD_MOVALL] =3D "MOVALL", + [GITS_CMD_INVALL] =3D "INVALL", + [GITS_CMD_INT] =3D "INT", + [GITS_CMD_CLEAR] =3D "CLEAR", + [GITS_CMD_SYNC] =3D "SYNC", +}; + +struct its_cmd_desc { + union { + struct { + struct its_device *dev; + u32 event_id; + } its_inv_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_int_cmd; + + struct { + struct its_device *dev; + bool valid; + } its_mapd_cmd; + + struct { + struct its_collection *col; + bool valid; + } its_mapc_cmd; + + struct { + struct its_device *dev; + u32 phys_id; + u32 event_id; + u32 col_id; + } its_mapti_cmd; + + struct { + struct its_device *dev; + struct its_collection *col; + u32 event_id; + } its_movi_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_discard_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_clear_cmd; + + struct { + struct its_collection *col; + } its_invall_cmd; + + struct { + struct its_collection *col; + } its_sync_cmd; + }; +}; + +typedef void (*its_cmd_builder_t)(struct its_cmd_block *, + struct its_cmd_desc *); + +/* ITS COMMANDS */ + +static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) +{ + cmd->raw_cmd[0] &=3D ~0xffUL; + cmd->raw_cmd[0] |=3D cmd_nr; +} + +static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) +{ + cmd->raw_cmd[0] &=3D BIT_ULL(32) - 1; + cmd->raw_cmd[0] |=3D ((u64)devid) << 32; +} + +static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) +{ + cmd->raw_cmd[1] &=3D ~0xffffffffUL; + cmd->raw_cmd[1] |=3D id; +} + +static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) +{ + cmd->raw_cmd[1] &=3D 0xffffffffUL; + cmd->raw_cmd[1] |=3D ((u64)phys_id) << 32; +} + +static void its_encode_size(struct its_cmd_block *cmd, u8 size) +{ + cmd->raw_cmd[1] &=3D ~0x1fUL; + cmd->raw_cmd[1] |=3D size & 0x1f; +} + +static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) +{ + cmd->raw_cmd[2] &=3D ~0xffffffffffffUL; + cmd->raw_cmd[2] |=3D itt_addr & 0xffffffffff00UL; +} + +static void its_encode_valid(struct its_cmd_block *cmd, int valid) +{ + cmd->raw_cmd[2] &=3D ~(1UL << 63); + cmd->raw_cmd[2] |=3D ((u64)!!valid) << 63; +} + +static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) +{ + cmd->raw_cmd[2] &=3D ~(0xfffffffffUL << 16); + cmd->raw_cmd[2] |=3D (target_addr & (0xffffffffUL << 16)); +} + +static void its_encode_collection(struct its_cmd_block *cmd, u16 col) +{ + cmd->raw_cmd[2] &=3D ~0xffffUL; + cmd->raw_cmd[2] |=3D col; +} + +static inline void its_fixup_cmd(struct its_cmd_block *cmd) +{ + /* Let's fixup BE commands */ + cmd->raw_cmd[0] =3D cpu_to_le64(cmd->raw_cmd[0]); + cmd->raw_cmd[1] =3D cpu_to_le64(cmd->raw_cmd[1]); + cmd->raw_cmd[2] =3D cpu_to_le64(cmd->raw_cmd[2]); + cmd->raw_cmd[3] =3D cpu_to_le64(cmd->raw_cmd[3]); +} + +static u64 its_cmd_ptr_to_offset(struct its_cmd_block *ptr) +{ + return (ptr - its_data.cmd_base) * sizeof(*ptr); +} + +static struct its_cmd_block *its_post_commands(void) +{ + u64 wr =3D its_cmd_ptr_to_offset(its_data.cmd_write); + + writeq(wr, its_data.base + GITS_CWRITER); + return its_data.cmd_write; +} + + +static struct its_cmd_block *its_allocate_entry(void) +{ + struct its_cmd_block *cmd; + + assert((u64)its_data.cmd_write < (u64)its_data.cmd_base + SZ_64K); + cmd =3D its_data.cmd_write++; + return cmd; +} + +static void its_wait_for_range_completion(struct its_cmd_block *from, + struct its_cmd_block *to) +{ + u64 rd_idx, from_idx, to_idx; + u32 count =3D 1000000; /* 1s! */ + + from_idx =3D its_cmd_ptr_to_offset(from); + to_idx =3D its_cmd_ptr_to_offset(to); + while (1) { + rd_idx =3D readq(its_data.base + GITS_CREADR); + if (rd_idx >=3D to_idx || rd_idx < from_idx) + break; + + count--; + if (!count) { + unsigned int cmd_id =3D from->raw_cmd[0] & 0xFF; + + assert_msg(false, "%s timeout!", + cmd_id <=3D 0xF ? its_cmd_string[cmd_id] : + "Unexpected"); + return; + } + cpu_relax(); + udelay(1); + } +} + +static void its_send_single_command(its_cmd_builder_t builder, + struct its_cmd_desc *desc) +{ + struct its_cmd_block *cmd, *next_cmd; + + cmd =3D its_allocate_entry(); + builder(cmd, desc); + next_cmd =3D its_post_commands(); + + its_wait_for_range_completion(cmd, next_cmd); +} + + +static void its_build_mapd_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + unsigned long itt_addr; + u8 size =3D 12; /* 4096 eventids */ + + itt_addr =3D (unsigned long)desc->its_mapd_cmd.dev->itt; + itt_addr =3D ALIGN(itt_addr, ITS_ITT_ALIGN); + + its_encode_cmd(cmd, GITS_CMD_MAPD); + its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); + its_encode_size(cmd, size - 1); + its_encode_itt(cmd, itt_addr); + its_encode_valid(cmd, desc->its_mapd_cmd.valid); + + its_fixup_cmd(cmd); + printf("ITS: MAPD devid=3D%d size =3D 0x%x itt=3D0x%lx valid=3D%d\n", + desc->its_mapd_cmd.dev->device_id, + size, itt_addr, desc->its_mapd_cmd.valid); + +} + +static void its_build_mapc_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MAPC); + its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); + its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); + its_encode_valid(cmd, desc->its_mapc_cmd.valid); + + its_fixup_cmd(cmd); + report_info("MAPC col_id=3D%d target_addr =3D 0x%lx valid=3D%d", + desc->its_mapc_cmd.col->col_id, + desc->its_mapc_cmd.col->target_address, + desc->its_mapc_cmd.valid); +} + +static void its_build_mapti_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MAPTI); + its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); + its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); + its_encode_collection(cmd, desc->its_mapti_cmd.col_id); + + its_fixup_cmd(cmd); + report_info("MAPTI dev_id=3D%d event_id=3D%d -> phys_id=3D%d, col_id=3D%d= ", + desc->its_mapti_cmd.dev->device_id, + desc->its_mapti_cmd.event_id, + desc->its_mapti_cmd.phys_id, + desc->its_mapti_cmd.col_id); +} + +static void its_build_invall_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INVALL); + its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); + + its_fixup_cmd(cmd); + report_info("INVALL col_id=3D%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_clear_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_CLEAR); + its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_clear_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("CLEAR col_id=3D%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_discard_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_DISCARD); + its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_discard_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("DISCARD col_id=3D%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_inv_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INV); + its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_inv_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("INV dev_id=3D%d event_id=3D%d", + desc->its_inv_cmd.dev->device_id, + desc->its_inv_cmd.event_id); +} + +static void its_build_int_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INT); + its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_int_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("INT dev_id=3D%d event_id=3D%d", + desc->its_int_cmd.dev->device_id, + desc->its_int_cmd.event_id); +} + +static void its_build_sync_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_SYNC); + its_encode_target(cmd, desc->its_sync_cmd.col->target_address); + its_fixup_cmd(cmd); + report_info("SYNC target_addr =3D 0x%lx", + desc->its_sync_cmd.col->target_address); +} + +static void its_build_movi_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MOVI); + its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_movi_cmd.event_id); + its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); + + its_fixup_cmd(cmd); + report_info("MOVI dev_id=3D%d event_id =3D %d col_id=3D%d", + desc->its_movi_cmd.dev->device_id, + desc->its_movi_cmd.event_id, + desc->its_movi_cmd.col->col_id); +} + +void its_send_mapd(struct its_device *dev, int valid) +{ + struct its_cmd_desc desc; + + desc.its_mapd_cmd.dev =3D dev; + desc.its_mapd_cmd.valid =3D !!valid; + + its_send_single_command(its_build_mapd_cmd, &desc); +} + +void its_send_mapc(struct its_collection *col, int valid) +{ + struct its_cmd_desc desc; + + desc.its_mapc_cmd.col =3D col; + desc.its_mapc_cmd.valid =3D !!valid; + + its_send_single_command(its_build_mapc_cmd, &desc); +} + +void its_send_mapti(struct its_device *dev, u32 irq_id, + u32 event_id, struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_mapti_cmd.dev =3D dev; + desc.its_mapti_cmd.phys_id =3D irq_id; + desc.its_mapti_cmd.event_id =3D event_id; + desc.its_mapti_cmd.col_id =3D col->col_id; + + its_send_single_command(its_build_mapti_cmd, &desc); +} + +void its_send_int(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_int_cmd.dev =3D dev; + desc.its_int_cmd.event_id =3D event_id; + + its_send_single_command(its_build_int_cmd, &desc); +} + +void its_send_movi(struct its_device *dev, + struct its_collection *col, u32 id) +{ + struct its_cmd_desc desc; + + desc.its_movi_cmd.dev =3D dev; + desc.its_movi_cmd.col =3D col; + desc.its_movi_cmd.event_id =3D id; + + its_send_single_command(its_build_movi_cmd, &desc); +} + +void its_send_invall(struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_invall_cmd.col =3D col; + + its_send_single_command(its_build_invall_cmd, &desc); +} + +void its_send_inv(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_inv_cmd.dev =3D dev; + desc.its_inv_cmd.event_id =3D event_id; + + its_send_single_command(its_build_inv_cmd, &desc); +} + +void its_send_discard(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_discard_cmd.dev =3D dev; + desc.its_discard_cmd.event_id =3D event_id; + + its_send_single_command(its_build_discard_cmd, &desc); +} + +void its_send_clear(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_clear_cmd.dev =3D dev; + desc.its_clear_cmd.event_id =3D event_id; + + its_send_single_command(its_build_clear_cmd, &desc); +} + +void its_send_sync(struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_sync_cmd.col =3D col; + + its_send_single_command(its_build_sync_cmd, &desc); +} + --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580208003180316.26536850080765; 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Tue, 28 Jan 2020 05:36:39 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A6CD3800D50; Tue, 28 Jan 2020 10:36:37 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 694E31001B30; Tue, 28 Jan 2020 10:36:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207800; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S7IyFp9yNNPGRardzvjsfdUtfgsnLQUlfdwQx3hiSAI=; b=A6gwW4gEb+E408Db6/Uh0kcFo7feWYo12Hf4JoWYIvHeCC9DPiUl34AoDkbzHidhLlu2hO sQ+jZNpPNZdZByR8o6Mn0IIWzkX7t6G0hgjdrMqohRw17WMlCiGHJrxlX4Z2HE62oMfccr 2WGYK2QZ0nl6qOjrQhAIcE8tXe3RKc0= X-MC-Unique: 9opVXubhMyK7jMA7Su5sZg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 11/14] arm/arm64: ITS: INT functional tests Date: Tue, 28 Jan 2020 11:34:56 +0100 Message-Id: <20200128103459.19413-12-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Triggers LPIs through the INT command. the test checks the LPI hits the right CPU and triggers the right LPI intid, ie. the translation is correct. Updates to the config table also are tested, along with inv and invall commands. Signed-off-by: Eric Auger --- v2 -> v3: - add comments - keep the report_skip in case there aren't 4 vcpus to be able to run other tests in the its category. - fix the prefix pop - move its_event and its_stats to arm/gic.c --- arm/gic.c | 228 +++++++++++++++++++++++++++++++++++++++++++--- arm/unittests.cfg | 7 ++ 2 files changed, 224 insertions(+), 11 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 4d7dd03..50104b1 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -160,6 +160,87 @@ static void ipi_handler(struct pt_regs *regs __unused) } } =20 +static void setup_irq(handler_t handler) +{ + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, handler); +#else + install_irq_handler(EL1H_IRQ, handler); +#endif + local_irq_enable(); +} + +#if defined(__aarch64__) +struct its_event { + int cpu_id; + int lpi_id; +}; + +struct its_stats { + struct its_event expected; + struct its_event observed; +}; + +static struct its_stats lpi_stats; + +static void lpi_handler(struct pt_regs *regs __unused) +{ + u32 irqstat =3D gic_read_iar(); + int irqnr =3D gic_iar_irqnr(irqstat); + + gic_write_eoir(irqstat); + if (irqnr < 8192) + report(false, "Unexpected non LPI interrupt received"); + smp_rmb(); /* pairs with wmb in lpi_stats_expect */ + lpi_stats.observed.cpu_id =3D smp_processor_id(); + lpi_stats.observed.lpi_id =3D irqnr; + smp_wmb(); /* pairs with rmb in check_lpi_stats */ +} + +static void lpi_stats_expect(int exp_cpu_id, int exp_lpi_id) +{ + lpi_stats.expected.cpu_id =3D exp_cpu_id; + lpi_stats.expected.lpi_id =3D exp_lpi_id; + lpi_stats.observed.cpu_id =3D -1; + lpi_stats.observed.lpi_id =3D -1; + smp_wmb(); /* pairs with rmb in handler */ +} + +static void check_lpi_stats(void) +{ + mdelay(100); + smp_rmb(); /* pairs with wmb in lpi_handler */ + if ((lpi_stats.observed.cpu_id !=3D lpi_stats.expected.cpu_id) || + (lpi_stats.observed.lpi_id !=3D lpi_stats.expected.lpi_id)) { + if (lpi_stats.observed.cpu_id =3D=3D -1 && + lpi_stats.observed.lpi_id =3D=3D -1) { + report(false, + "No LPI received whereas (cpuid=3D%d, intid=3D%d) " + "was expected", lpi_stats.expected.cpu_id, + lpi_stats.expected.lpi_id); + } else { + report(false, "Unexpected LPI (cpuid=3D%d, intid=3D%d)", + lpi_stats.observed.cpu_id, + lpi_stats.observed.lpi_id); + } + } else if (lpi_stats.expected.lpi_id !=3D -1) { + report(true, "LPI %d on CPU %d", lpi_stats.observed.lpi_id, + lpi_stats.observed.cpu_id); + } else { + report(true, "no LPI received, as expected"); + } +} + +static void secondary_lpi_test(void) +{ + setup_irq(lpi_handler); + cpumask_set_cpu(smp_processor_id(), &ready); + while (1) + wfi(); +} +#endif + static void gicv2_ipi_send_self(void) { writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); @@ -217,17 +298,6 @@ static void ipi_test_smp(void) report_prefix_pop(); } =20 -static void setup_irq(handler_t handler) -{ - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, handler); -#else - install_irq_handler(EL1H_IRQ, handler); -#endif - local_irq_enable(); -} - static void ipi_send(void) { setup_irq(ipi_handler); @@ -522,6 +592,7 @@ static void gic_test_mmio(void) #if defined(__arm__) =20 static void test_its_introspection(void) {} +static void test_its_trigger(void) {} =20 #else /* __arch64__ */ =20 @@ -561,6 +632,137 @@ static void test_its_introspection(void) report_info("collection baser entry_size =3D 0x%x", coll_baser->esz); } =20 +static bool its_prerequisites(int nb_cpus) +{ + int cpu; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return true; + } + + if (nr_cpus < 4) { + report_skip("Test requires at least %d vcpus", nb_cpus); + return true; + } + + stats_reset(); + + setup_irq(lpi_handler); + + for_each_present_cpu(cpu) { + if (cpu =3D=3D 0) + continue; + smp_boot_secondary(cpu, secondary_lpi_test); + } + wait_on_ready(); + + its_enable_defaults(); + + lpi_stats_expect(-1, -1); + check_lpi_stats(); + + return false; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_prerequisites(4)) + return; + + dev2 =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); + dev7 =3D its_create_device(7 /* dev id */, 8 /* nb_ites */); + + col3 =3D its_create_collection(3 /* col id */, 3/* target PE */); + col2 =3D its_create_collection(2 /* col id */, 2/* target PE */); + + gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT); + gicv3_lpi_set_config(8196, LPI_PROP_DEFAULT); + + its_send_invall(col2); + its_send_invall(col3); + + report_prefix_push("int"); + /* + * dev=3D2, eventid=3D20 -> lpi=3D 8195, col=3D3 + * dev=3D7, eventid=3D255 -> lpi=3D 8196, col=3D2 + * Trigger dev2, eventid=3D20 and dev7, eventid=3D255 + * Check both LPIs hit + */ + + its_send_mapd(dev2, true); + its_send_mapd(dev7, true); + + its_send_mapc(col3, true); + its_send_mapc(col2, true); + + its_send_mapti(dev2, 8195 /* lpi id */, + 20 /* event id */, col3); + its_send_mapti(dev7, 8196 /* lpi id */, + 255 /* event id */, col2); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); + + report_prefix_pop(); + + report_prefix_push("inv/invall"); + + /* + * disable 8195, check dev2/eventid=3D20 does not trigger the + * corresponding LPI + */ + gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT & ~0x1); + its_send_inv(dev2, 20); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + + /* + * re-enable the LPI but willingly do not call invall + * so the change in config is not taken into account. + * The LPI should not hit + */ + gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + + /* Now call the invall and check the LPI hits */ + its_send_invall(col3); + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + report_prefix_pop(); + /* + * Unmap device 2 and check the eventid 20 formerly + * attached to it does not hit anymore + */ + report_prefix_push("mapd valid=3Dfalse"); + its_send_mapd(dev2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + report_prefix_pop(); + + /* Unmap the collection this time and check no LPI does hit */ + report_prefix_push("mapc valid=3Dfalse"); + its_send_mapc(col2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev7, 255); + check_lpi_stats(); + report_prefix_pop(); +} #endif =20 int main(int argc, char **argv) @@ -594,6 +796,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); gic_test_mmio(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-trigger")) { + report_prefix_push(argv[1]); + test_its_trigger(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index ba2b31b..bfafec5 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -129,6 +129,13 @@ extra_params =3D -machine gic-version=3D3 -append 'its= -introspection' groups =3D its arch =3D arm64 =20 +[its-trigger] +file =3D gic.flat +smp =3D $MAX_SMP +extra_params =3D -machine gic-version=3D3 -append 'its-trigger' +groups =3D its +arch =3D arm64 + # Test PSCI emulation [psci] file =3D psci.flat --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580208080149480.9537735747207; Tue, 28 Jan 2020 02:41:20 -0800 (PST) Received: from localhost ([::1]:56744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOJ5-0002J7-2Y for importer@patchew.org; Tue, 28 Jan 2020 05:41:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48443) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOEi-0001HL-Pj for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwOEh-0000td-IK for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:48 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:35370 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iwOEg-0000tH-T7 for qemu-devel@nongnu.org; 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bh=4rg/k06agYpeHTMb6VPLMCe1FRP5QhHn6nkrtKzHYyU=; b=hS7ojwrPl2KOHOqqDjee8mkf4RRBab7GJVyEbtneiEKg8C/OTueLMFCly4Pyb6rKNivn7b Mv/or+DSxg/QiH2JSQsGSWPDHQaTczd0ArzaHsBN67TOk1k1fHqcW6e3uDl+Ll8OwoDuxn IqQw36eOocKUgPegUOXNTXKFpLqaL9A= X-MC-Unique: qhqu4rEkMkGvCxNOhUNI6A-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 12/14] arm/run: Allow Migration tests Date: Tue, 28 Jan 2020 11:34:57 +0100 Message-Id: <20200128103459.19413-13-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Let's link getchar.o to use puts and getchar from the tests. Then allow tests belonging to the migration group to trigger the migration from the test code by putting "migrate" into the uart. Then the code can wait for the migration completion by using getchar(). The __getchar implement is minimalist as it just reads the data register. It is just meant to read the single character emitted at the end of the migration by the runner script. It is not meant to read more data (FIFOs are not enabled). Signed-off-by: Eric Auger --- v2 -> v3: - take the lock - assert if more than 16 chars - removed Thomas' R-b --- arm/Makefile.common | 2 +- arm/run | 2 +- lib/arm/io.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/arm/Makefile.common b/arm/Makefile.common index b8988f2..a123e85 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -32,7 +32,7 @@ CFLAGS +=3D -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I l= ib asm-offsets =3D lib/$(ARCH)/asm-offsets.h include $(SRCDIR)/scripts/asm-offsets.mak =20 -cflatobjs +=3D lib/util.o +cflatobjs +=3D lib/util.o lib/getchar.o cflatobjs +=3D lib/alloc_phys.o cflatobjs +=3D lib/alloc_page.o cflatobjs +=3D lib/vmalloc.o diff --git a/arm/run b/arm/run index 277db9b..a390ca5 100755 --- a/arm/run +++ b/arm/run @@ -61,6 +61,6 @@ fi M+=3D",accel=3D$ACCEL" command=3D"$qemu -nodefaults $M -cpu $processor $chr_testdev $pci_testdev" command+=3D" -display none -serial stdio -kernel" -command=3D"$(timeout_cmd) $command" +command=3D"$(migration_cmd) $(timeout_cmd) $command" =20 run_qemu $command "$@" diff --git a/lib/arm/io.c b/lib/arm/io.c index 99fd315..d8e7745 100644 --- a/lib/arm/io.c +++ b/lib/arm/io.c @@ -87,6 +87,34 @@ void puts(const char *s) spin_unlock(&uart_lock); } =20 +static int ____getchar(void) +{ + int c; + + spin_lock(&uart_lock); + c =3D readb(uart0_base); + spin_unlock(&uart_lock); + + return c ? : -1; +} + +/* + * Minimalist implementation for migration completion detection. + * Without FIFOs enabled on the QEMU UART device we just read + * the data register: we cannot read more than 16 characters. + */ +int __getchar(void) +{ + int c =3D ____getchar(); + static int count; + + if (c !=3D -1) + ++count; + + assert(count < 16); + + return c; +} =20 /* * Defining halt to take 'code' as an argument guarantees that it will --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580208026628436.6653619785898; Tue, 28 Jan 2020 02:40:26 -0800 (PST) Received: from localhost ([::1]:56712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOID-0000Lw-KD for importer@patchew.org; Tue, 28 Jan 2020 05:40:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48478) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOEp-0001an-I6 for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwOEo-0000xe-BY for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:55 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:42880 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iwOEo-0000xH-8s for qemu-devel@nongnu.org; Tue, 28 Jan 2020 05:36:54 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-263-UG3wMHMNNiSvYC7irf-cqQ-1; Tue, 28 Jan 2020 05:36:52 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 12447800D53; Tue, 28 Jan 2020 10:36:50 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 52B201001B08; Tue, 28 Jan 2020 10:36:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207813; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K7xClZeAzAhgTph2V9BhHIcpidTH43JOzyIXf0zlJ/g=; b=HrcCg28fn1NXA2Cz2Voq3pAL0dItLjW2NzM486ox2oPJ+HgN2gYMnrLzVyB0NqqgXFBoAJ lmyOhkdPo5fBuOmy8dP/yaxW787KyURLOu//Io3J8INxGwU0qzA0EbBjzMe4OcfZgQ1mp1 xu1mv9B1IW5oRgEhrrkdlVmu3ozgo8A= X-MC-Unique: UG3wMHMNNiSvYC7irf-cqQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 13/14] arm/arm64: ITS: migration tests Date: Tue, 28 Jan 2020 11:34:58 +0100 Message-Id: <20200128103459.19413-14-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This test maps LPIs (populates the device table, the collection table, interrupt translation tables, configuration table), migrates and make sure the translation is correct on the destination. Signed-off-by: Eric Auger --- arm/gic.c | 59 ++++++++++++++++++++++++++++++++++++---- arm/unittests.cfg | 8 ++++++ lib/arm/asm/gic-v3-its.h | 2 ++ lib/arm/gic-v3-its.c | 22 +++++++++++++++ 4 files changed, 85 insertions(+), 6 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 50104b1..fa8626a 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -593,6 +593,7 @@ static void gic_test_mmio(void) =20 static void test_its_introspection(void) {} static void test_its_trigger(void) {} +static void test_its_migration(void) {} =20 #else /* __arch64__ */ =20 @@ -665,13 +666,19 @@ static bool its_prerequisites(int nb_cpus) return false; } =20 -static void test_its_trigger(void) +/* + * Setup the configuration for those mappings: + * dev_id=3D2 event=3D20 -> vcpu 3, intid=3D8195 + * dev_id=3D7 event=3D255 -> vcpu 2, intid=3D8196 + * LPIs ready to hit + */ +static int its_setup1(void) { struct its_collection *col3, *col2; struct its_device *dev2, *dev7; =20 if (its_prerequisites(4)) - return; + return -1; =20 dev2 =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); dev7 =3D its_create_device(7 /* dev id */, 8 /* nb_ites */); @@ -685,14 +692,10 @@ static void test_its_trigger(void) its_send_invall(col2); its_send_invall(col3); =20 - report_prefix_push("int"); /* * dev=3D2, eventid=3D20 -> lpi=3D 8195, col=3D3 * dev=3D7, eventid=3D255 -> lpi=3D 8196, col=3D2 - * Trigger dev2, eventid=3D20 and dev7, eventid=3D255 - * Check both LPIs hit */ - its_send_mapd(dev2, true); its_send_mapd(dev7, true); =20 @@ -703,6 +706,23 @@ static void test_its_trigger(void) 20 /* event id */, col3); its_send_mapti(dev7, 8196 /* lpi id */, 255 /* event id */, col2); + return 0; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_setup1()) + return; + + col3 =3D its_get_collection(3); + col2 =3D its_get_collection(2); + dev2 =3D its_get_device(2); + dev7 =3D its_get_device(7); + + report_prefix_push("int"); =20 lpi_stats_expect(3, 8195); its_send_int(dev2, 20); @@ -763,6 +783,29 @@ static void test_its_trigger(void) check_lpi_stats(); report_prefix_pop(); } + +static void test_its_migration(void) +{ + struct its_device *dev2, *dev7; + + if (its_setup1()) + return; + + dev2 =3D its_get_device(2); + dev7 =3D its_get_device(7); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); +} #endif =20 int main(int argc, char **argv) @@ -800,6 +843,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_trigger(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-migration")) { + report_prefix_push(argv[1]); + test_its_migration(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index bfafec5..8b8ec79 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -136,6 +136,14 @@ extra_params =3D -machine gic-version=3D3 -append 'its= -trigger' groups =3D its arch =3D arm64 =20 +[its-migration] +file =3D gic.flat +smp =3D $MAX_SMP +accel =3D kvm +extra_params =3D -machine gic-version=3D3 -append 'its-migration' +groups =3D its migration +arch =3D arm64 + # Test PSCI emulation [psci] file =3D psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 0e5c5b6..febc2b2 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -151,6 +151,8 @@ extern void its_send_invall(struct its_collection *col); extern void its_send_movi(struct its_device *dev, struct its_collection *col, u32 id); extern void its_send_sync(struct its_collection *col); +extern struct its_device *its_get_device(u32 id); +extern struct its_collection *its_get_collection(u32 id); =20 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index c2dcd01..099940e 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -219,3 +219,25 @@ struct its_collection *its_create_collection(u32 col_i= d, u32 pe) its_data.nr_collections++; return new; } + +struct its_device *its_get_device(u32 id) +{ + int i; + + for (i =3D 0; i < GITS_MAX_DEVICES; i++) { + if (its_data.devices[i].device_id =3D=3D id) + return &its_data.devices[i]; + } + return NULL; +} + +struct its_collection *its_get_collection(u32 id) +{ + int i; + + for (i =3D 0; i < GITS_MAX_COLLECTIONS; i++) { + if (its_data.collections[i].col_id =3D=3D id) + return &its_data.collections[i]; + } + return NULL; +} --=20 2.20.1 From nobody Sun Feb 8 14:56:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580208241339644.4459401845776; Tue, 28 Jan 2020 02:44:01 -0800 (PST) Received: from localhost ([::1]:56788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOLg-00062n-BS for importer@patchew.org; Tue, 28 Jan 2020 05:44:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48538) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwOEy-0001uH-DF for qemu-devel@nongnu.org; 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Tue, 28 Jan 2020 10:36:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580207822; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iejx/JZ1+EnGuUcmALEj4bgYElrakUr3k1rCRIjvnWk=; b=bOTkgTJCq6OhK5qYTfHbLo2eEz44h5FgNroCnNrTS2V4qPA7aS3ACyFdfvTn0F8KmpsAZJ Fle7bIhmNQDNfKRdCwiGBYxQPNVQmMtTwpC8hTPWaUG1n3agJSeZG+tMnmpAETZi72iQgg UlHtxcMExvE6mpJ3x6APTgzrMUlbga8= X-MC-Unique: 8h2aoagmPQePo-TwIz8zLA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v3 14/14] arm/arm64: ITS: pending table migration test Date: Tue, 28 Jan 2020 11:34:59 +0100 Message-Id: <20200128103459.19413-15-eric.auger@redhat.com> In-Reply-To: <20200128103459.19413-1-eric.auger@redhat.com> References: <20200128103459.19413-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add two new migration tests. One testing the migration of a topology where collection were unmapped. The second test checks the migration of the pending table. Signed-off-by: Eric Auger --- v2 -> v3: - tests belong to both its and migration groups --- arm/gic.c | 150 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 16 +++++ 2 files changed, 166 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index fa8626a..ec3dd3a 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -195,6 +195,7 @@ static void lpi_handler(struct pt_regs *regs __unused) smp_rmb(); /* pairs with wmb in lpi_stats_expect */ lpi_stats.observed.cpu_id =3D smp_processor_id(); lpi_stats.observed.lpi_id =3D irqnr; + acked[lpi_stats.observed.cpu_id]++; smp_wmb(); /* pairs with rmb in check_lpi_stats */ } =20 @@ -239,6 +240,18 @@ static void secondary_lpi_test(void) while (1) wfi(); } + +static void check_lpi_hits(int *expected) +{ + int i; + + for (i =3D 0; i < nr_cpus; i++) { + if (acked[i] !=3D expected[i]) + report(false, "expected %d LPIs on PE #%d, %d observed", + expected[i], i, acked[i]); + } + report(true, "check LPI on all vcpus"); +} #endif =20 static void gicv2_ipi_send_self(void) @@ -594,6 +607,8 @@ static void gic_test_mmio(void) static void test_its_introspection(void) {} static void test_its_trigger(void) {} static void test_its_migration(void) {} +static void test_migrate_unmapped_collection(void) {} +static void test_its_pending_migration(void) {} =20 #else /* __arch64__ */ =20 @@ -666,6 +681,18 @@ static bool its_prerequisites(int nb_cpus) return false; } =20 +static void set_lpi(struct its_device *dev, u32 eventid, u32 physid, + struct its_collection *col) +{ + if (!dev || !col) + report_abort("wrong device or collection"); + + its_send_mapti(dev, physid, eventid, col); + + gicv3_lpi_set_config(physid, LPI_PROP_DEFAULT); + its_send_invall(col); +} + /* * Setup the configuration for those mappings: * dev_id=3D2 event=3D20 -> vcpu 3, intid=3D8195 @@ -806,6 +833,121 @@ static void test_its_migration(void) its_send_int(dev7, 255); check_lpi_stats(); } + +static void test_migrate_unmapped_collection(void) +{ + struct its_collection *col; + struct its_device *dev2, *dev7; + u8 config; + + if (its_setup1()) + return; + + col =3D its_create_collection(nr_cpus - 1, nr_cpus - 1); + dev2 =3D its_get_device(2); + dev7 =3D its_get_device(7); + + /* MAPTI with the collection unmapped */ + set_lpi(dev2, 0, 8192, col); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + /* on the destination, map the collection */ + its_send_mapc(col, true); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); + + config =3D gicv3_lpi_get_config(8192); + report(config =3D=3D LPI_PROP_DEFAULT, + "Config of LPI 8192 was properly migrated"); + + lpi_stats_expect(nr_cpus - 1, 8192); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* unmap the collection */ + its_send_mapc(col, false); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* remap event 0 onto lpiid 8193 */ + set_lpi(dev2, 0, 8193, col); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* remap the collection */ + its_send_mapc(col, true); + lpi_stats_expect(nr_cpus - 1, 8193); +} + +static void test_its_pending_migration(void) +{ + struct its_device *dev; + struct its_collection *collection[2]; + int expected[NR_CPUS]; + u64 pendbaser; + void *ptr; + int i; + + if (its_prerequisites(4)) + return; + + dev =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); + its_send_mapd(dev, true); + + collection[0] =3D its_create_collection(nr_cpus - 1, nr_cpus - 1); + collection[1] =3D its_create_collection(nr_cpus - 2, nr_cpus - 2); + its_send_mapc(collection[0], true); + its_send_mapc(collection[1], true); + + /* disable lpi at redist level */ + gicv3_lpi_rdist_ctrl(nr_cpus - 1, false); + gicv3_lpi_rdist_ctrl(nr_cpus - 2, false); + + /* even lpis are assigned to even cpu */ + for (i =3D 0; i < 256; i++) { + struct its_collection *col =3D i % 2 ? collection[0] : + collection[1]; + int vcpu =3D col->target_address >> 16; + + its_send_mapti(dev, 8192 + i, i, col); + gicv3_lpi_set_config(8192 + i, LPI_PROP_DEFAULT); + gicv3_lpi_set_pending_table_bit(vcpu, 8192 + i, true); + } + its_send_invall(collection[0]); + its_send_invall(collection[1]); + + /* Set the PTZ bit on each pendbaser */ + + expected[nr_cpus - 1] =3D 128; + expected[nr_cpus - 2] =3D 128; + + ptr =3D gicv3_data.redist_base[nr_cpus - 1] + GICR_PENDBASER; + pendbaser =3D readq(ptr); + writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr); + + ptr =3D gicv3_data.redist_base[nr_cpus - 2] + GICR_PENDBASER; + pendbaser =3D readq(ptr); + writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr); + + gicv3_lpi_rdist_ctrl(nr_cpus - 1, true); + gicv3_lpi_rdist_ctrl(nr_cpus - 2, true); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + mdelay(1000); + + check_lpi_hits(expected); +} #endif =20 int main(int argc, char **argv) @@ -847,6 +989,14 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_migration(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-pending-migration")) { + report_prefix_push(argv[1]); + test_its_pending_migration(); + report_prefix_pop(); + } else if (!strcmp(argv[1], "its-migrate-unmapped-collection")) { + report_prefix_push(argv[1]); + test_migrate_unmapped_collection(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 8b8ec79..d917157 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -144,6 +144,22 @@ extra_params =3D -machine gic-version=3D3 -append 'its= -migration' groups =3D its migration arch =3D arm64 =20 +[its-pending-migration] +file =3D gic.flat +smp =3D $MAX_SMP +accel =3D kvm +extra_params =3D -machine gic-version=3D3 -append 'its-pending-migration' +groups =3D its migration +arch =3D arm64 + +[its-migrate-unmapped-collection] +file =3D gic.flat +smp =3D $MAX_SMP +accel =3D kvm +extra_params =3D -machine gic-version=3D3 -append 'its-migrate-unmapped-co= llection' +groups =3D its migration +arch =3D arm64 + # Test PSCI emulation [psci] file =3D psci.flat --=20 2.20.1