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[173.198.77.92]) by smtp.gmail.com with ESMTPSA id v4sm8377880pgo.63.2020.01.24.15.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 15:20:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UyCQge1KXUAicsccNG4/t552CMDJ9UzmYHcJdartGao=; b=nAA/OUw8/taL8k9ueq3WwA8/0jMt6J9uHGCXCVyFueNRE3zHqMdkwnvvdRGIbX6rCR k6cajBM+YHyX2DxdFt57Px2pI9/g1abHMFFjW22teQU+AtbdOfnuCODK3Op7EJin4IHv 5DjPXbFYvbZ4QK4da3YZws6p95xoNEk2AqsU/MzKyjLmVKpyzYCQCHssBqoTdLygR9NM bcTTdQ2fXCjMLy18bdg+8uynCY72FWETb/7Bf54ZC+wj7mDKklvvRFedVWe/qSYBgJvB upryRslcoAY7x/2XoV6FcqVnvwdKDUVJd7b00QZ6L2DuQ9aFWKSr6+sc6CjwhZBIKBHE O1Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UyCQge1KXUAicsccNG4/t552CMDJ9UzmYHcJdartGao=; b=qEOJgU7NIqIKFP3yW+lIgiEMaT9x7IyV0LIrSszgNwHZf9H5CqK1TZJtfCLBA1Kajj kOvLrc1k0qllnBzySyCuIfI3IGaZGkMq9J8WiCp0clPMJh56eGmvuiwFbRCy2/sVbdKz M4bNtV1XOzIllTJ9XUO7NjosKWyMbtlLsewmqq4IQF9iIV82xwFkNbn5/qj8utkCS6uN IcMAiFQ2DWFQa8NR8nCi5z9LNgAbZkFmooWjRmzaRUzZkAp6oAsMLtlmLSzcDzKUFiaX IgO4XQJn4qv55YdjNHUTYhoM5V4BzPa3UrINzfHbsQoQorRbJaXn1dQDJQVMjoPuWkvy kk7Q== X-Gm-Message-State: APjAAAVKWLEqQCrh1Ol1vvrlCOv4tlVgnQ8eNGQxux9rbxflkNF2P2Gy z5TvWZhXpcsIvumJ4x4RwT+68zczbdQ= X-Google-Smtp-Source: APXvYqx7J7VQGSC0UN8DQSwXlvCVd6mqyTrkKrH6/hLA3eS7vCh/9ExC5w3Q0oY9LwBa66JqR3McQw== X-Received: by 2002:a63:5220:: with SMTP id g32mr3720534pgb.116.1579908041931; Fri, 24 Jan 2020 15:20:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL v3 11/11] target/hppa: Allow, but diagnose, LDCW aligned only mod 4 Date: Fri, 24 Jan 2020 13:20:09 -1000 Message-Id: <20200124232009.12928-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200124232009.12928-1-richard.henderson@linaro.org> References: <20200124232009.12928-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, deller@gmx.de, John David Anglin , svens@stackframe.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PA-RISC 1.1 specification says that LDCW must be aligned mod 16 or the operation is undefined. However, real hardware only generates an unaligned access trap for unaligned mod 4. Match real hardware, but diagnose with GUEST_ERROR a violation of the specification. At the same time fix a bug in the initialization of mop, where the size was specified twice, and another to free the zero temporary. Tested-by: Helge Deller Reported-by: Helge Deller Suggested-by: John David Anglin Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 9 +++++++++ target/hppa/translate.c | 15 ++++++++++++++- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 38d834ef6b..2d483aab58 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -17,6 +17,8 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void,= env, tl, tr) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) =20 +DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) + DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index f0516e81f1..7823706e9c 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -153,6 +153,15 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target= _ulong addr, do_stby_e(env, addr, val, true, GETPC()); } =20 +void HELPER(ldc_check)(target_ulong addr) +{ + if (unlikely(addr & 0xf)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Undefined ldc to unaligned address mod 16: " + TARGET_FMT_lx "\n", addr); + } +} + target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr, uint32_t level, uint32_t want) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f25927aeca..52d7bea1ea 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2942,7 +2942,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) =20 static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { - MemOp mop =3D MO_TEUL | MO_ALIGN_16 | a->size; + MemOp mop =3D MO_TE | MO_ALIGN | a->size; TCGv_reg zero, dest, ofs; TCGv_tl addr; =20 @@ -2958,8 +2958,21 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) =20 form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, a->disp, a->sp, a->m, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + + /* + * For hppa1.1, LDCW is undefined unless aligned mod 16. + * However actual hardware succeeds with aligned mod 4. + * Detect this case and log a GUEST_ERROR. + * + * TODO: HPPA64 relaxes the over-alignment requirement + * with the ,co completer. + */ + gen_helper_ldc_check(addr); + zero =3D tcg_const_reg(0); tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); + tcg_temp_free(zero); + if (a->m) { save_gpr(ctx, a->b, ofs); } --=20 2.20.1