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[173.198.77.92]) by smtp.gmail.com with ESMTPSA id b21sm84521pfp.0.2020.01.22.16.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2020 16:03:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y+UZSm36UbjApeVCaAm7+pNHHNI5asAQd1KZZfSzaOQ=; b=Tcn7NttZMlZ297f6NwErgD7oaEF7G18oRRvpaLuA6E3gobQ+1IzDr+4C6fRBHe1eXw eQONStw0qTHL8drQstm3KK6ZD7OfBw6SbemvYbjRMQvGWA4XLJBmwzNSsKdskaaajuV8 sx2sJvmeF28rsQs7VkEKgpjzfY2LxXQK67hPx0Ovk+7d6Jmuy8OIOZxo/90aozB24tvd Jf08dUNmK5NsoteizDAaYyPirtwQoAGTVglkBu5g0ImoyytjTeRzlEVPucKk1+02eA3V E1v2Zq/dEsqrMLe+zjDQ2JQWplQj96496HYuTaFjP5XHzu4XQ33b5j9I3IKbk0C1nvcb tWrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y+UZSm36UbjApeVCaAm7+pNHHNI5asAQd1KZZfSzaOQ=; b=NTT2QkoBF9rN2/60IBRNGo00MdMi2oYV5SUApTg63QJU9+iCO9aj1vgZZMuVEYxMJe Jr5xsMV0axPBSin7BHqpwW86OYcfCgJ1JbLV8ko3jqt3pV1EuiCYD+NcfRLQAZZdXxwh C6hW40jBGwUPItwJNTmrK4gNZ03nv+UEogf3eY0Htqg3butKtH2pkjcUhFiXye1S7Gv+ 9lUarmXVh00Ag2yKWtHpf53eDqCpG/4a00BK2xvCGv0xIpGAo5VIipLSZmVNMhxQXrbb roFxMhnXjeY6MeNI5XdZa7BZIKIee9Dh+5pnnJmOcvVMX+j5m/l7rMJ3eVjwpGFjskEm 128Q== X-Gm-Message-State: APjAAAWGx8c1shbpii2u8LodVxH6tv+fKo0iisiX+oRWqBCkcpqGxdb0 iotTkOAguM+ukJY28srjUvzAH7ehyZI= X-Google-Smtp-Source: APXvYqz5Rgnhu3p8RjIyJ0XXVLyyVQWBnC5a7ZSHzmGgB8VdubMOSNK+pabgmqD5yWymogxq1TA7lQ== X-Received: by 2002:a17:90a:8a0e:: with SMTP id w14mr1237979pjn.51.1579737798257; Wed, 22 Jan 2020 16:03:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH rc1 03/24] target/avr: Add instruction translation - Registers definition Date: Wed, 22 Jan 2020 14:02:46 -1000 Message-Id: <20200123000307.11541-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200123000307.11541-1-richard.henderson@linaro.org> References: <20200123000307.11541-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.67 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, me@xcancerberox.com.ar, S.E.Harris@kent.ac.uk, dovgaluk@ispras.ru, imammedo@redhat.com, mrolnik@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Michael Rolnik Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200118191416.19934-4-mrolnik@gmail.com> Signed-off-by: Richard Henderson --- target/avr/translate.c | 171 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr/translate.c new file mode 100644 index 0000000000..535f666d18 --- /dev/null +++ b/target/avr/translate.c @@ -0,0 +1,171 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "tcg/tcg.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "tcg/tcg-op.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" +#include "exec/log.h" +#include "exec/translator.h" +#include "exec/gen-icount.h" + +/* + * Define if you want a BREAK instruction translated to a breakpoint + * Active debugging connection is assumed + * This is for + * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tes= ts + * tests + */ +#undef BREAKPOINT_ON_BREAK + +static TCGv cpu_pc; + +static TCGv cpu_Cf; +static TCGv cpu_Zf; +static TCGv cpu_Nf; +static TCGv cpu_Vf; +static TCGv cpu_Sf; +static TCGv cpu_Hf; +static TCGv cpu_Tf; +static TCGv cpu_If; + +static TCGv cpu_rampD; +static TCGv cpu_rampX; +static TCGv cpu_rampY; +static TCGv cpu_rampZ; + +static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS]; +static TCGv cpu_eind; +static TCGv cpu_sp; + +static TCGv cpu_skip; + +static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", +}; +#define REG(x) (cpu_r[x]) + +enum { + DISAS_EXIT =3D DISAS_TARGET_0, /* We want return to the cpu main lo= op. */ + DISAS_LOOKUP =3D DISAS_TARGET_1, /* We have a variable condition exit= . */ + DISAS_CHAIN =3D DISAS_TARGET_2, /* We have a single condition exit. = */ +}; + +typedef struct DisasContext DisasContext; + +/* This is the state at translation time. */ +struct DisasContext { + TranslationBlock *tb; + + CPUAVRState *env; + CPUState *cs; + + target_long npc; + uint32_t opcode; + + /* Routine used to access memory */ + int memidx; + int bstate; + int singlestep; + + /* + * some AVR instructions can make the following instruction to be skip= ped + * Let's name those instructions + * A - instruction that can skip the next one + * B - instruction that can be skipped. this depends on executio= n of A + * there are two scenarios + * 1. A and B belong to the same translation block + * 2. A is the last instruction in the translation block and B is the = last + * + * following variables are used to simplify the skipping logic, they a= re + * used in the following manner (sketch) + * + * TCGLabel *skip_label =3D NULL; + * if (ctx.skip_cond !=3D TCG_COND_NEVER) { + * skip_label =3D gen_new_label(); + * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); + * } + * + * if (free_skip_var0) { + * tcg_temp_free(skip_var0); + * free_skip_var0 =3D false; + * } + * + * translate(&ctx); + * + * if (skip_label) { + * gen_set_label(skip_label); + * } + */ + TCGv skip_var0; + TCGv skip_var1; + TCGCond skip_cond; + bool free_skip_var0; +}; + +static int to_regs_16_31_by_one(DisasContext *ctx, int indx) +{ + return 16 + (indx % 16); +} + +static int to_regs_16_23_by_one(DisasContext *ctx, int indx) +{ + return 16 + (indx % 8); +} +static int to_regs_24_30_by_two(DisasContext *ctx, int indx) +{ + return 24 + (indx % 4) * 2; +} +static int to_regs_00_30_by_two(DisasContext *ctx, int indx) +{ + return (indx % 16) * 2; +} + +static uint16_t next_word(DisasContext *ctx) +{ + return cpu_lduw_code(ctx->env, ctx->npc++ * 2); +} + +static int append_16(DisasContext *ctx, int x) +{ + return x << 16 | next_word(ctx); +} + + +static bool avr_have_feature(DisasContext *ctx, int feature) +{ + if (!avr_feature(ctx->env, feature)) { + gen_helper_unsupported(cpu_env); + ctx->bstate =3D DISAS_NORETURN; + return false; + } + return true; +} + +static bool decode_insn(DisasContext *ctx, uint16_t insn); +#include "decode_insn.inc.c" --=20 2.20.1