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X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This splits the common write callback into separate ast2400 and ast2500 implementations. This makes it clearer when implementing differing behaviour. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/aspeed_scu.c | 80 +++++++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 23 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index f62fa25e3474..7108cad8c6a7 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -232,8 +232,47 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr o= ffset, unsigned size) return s->regs[reg]; } =20 -static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, - unsigned size) +static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + AspeedSCUState *s =3D ASPEED_SCU(opaque); + int reg =3D TO_REG(offset); + + if (reg >=3D ASPEED_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && + !s->regs[PROT_KEY]) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); + } + + trace_aspeed_scu_write(offset, size, data); + + switch (reg) { + case PROT_KEY: + s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; + return; + case SILICON_REV: + case FREQ_CNTR_EVAL: + case VGA_SCRATCH1 ... VGA_SCRATCH8: + case RNG_DATA: + case FREE_CNTR4: + case FREE_CNTR4_EXT: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + s->regs[reg] =3D data; +} + +static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); int reg =3D TO_REG(offset); @@ -257,25 +296,11 @@ static void aspeed_scu_write(void *opaque, hwaddr off= set, uint64_t data, case PROT_KEY: s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; return; - case CLK_SEL: - s->regs[reg] =3D data; - break; case HW_STRAP1: - if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { - s->regs[HW_STRAP1] |=3D data; - return; - } - /* Jump to assignment below */ - break; + s->regs[HW_STRAP1] |=3D data; + return; case SILICON_REV: - if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { - s->regs[HW_STRAP1] &=3D ~data; - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Write to read-only offset 0x%" HWADDR_PRIx = "\n", - __func__, offset); - } - /* Avoid assignment below, we've handled everything */ + s->regs[HW_STRAP1] &=3D ~data; return; case FREQ_CNTR_EVAL: case VGA_SCRATCH1 ... VGA_SCRATCH8: @@ -291,9 +316,18 @@ static void aspeed_scu_write(void *opaque, hwaddr offs= et, uint64_t data, s->regs[reg] =3D data; } =20 -static const MemoryRegionOps aspeed_scu_ops =3D { +static const MemoryRegionOps aspeed_ast2400_scu_ops =3D { + .read =3D aspeed_scu_read, + .write =3D aspeed_ast2400_scu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static const MemoryRegionOps aspeed_ast2500_scu_ops =3D { .read =3D aspeed_scu_read, - .write =3D aspeed_scu_write, + .write =3D aspeed_ast2500_scu_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, @@ -469,7 +503,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *kla= ss, void *data) asc->calc_hpll =3D aspeed_2400_scu_calc_hpll; asc->apb_divider =3D 2; asc->nr_regs =3D ASPEED_SCU_NR_REGS; - asc->ops =3D &aspeed_scu_ops; + asc->ops =3D &aspeed_ast2400_scu_ops; } =20 static const TypeInfo aspeed_2400_scu_info =3D { @@ -489,7 +523,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *kla= ss, void *data) asc->calc_hpll =3D aspeed_2500_scu_calc_hpll; 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Mon, 20 Jan 2020 17:33:16 -0800 (PST) From: Joel Stanley To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell Subject: [PATCH 2/2] aspeed/scu: Implement chip ID register Date: Tue, 21 Jan 2020 12:03:02 +1030 Message-Id: <20200121013302.43839-3-joel@jms.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200121013302.43839-1-joel@jms.id.au> References: <20200121013302.43839-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This returns a fixed but non-zero value for the chip id. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/aspeed_scu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 7108cad8c6a7..19d1780a40da 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -77,6 +77,8 @@ #define CPU2_BASE_SEG4 TO_REG(0x110) #define CPU2_BASE_SEG5 TO_REG(0x114) #define CPU2_CACHE_CTRL TO_REG(0x118) +#define CHIP_ID0 TO_REG(0x150) +#define CHIP_ID1 TO_REG(0x154) #define UART_HPLL_CLK TO_REG(0x160) #define PCIE_CTRL TO_REG(0x180) #define BMC_MMIO_CTRL TO_REG(0x184) @@ -115,6 +117,8 @@ #define AST2600_HW_STRAP2_PROT TO_REG(0x518) #define AST2600_RNG_CTRL TO_REG(0x524) #define AST2600_RNG_DATA TO_REG(0x540) +#define AST2600_CHIP_ID0 TO_REG(0x5B0) +#define AST2600_CHIP_ID1 TO_REG(0x5B4) =20 #define AST2600_CLK TO_REG(0x40) =20 @@ -182,6 +186,8 @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_R= EGS] =3D { [CPU2_BASE_SEG1] =3D 0x80000000U, [CPU2_BASE_SEG4] =3D 0x1E600000U, [CPU2_BASE_SEG5] =3D 0xC0000000U, + [CHIP_ID0] =3D 0x1234ABCDU, + [CHIP_ID1] =3D 0x88884444U, [UART_HPLL_CLK] =3D 0x00001903U, [PCIE_CTRL] =3D 0x0000007BU, [BMC_DEV_ID] =3D 0x00002402U @@ -307,6 +313,8 @@ static void aspeed_ast2500_scu_write(void *opaque, hwad= dr offset, case RNG_DATA: case FREE_CNTR4: case FREE_CNTR4_EXT: + case CHIP_ID0: + case CHIP_ID1: qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -620,6 +628,8 @@ static void aspeed_ast2600_scu_write(void *opaque, hwad= dr offset, case AST2600_RNG_DATA: case AST2600_SILICON_REV: case AST2600_SILICON_REV2: + case AST2600_CHIP_ID0: + case AST2600_CHIP_ID1: /* Add read only registers here */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", @@ -648,6 +658,9 @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_= SCU_NR_REGS] =3D { [AST2600_CLK_STOP_CTRL2] =3D 0xFFF0FFF0, [AST2600_SDRAM_HANDSHAKE] =3D 0x00000040, /* SoC completed DRAM ini= t */ [AST2600_HPLL_PARAM] =3D 0x1000405F, + [AST2600_CHIP_ID0] =3D 0x1234ABCD, + [AST2600_CHIP_ID1] =3D 0x88884444, + }; =20 static void aspeed_ast2600_scu_reset(DeviceState *dev) --=20 2.24.1