From nobody Thu May 2 11:50:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1579518873; cv=none; d=zohomail.com; s=zohoarc; b=GVIK3Tn8w6Mqa2h6ccaxU1roqAGDIl/1Ly72vGvnJyhtZyWQ2k/GUjp04rWfyjGNdWnd/zbB5sv2JjUoGnOhh3bDFcighVjbsTIMtnJMcYK/4y767+NE2OkFlTZyQr7FPNQ8s+A7XuN+lhpjkphcwR60dgzDk30GNHvKNNbg074= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1579518873; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PJaOlxGYJR+Hgb3TYWvCFHuuQTO5YPttkvJV+40NtVo=; b=fQ35a95aI92BFBiC9KqnfZeI3MLN4YcdY/0Iw6fJwZgtWASOjxf7ZkJ1VctXuRuWnAMF96F3AnOnpnSP4OJLGaFIX7MHTxy2lgeODwKQ+fAm/2AEHty5gyz1yGLS0+eoicuO2LqHQw9RMbyVH35sfs3uFPreWfUN0sRgooI28w8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1579518873739381.721249884774; Mon, 20 Jan 2020 03:14:33 -0800 (PST) Received: from localhost ([::1]:34424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1itV0q-00004v-CJ for importer@patchew.org; Mon, 20 Jan 2020 06:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40108) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1itUd7-000862-M3 for qemu-devel@nongnu.org; Mon, 20 Jan 2020 05:50:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1itUd3-0000kd-Qs for qemu-devel@nongnu.org; Mon, 20 Jan 2020 05:50:01 -0500 Received: from 18.mo3.mail-out.ovh.net ([87.98.172.162]:54952) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1itUd3-0000jf-KE for qemu-devel@nongnu.org; Mon, 20 Jan 2020 05:49:57 -0500 Received: from player718.ha.ovh.net (unknown [10.108.54.237]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 00A9523E326 for ; Mon, 20 Jan 2020 11:49:54 +0100 (CET) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id A442FE5062C2; Mon, 20 Jan 2020 10:49:45 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH v2 1/2] target/ppc: Add privileged message send facilities Date: Mon, 20 Jan 2020 11:49:34 +0100 Message-Id: <20200120104935.24449-2-clg@kaod.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200120104935.24449-1-clg@kaod.org> References: <20200120104935.24449-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 9642769755435338726 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedugedrudehgddugecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdekvddrieegrddvhedtrddujedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejudekrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedt Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.172.162 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The Processor Control facility for POWER8 processors and later provides a mechanism for the hypervisor to send messages to other threads in the system (msgsnd instruction) and cause hypervisor-level exceptions. Privileged non-hypervisor programs can also send messages (msgsndp instruction) but are restricted to the threads of the same subprocessor and cause privileged-level exceptions. The Directed Privileged Doorbell Exception State (DPDES) register reflects the state of pending privileged doorbell exceptions and can be used to modify that state. The register can be used to read and modify the state of privileged doorbell exceptions for all threads of a subprocessor and thus is a shared facility for that subprocessor. The register can be read/written by the hypervisor and read by the supervisor if enabled in the HFSCR, otherwise a hypervisor facility unavailable exception is generated. The privileged message send and clear instructions (msgsndp & msgclrp) are used to generate and clear the presence of a directed privileged doorbell exception, respectively. The msgsndp instruction can be used to target any thread of the current subprocessor, msgclrp acts on the thread issuing the instruction. These instructions are privileged, but will generate a hypervisor facility unavailable exception if not enabled in the HFSCR and executed in privileged non-hypervisor state. The HV facility unavailable exception will be addressed in other patch. Add and implement this register and instructions by reading or modifying the pending interrupt state of the cpu. Note that TCG only supports one thread per core and so we only need to worry about the cpu making the access. Signed-off-by: Suraj Jitindar Singh Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/helper.h | 4 ++ target/ppc/excp_helper.c | 66 +++++++++++++++++++++++++-------- target/ppc/misc_helper.c | 36 ++++++++++++++++++ target/ppc/translate.c | 26 +++++++++++++ target/ppc/translate_init.inc.c | 20 ++++++++-- 5 files changed, 132 insertions(+), 20 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index cd0dfe383a2a..cfb4c07085ca 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -657,6 +657,10 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl,= env) DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_purr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_2(store_ptcr, void, env, tl) +DEF_HELPER_FLAGS_1(load_dpdes, TCG_CALL_NO_RWG, tl, env) +DEF_HELPER_FLAGS_2(store_dpdes, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_2(book3s_msgsndp, void, env, tl) +DEF_HELPER_2(book3s_msgclrp, void, env, tl) #endif DEF_HELPER_2(store_sdr1, void, env, tl) DEF_HELPER_2(store_pidr, void, env, tl) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5752ed4a4d83..1b07c3ed561e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -900,7 +900,11 @@ static void ppc_hw_interrupt(CPUPPCState *env) } if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DOORBELL); - powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); + if (is_book3s_arch2x(env)) { + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR); + } else { + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); + } return; } if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) { @@ -1221,39 +1225,30 @@ void helper_msgsnd(target_ulong rb) } =20 /* Server Processor Control */ -static int book3s_dbell2irq(target_ulong rb) -{ - int msg =3D rb & DBELL_TYPE_MASK; =20 +static bool dbell_type_server(target_ulong rb) +{ /* * A Directed Hypervisor Doorbell message is sent only if the * message type is 5. All other types are reserved and the * instruction is a no-op */ - return msg =3D=3D DBELL_TYPE_DBELL_SERVER ? PPC_INTERRUPT_HDOORBELL : = -1; + return (rb & DBELL_TYPE_MASK) =3D=3D DBELL_TYPE_DBELL_SERVER; } =20 void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) { - int irq =3D book3s_dbell2irq(rb); - - if (irq < 0) { + if (!dbell_type_server(rb)) { return; } =20 - env->pending_interrupts &=3D ~(1 << irq); + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_HDOORBELL); } =20 -void helper_book3s_msgsnd(target_ulong rb) +static void book3s_msgsnd_common(int pir, int irq) { - int irq =3D book3s_dbell2irq(rb); - int pir =3D rb & DBELL_PROCIDTAG_MASK; CPUState *cs; =20 - if (irq < 0) { - return; - } - qemu_mutex_lock_iothread(); CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -1267,6 +1262,45 @@ void helper_book3s_msgsnd(target_ulong rb) } qemu_mutex_unlock_iothread(); } + +void helper_book3s_msgsnd(target_ulong rb) +{ + int pir =3D rb & DBELL_PROCIDTAG_MASK; + + if (!dbell_type_server(rb)) { + return; + } + + book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL); +} + +#if defined(TARGET_PPC64) +void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) +{ + if (!dbell_type_server(rb)) { + return; + } + + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DOORBELL); +} + +/* + * sends a message to other threads that are on the same + * multi-threaded processor + */ +void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) +{ + int pir =3D env->spr_cb[SPR_PIR].default_value; + + if (!dbell_type_server(rb)) { + return; + } + + /* TODO: TCG supports only one thread */ + + book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); +} +#endif #endif =20 void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 2318f3ab45b2..0c5919ff08b0 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -105,6 +105,42 @@ void helper_store_pcr(CPUPPCState *env, target_ulong v= alue) =20 env->spr[SPR_PCR] =3D value & pcc->pcr_mask; } + +/* + * DPDES register is shared. Each bit reflects the state of the + * doorbell interrupt of a thread of the same core. + */ +target_ulong helper_load_dpdes(CPUPPCState *env) +{ + target_ulong dpdes =3D 0; + + /* TODO: TCG supports only one thread */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { + dpdes =3D 1; + } + + return dpdes; +} + +void helper_store_dpdes(CPUPPCState *env, target_ulong val) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D CPU(cpu); + + /* TODO: TCG supports only one thread */ + if (val & ~0x1) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " + TARGET_FMT_lx"\n", val); + return; + } + + if (val & 0x1) { + env->pending_interrupts |=3D 1 << PPC_INTERRUPT_DOORBELL; + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DOORBELL); + } +} #endif /* defined(TARGET_PPC64) */ =20 void helper_store_pidr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9dcf8dc2610a..36fa27367cb2 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6645,6 +6645,28 @@ static void gen_msgsnd(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } =20 +#if defined(TARGET_PPC64) +static void gen_msgclrp(DisasContext *ctx) +{ +#if defined(CONFIG_USER_ONLY) + GEN_PRIV; +#else + CHK_SV; + gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); +#endif /* defined(CONFIG_USER_ONLY) */ +} + +static void gen_msgsndp(DisasContext *ctx) +{ +#if defined(CONFIG_USER_ONLY) + GEN_PRIV; +#else + CHK_SV; + gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); +#endif /* defined(CONFIG_USER_ONLY) */ +} +#endif + static void gen_msgsync(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) @@ -7187,6 +7209,10 @@ GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000,= PPC_ALTIVEC), GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), +GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, + PPC_NONE, PPC2_ISA207S), +GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, + PPC_NONE, PPC2_ISA207S), #endif =20 #undef GEN_INT_ARITH_ADD diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index d33d65dff702..9e2396a7b5a1 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -464,6 +464,17 @@ static void spr_write_pcr(DisasContext *ctx, int sprn,= int gprn) { gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); } + +/* DPDES */ +static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); +} + +static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); +} #endif #endif =20 @@ -8238,10 +8249,11 @@ static void gen_spr_power8_dpdes(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) /* Directed Privileged Door-bell Exception State, used for IPI */ - spr_register(env, SPR_DPDES, "DPDES", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); + spr_register_kvm_hv(env, SPR_DPDES, "DPDES", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dpdes, SPR_NOACCESS, + &spr_read_dpdes, &spr_write_dpdes, + KVM_REG_PPC_DPDES, 0x00000000); #endif } =20 --=20 2.21.1 From nobody Thu May 2 11:50:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 20 Jan 2020 05:50:31 -0500 Received: from player718.ha.ovh.net (unknown [10.108.16.135]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 9CDD411F2D4 for ; Mon, 20 Jan 2020 11:50:27 +0100 (CET) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id 922BDE506393; Mon, 20 Jan 2020 10:49:54 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH v2 2/2] target/ppc: add support for Hypervisor Facility Unavailable Exception Date: Mon, 20 Jan 2020 11:49:35 +0100 Message-Id: <20200120104935.24449-3-clg@kaod.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200120104935.24449-1-clg@kaod.org> References: <20200120104935.24449-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 9644740080235088870 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedugedrudehgddugecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdekvddrieegrddvhedtrddujedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejudekrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedt Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.37.72 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The privileged message send and clear instructions (msgsndp & msgclrp) are privileged, but will generate a hypervisor facility unavailable exception if not enabled in the HFSCR and executed in privileged non-hypervisor state. Add checks when accessing the DPDES register and when using the msgsndp and msgclrp isntructions. Signed-off-by: Suraj Jitindar Singh Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 6 ++++++ target/ppc/excp_helper.c | 13 +++++++++++++ target/ppc/misc_helper.c | 27 +++++++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8ebeaba649d0..96aeea1934d8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -397,6 +397,10 @@ typedef struct ppc_v3_pate_t { #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ =20 +/* HFSCR bits */ +#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ +#define HFSCR_IC_MSGP 0xA + #define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1) #define msr_shv ((env->msr >> MSR_SHV) & 1) @@ -1329,6 +1333,8 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHype= rvisor *vhyp); #endif =20 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, + const char *caller, uint32_t cause); =20 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) { diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1b07c3ed561e..027f54c0ed5f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -471,6 +471,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) case POWERPC_EXCP_FU: /* Facility unavailable exception = */ #ifdef TARGET_PPC64 env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); +#endif + break; + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ +#ifdef TARGET_PPC64 + env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); #endif break; case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ @@ -1277,6 +1286,8 @@ void helper_book3s_msgsnd(target_ulong rb) #if defined(TARGET_PPC64) void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) { + helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP); + if (!dbell_type_server(rb)) { return; } @@ -1292,6 +1303,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_u= long rb) { int pir =3D env->spr_cb[SPR_PIR].default_value; =20 + helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); + if (!dbell_type_server(rb)) { return; } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 0c5919ff08b0..55b68d1246e4 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -41,6 +41,18 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sp= rn) } =20 #ifdef TARGET_PPC64 +static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, + const char *caller, uint32_t cause, + uintptr_t raddr) +{ + qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n", + bit, caller); + + env->spr[SPR_HFSCR] &=3D ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); + + raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); +} + static void raise_fu_exception(CPUPPCState *env, uint32_t bit, uint32_t sprn, uint32_t cause, uintptr_t raddr) @@ -55,6 +67,17 @@ static void raise_fu_exception(CPUPPCState *env, uint32_= t bit, } #endif =20 +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, + const char *caller, uint32_t cause) +{ +#ifdef TARGET_PPC64 + if ((env->msr_mask & MSR_HVB) && !msr_hv && + !(env->spr[SPR_HFSCR] & (1UL << bit))= ) { + raise_hv_fu_exception(env, bit, caller, cause, GETPC()); + } +#endif +} + void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, uint32_t sprn, uint32_t cause) { @@ -114,6 +137,8 @@ target_ulong helper_load_dpdes(CPUPPCState *env) { target_ulong dpdes =3D 0; =20 + helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MS= GP); + /* TODO: TCG supports only one thread */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { dpdes =3D 1; @@ -127,6 +152,8 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong = val) PowerPCCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 + helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_M= SGP); + /* TODO: TCG supports only one thread */ if (val & ~0x1) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " --=20 2.21.1