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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:12 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dBNp37028226 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:11 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7714AAE045; Fri, 17 Jan 2020 09:39:11 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E6089AE055; Fri, 17 Jan 2020 09:39:09 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:09 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 1/7] Wrapper function to wait on condition for the main loop mutex Date: Fri, 17 Jan 2020 15:08:49 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-0016-0000-0000-000002DE32F9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-0017-0000-0000-00003340CE2C Message-Id: <20200117093855.19074-2-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxlogscore=788 impostorscore=0 adultscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad Introduce a wrapper function to wait on condition for the main loop mutex. This function atomically releases the main loop mutex and causes the calling thread to block on the condition. This wrapper is required because qemu_global_mutex is a static variable. Signed-off-by: Aravinda Prasad Signed-off-by: Ganesh Goudar Reviewed-by: David Gibson Reviewed-by: Greg Kurz --- cpus.c | 5 +++++ include/qemu/main-loop.h | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/cpus.c b/cpus.c index be2d655f37..c06a2ad20b 100644 --- a/cpus.c +++ b/cpus.c @@ -1839,6 +1839,11 @@ void qemu_mutex_unlock_iothread(void) qemu_mutex_unlock(&qemu_global_mutex); } =20 +void qemu_cond_wait_iothread(QemuCond *cond) +{ + qemu_cond_wait(cond, &qemu_global_mutex); +} + static bool all_vcpus_paused(void) { CPUState *cpu; diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h index f6ba78ea73..a6d20b0719 100644 --- a/include/qemu/main-loop.h +++ b/include/qemu/main-loop.h @@ -295,6 +295,14 @@ void qemu_mutex_lock_iothread_impl(const char *file, i= nt line); */ void qemu_mutex_unlock_iothread(void); =20 +/* + * qemu_cond_wait_iothread: Wait on condition for the main loop mutex + * + * This function atomically releases the main loop mutex and causes + * the calling thread to block on the condition. + */ +void qemu_cond_wait_iothread(QemuCond *cond); + /* internal interfaces */ =20 void qemu_fd_register(int fd); --=20 2.17.2 From nobody Wed May 1 19:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1579254215; cv=none; d=zohomail.com; s=zohoarc; b=StKgKnx1yWZrLSWiTZsSe9vXL3NA4nYOGGw0VM3Z/rag9B1No8hl/kbPX+9496G2z6jIQ1STc+ucpT5AyhUnLyeeEptVDFlHFH6RAbzKxUI1Pds5TBgOClESYZF6JJY1c5ewrL1WsBGDqUpcfkETqnUrnEDw86Sej354pXfZ/80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1579254215; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=hStOpiD4EOwsxWoSUwlFdBfVmIw68kjkIDPH3xflJlk=; b=KSQUC/HF9u04O8QPDllswiTvFIUEpvJdeb8FVQv/luothGPgckM2MwpNVK2l5/H2FEOWDvX1tpuUD62u5H1Pgz3eBjouEqGhJ5ssacogh4i7X8tpL3O/TrfUygwMnhPf8mCVn/WG28iRXCqMtR+7WYj8umG3+r4NGD1H1sASJ/o= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1579254215371633.786432712845; Fri, 17 Jan 2020 01:43:35 -0800 (PST) Received: from localhost ([::1]:54546 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1isOA9-0003bh-Tx for importer@patchew.org; Fri, 17 Jan 2020 04:43:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49497) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1isO6C-0006yn-PM for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1isO68-00071C-J0 for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:28 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:24792) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1isO68-00070Q-Ap for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:24 -0500 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00H9b5PT143819 for ; Fri, 17 Jan 2020 04:39:23 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xk0qsxn8e-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 17 Jan 2020 04:39:23 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:17 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dGSD40698106 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:16 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 482E4AE05D; Fri, 17 Jan 2020 09:39:16 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BAFC1AE053; Fri, 17 Jan 2020 09:39:14 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:14 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 2/7] ppc: spapr: Introduce FWNMI capability Date: Fri, 17 Jan 2020 15:08:50 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-0028-0000-0000-000003D1EF7A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-0029-0000-0000-000024961A4A Message-Id: <20200117093855.19074-3-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 mlxlogscore=681 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad Introduce fwnmi an spapr capability and add a helper function which tries to enable it, which would be used by following patch of the series. This patch by itself does not change the existing behavior. Signed-off-by: Aravinda Prasad [eliminate cap_ppc_fwnmi, add fwnmi cap to migration state and reprhase the commit message] Signed-off-by: Ganesh Goudar Reviewed-by: David Gibson --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c | 18 ++++++++++++++++++ include/hw/ppc/spapr.h | 5 ++++- target/ppc/kvm.c | 8 ++++++++ target/ppc/kvm_ppc.h | 6 ++++++ 5 files changed, 38 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 30a5fbd3be..f5c036d3d9 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1992,6 +1992,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_dtb, &vmstate_spapr_cap_large_decr, &vmstate_spapr_cap_ccf_assist, + &vmstate_spapr_cap_fwnmi, NULL } }; @@ -4398,6 +4399,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_OFF; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 481dfd2a27..3001098601 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -496,6 +496,14 @@ static void cap_ccf_assist_apply(SpaprMachineState *sp= apr, uint8_t val, } } =20 +static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val, + Error **errp) +{ + if (!val) { + return; /* Disabled by default */ + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { [SPAPR_CAP_HTM] =3D { .name =3D "htm", @@ -595,6 +603,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_ccf_assist_apply, }, + [SPAPR_CAP_FWNMI_MCE] =3D { + .name =3D "fwnmi-mce", + .description =3D "Handle fwnmi machine check exceptions", + .index =3D SPAPR_CAP_FWNMI_MCE, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_fwnmi_mce_apply, + }, }; =20 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -734,6 +751,7 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXP= AGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); +SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE); =20 void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 61f005c6f6..7bc5fc3a9e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -79,8 +79,10 @@ typedef enum { #define SPAPR_CAP_LARGE_DECREMENTER 0x08 /* Count Cache Flush Assist HW Instruction */ #define SPAPR_CAP_CCF_ASSIST 0x09 +/* FWNMI machine check handling */ +#define SPAPR_CAP_FWNMI_MCE 0x0A /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) =20 /* * Capability Values @@ -869,6 +871,7 @@ extern const VMStateDescription vmstate_spapr_cap_hpt_m= axpagesize; extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; extern const VMStateDescription vmstate_spapr_cap_large_decr; extern const VMStateDescription vmstate_spapr_cap_ccf_assist; +extern const VMStateDescription vmstate_spapr_cap_fwnmi; =20 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) { diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index b5799e62b4..9161eea865 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2054,6 +2054,14 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic= _proxy) } } =20 +int kvmppc_set_fwnmi(void) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + CPUState *cs =3D CPU(cpu); + + return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); +} + int kvmppc_smt_threads(void) { return cap_ppc_smt ? cap_ppc_smt : 1; diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index b713097bfb..2c60dedd0d 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -27,6 +27,7 @@ void kvmppc_enable_h_page_init(void); void kvmppc_set_papr(PowerPCCPU *cpu); int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); +int kvmppc_set_fwnmi(void); int kvmppc_smt_threads(void); void kvmppc_error_append_smt_possible_hint(Error *const *errp); int kvmppc_set_smt_threads(int smt); @@ -160,6 +161,11 @@ static inline void kvmppc_set_mpic_proxy(PowerPCCPU *c= pu, int mpic_proxy) { } =20 +static inline int kvmppc_set_fwnmi(void) +{ + return -1; +} + static inline int kvmppc_smt_threads(void) { return 1; --=20 2.17.2 From nobody Wed May 1 19:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1579254314; cv=none; d=zohomail.com; s=zohoarc; b=K/xKnGj8MY43uTPIJCkdW9VC7QVD9NsnKkdCmc4PrBDzDayEcejMNQuZaBhuHqqW82GmMT9KjXWv6JSuHmNYw5o3O7a5jU/MTzLQV0eKOAWlAAXGQV9yjtr4nSRkPG5fpOj1HywFywiY4DHjIyq1qSajzZ56pSz3pZ+NqrEMT/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1579254314; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=OyGMne4mdhNEDP80qWJ2/m9xMtwspiLUgPC4wTo4c8M=; b=B31E+FJ+Vt71R8EaRArz+4eH7JtCaNri/GecQe+/wsQl8CFHFZlT1QNRfsXw6WYNDKX1XpgXJCnCzFW/6PLNdBn34JEdGbZcGzVCO+nL9u+MXuX4ztTWrqqBGG/g3MTsrGESscuaw1vZ24dUw/ZXh6+coaM+Y0nsszrgb1QBQx4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1579254314904428.1498636697447; Fri, 17 Jan 2020 01:45:14 -0800 (PST) Received: from localhost ([::1]:54568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1isOBl-0005wD-R3 for importer@patchew.org; Fri, 17 Jan 2020 04:45:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49529) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1isO6I-00072t-Ns for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1isO6E-00075Z-Vy for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:34 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:63190 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1isO6E-000752-Rj for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:30 -0500 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00H9b5l6022954 for ; Fri, 17 Jan 2020 04:39:30 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2xk0qrpme5-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 17 Jan 2020 04:39:30 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:26 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dPMF46072298 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:25 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 06620AE04D; Fri, 17 Jan 2020 09:39:25 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 79A40AE045; Fri, 17 Jan 2020 09:39:23 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:23 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 3/7] target/ppc: Handle NMI guest exit Date: Fri, 17 Jan 2020 15:08:51 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-4275-0000-0000-000003986C74 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-4276-0000-0000-000038AC6D71 Message-Id: <20200117093855.19074-4-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad Memory error such as bit flips that cannot be corrected by hardware are passed on to the kernel for handling. If the memory address in error belongs to guest then the guest kernel is responsible for taking suitable action. Patch [1] enhances KVM to exit guest with exit reason set to KVM_EXIT_NMI in such cases. This patch handles KVM_EXIT_NMI exit. [1] https://www.spinics.net/lists/kvm-ppc/msg12637.html (e20bbd3d and related commits) Signed-off-by: Aravinda Prasad Signed-off-by: Ganesh Goudar Reviewed-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 8 ++++++++ hw/ppc/spapr_events.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 10 ++++++++++ target/ppc/kvm.c | 14 ++++++++++++++ target/ppc/kvm_ppc.h | 2 ++ target/ppc/trace-events | 1 + 6 files changed, 72 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f5c036d3d9..46bac1a83c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1677,6 +1677,12 @@ static void spapr_machine_reset(MachineState *machin= e) first_ppc_cpu->env.gpr[5] =3D 0; =20 spapr->cas_reboot =3D false; + + spapr->mc_status =3D -1; + spapr->guest_machine_check_addr =3D -1; + + /* Signal all vCPUs waiting on this condition */ + qemu_cond_broadcast(&spapr->mc_delivery_cond); } =20 static void spapr_create_nvram(SpaprMachineState *spapr) @@ -2971,6 +2977,8 @@ static void spapr_machine_init(MachineState *machine) =20 kvmppc_spapr_enable_inkernel_multitce(); } + + qemu_cond_init(&spapr->mc_delivery_cond); } =20 static int spapr_kvm_type(MachineState *machine, const char *vm_type) diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index e355e000d0..dfc0de840a 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -40,6 +40,7 @@ #include "hw/ppc/spapr_drc.h" #include "qemu/help_option.h" #include "qemu/bcd.h" +#include "qemu/main-loop.h" #include "hw/ppc/spapr_ovec.h" #include =20 @@ -622,6 +623,42 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprDr= cType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_i= d); } =20 +void spapr_mce_req_event(PowerPCCPU *cpu) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + CPUState *cs =3D CPU(cpu); + + if (spapr->guest_machine_check_addr =3D=3D -1) { + /* + * This implies that we have hit a machine check either when the + * guest has not registered FWNMI (i.e., "ibm,nmi-register" not + * called) or between system reset and "ibm,nmi-register". + * Fall back to the old machine check behavior in such cases. + */ + cs->exception_index =3D POWERPC_EXCP_MCHECK; + ppc_cpu_do_interrupt(cs); + return; + } + + while (spapr->mc_status !=3D -1) { + /* + * Check whether the same CPU got machine check error + * while still handling the mc error (i.e., before + * that CPU called "ibm,nmi-interlock") + */ + if (spapr->mc_status =3D=3D cpu->vcpu_id) { + qemu_system_guest_panicked(NULL); + return; + } + qemu_cond_wait_iothread(&spapr->mc_delivery_cond); + /* Meanwhile if the system is reset, then just return */ + if (spapr->guest_machine_check_addr =3D=3D -1) { + return; + } + } + spapr->mc_status =3D cpu->vcpu_id; +} + static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 7bc5fc3a9e..909d3976f9 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -191,6 +191,15 @@ struct SpaprMachineState { * occurs during the unplug process. */ QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; =20 + /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */ + target_ulong guest_machine_check_addr; + /* + * mc_status is set to -1 if mc is not in progress, else is set to the= CPU + * handling the mc. + */ + int mc_status; + QemuCond mc_delivery_cond; + /*< public >*/ char *kvm_type; char *host_model; @@ -804,6 +813,7 @@ void spapr_clear_pending_events(SpaprMachineState *spap= r); int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); +void spapr_mce_req_event(PowerPCCPU *cpu); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 9161eea865..21a4c79d41 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1702,6 +1702,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_ru= n *run) ret =3D 0; break; =20 + case KVM_EXIT_NMI: + trace_kvm_handle_nmi_exception(); + ret =3D kvm_handle_nmi(cpu, run); + break; + default: fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); ret =3D -1; @@ -2797,6 +2802,15 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) return data & 0xffff; } =20 +int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) +{ + cpu_synchronize_state(CPU(cpu)); + + spapr_mce_req_event(cpu); + + return 0; +} + int kvmppc_enable_hwrng(void) { if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRN= G)) { diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 2c60dedd0d..9e4f2357cc 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -84,6 +84,8 @@ void kvm_check_mmu(PowerPCCPU *cpu, Error **errp); void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online); void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset); =20 +int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run); + #else =20 static inline uint32_t kvmppc_get_tbfreq(void) diff --git a/target/ppc/trace-events b/target/ppc/trace-events index 3dc6740706..6d15aa90b4 100644 --- a/target/ppc/trace-events +++ b/target/ppc/trace-events @@ -28,3 +28,4 @@ kvm_handle_papr_hcall(void) "handle PAPR hypercall" kvm_handle_epr(void) "handle epr" kvm_handle_watchdog_expiry(void) "handle watchdog expiry" kvm_handle_debug_exception(void) "handle debug exception" +kvm_handle_nmi_exception(void) "handle NMI exception" --=20 2.17.2 From nobody Wed May 1 19:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:31 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dUNi62652416 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:30 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B049AAE058; Fri, 17 Jan 2020 09:39:30 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2FABAAE055; Fri, 17 Jan 2020 09:39:29 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:29 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 4/7] target/ppc: Build rtas error log upon an MCE Date: Fri, 17 Jan 2020 15:08:52 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-0028-0000-0000-000003D1EF7F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-0029-0000-0000-000024961A50 Message-Id: <20200117093855.19074-5-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 mlxscore=0 suspectscore=2 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad Upon a machine check exception (MCE) in a guest address space, KVM causes a guest exit to enable QEMU to build and pass the error to the guest in the PAPR defined rtas error log format. This patch builds the rtas error log, copies it to the rtas_addr and then invokes the guest registered machine check handler. The handler in the guest takes suitable action(s) depending on the type and criticality of the error. For example, if an error is unrecoverable memory corruption in an application inside the guest, then the guest kernel sends a SIGBUS to the application. For recoverable errors, the guest performs recovery actions and logs the error. Signed-off-by: Aravinda Prasad [Assume SLOF has allocated enough room for rtas error log] Signed-off-by: Ganesh Goudar Reviewed-by: David Gibson --- hw/ppc/spapr_events.c | 220 ++++++++++++++++++++++++++++++++++++++++- hw/ppc/spapr_rtas.c | 26 +++++ include/hw/ppc/spapr.h | 6 +- target/ppc/kvm.c | 4 +- 4 files changed, 253 insertions(+), 3 deletions(-) diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index dfc0de840a..54eaf28a9e 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -214,6 +214,104 @@ struct hp_extended_log { struct rtas_event_log_v6_hp hp; } QEMU_PACKED; =20 +struct rtas_event_log_v6_mc { +#define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */ + struct rtas_event_log_v6_section_header hdr; + uint32_t fru_id; + uint32_t proc_id; + uint8_t error_type; +#define RTAS_LOG_V6_MC_TYPE_UE 0 +#define RTAS_LOG_V6_MC_TYPE_SLB 1 +#define RTAS_LOG_V6_MC_TYPE_ERAT 2 +#define RTAS_LOG_V6_MC_TYPE_TLB 4 +#define RTAS_LOG_V6_MC_TYPE_D_CACHE 5 +#define RTAS_LOG_V6_MC_TYPE_I_CACHE 7 + uint8_t sub_err_type; +#define RTAS_LOG_V6_MC_UE_INDETERMINATE 0 +#define RTAS_LOG_V6_MC_UE_IFETCH 1 +#define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2 +#define RTAS_LOG_V6_MC_UE_LOAD_STORE 3 +#define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4 +#define RTAS_LOG_V6_MC_SLB_PARITY 0 +#define RTAS_LOG_V6_MC_SLB_MULTIHIT 1 +#define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2 +#define RTAS_LOG_V6_MC_ERAT_PARITY 1 +#define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2 +#define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3 +#define RTAS_LOG_V6_MC_TLB_PARITY 1 +#define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 +#define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 + uint8_t reserved_1[6]; + uint64_t effective_address; + uint64_t logical_address; +} QEMU_PACKED; + +struct mc_extended_log { + struct rtas_event_log_v6 v6hdr; + struct rtas_event_log_v6_mc mc; +} QEMU_PACKED; + +struct MC_ierror_table { + unsigned long srr1_mask; + unsigned long srr1_value; + bool nip_valid; /* nip is a valid indicator of faulting address */ + uint8_t error_type; + uint8_t error_subtype; + unsigned int initiator; + unsigned int severity; +}; + +static const struct MC_ierror_table mc_ierror_table[] =3D { +{ 0x00000000081c0000, 0x0000000000040000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000080000, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x00000000000c0000, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000100000, true, + RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000140000, true, + RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000180000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; + +struct MC_derror_table { + unsigned long dsisr_value; + bool dar_valid; /* dar is a valid indicator of faulting address */ + uint8_t error_type; + uint8_t error_subtype; + unsigned int initiator; + unsigned int severity; +}; + +static const struct MC_derror_table mc_derror_table[] =3D { +{ 0x00008000, false, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00004000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000800, true, + RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000400, true, + RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000080, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY = */ + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000100, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; + +#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) + typedef enum EventClass { EVENT_CLASS_INTERNAL_ERRORS =3D 0, EVENT_CLASS_EPOW =3D 1, @@ -623,7 +721,125 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprD= rcType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_i= d); } =20 -void spapr_mce_req_event(PowerPCCPU *cpu) +static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, + struct mc_extended_log *ext_elog) +{ + int i; + CPUPPCState *env =3D &cpu->env; + uint32_t summary; + uint64_t dsisr =3D env->spr[SPR_DSISR]; + + summary =3D RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT; + if (recovered) { + summary |=3D RTAS_LOG_DISPOSITION_FULLY_RECOVERED; + } else { + summary |=3D RTAS_LOG_DISPOSITION_NOT_RECOVERED; + } + + if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) { + for (i =3D 0; i < ARRAY_SIZE(mc_derror_table); i++) { + if (!(dsisr & mc_derror_table[i].dsisr_value)) { + continue; + } + + ext_elog->mc.error_type =3D mc_derror_table[i].error_type; + ext_elog->mc.sub_err_type =3D mc_derror_table[i].error_subtype; + if (mc_derror_table[i].dar_valid) { + ext_elog->mc.effective_address =3D cpu_to_be64(env->spr[SP= R_DAR]); + } + + summary |=3D mc_derror_table[i].initiator + | mc_derror_table[i].severity; + + return summary; + } + } else { + for (i =3D 0; i < ARRAY_SIZE(mc_ierror_table); i++) { + if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) !=3D + mc_ierror_table[i].srr1_value) { + continue; + } + + ext_elog->mc.error_type =3D mc_ierror_table[i].error_type; + ext_elog->mc.sub_err_type =3D mc_ierror_table[i].error_subtype; + if (mc_ierror_table[i].nip_valid) { + ext_elog->mc.effective_address =3D cpu_to_be64(env->nip); + } + + summary |=3D mc_ierror_table[i].initiator + | mc_ierror_table[i].severity; + + return summary; + } + } + + summary |=3D RTAS_LOG_INITIATOR_CPU; + return summary; +} + +static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, bool recovered) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + CPUState *cs =3D CPU(cpu); + uint64_t rtas_addr; + CPUPPCState *env =3D &cpu->env; + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + target_ulong msr =3D 0; + struct rtas_error_log log; + struct mc_extended_log *ext_elog; + uint32_t summary; + + /* + * Properly set bits in MSR before we invoke the handler. + * SRR0/1, DAR and DSISR are properly set by KVM + */ + if (!(*pcc->interrupts_big_endian)(cpu)) { + msr |=3D (1ULL << MSR_LE); + } + + if (env->msr & (1ULL << MSR_SF)) { + msr |=3D (1ULL << MSR_SF); + } + + msr |=3D (1ULL << MSR_ME); + + ext_elog =3D g_malloc0(sizeof(*ext_elog)); + summary =3D spapr_mce_get_elog_type(cpu, recovered, ext_elog); + + log.summary =3D cpu_to_be32(summary); + log.extended_length =3D cpu_to_be32(sizeof(*ext_elog)); + + spapr_init_v6hdr(&ext_elog->v6hdr); + ext_elog->mc.hdr.section_id =3D cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC); + ext_elog->mc.hdr.section_length =3D + cpu_to_be16(sizeof(struct rtas_event_log_v6_mc)); + ext_elog->mc.hdr.section_version =3D 1; + + /* get rtas addr from fdt */ + rtas_addr =3D spapr_get_rtas_addr(); + if (!rtas_addr) { + /* Unable to fetch rtas_addr. Hence reset the guest */ + ppc_cpu_do_system_reset(cs); + g_free(ext_elog); + return; + } + + stq_be_phys(&address_space_memory, rtas_addr + RTAS_ERROR_LOG_OFFSET, + env->gpr[3]); + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + + sizeof(env->gpr[3]), &log, sizeof(log)); + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + + sizeof(env->gpr[3]) + sizeof(log), ext_elog, + sizeof(*ext_elog)); + + env->gpr[3] =3D rtas_addr + RTAS_ERROR_LOG_OFFSET; + env->msr =3D msr; + env->nip =3D spapr->guest_machine_check_addr; + + g_free(ext_elog); +} + +void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); CPUState *cs =3D CPU(cpu); @@ -657,6 +873,8 @@ void spapr_mce_req_event(PowerPCCPU *cpu) } } spapr->mc_status =3D cpu->vcpu_id; + + spapr_mce_dispatch_elog(cpu, recovered); } =20 static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8d8d8cdfcb..2c066a372d 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -477,6 +477,32 @@ void spapr_dt_rtas_tokens(void *fdt, int rtas) } } =20 +hwaddr spapr_get_rtas_addr(void) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + int rtas_node; + const fdt32_t *rtas_data; + void *fdt =3D spapr->fdt_blob; + + /* fetch rtas addr from fdt */ + rtas_node =3D fdt_path_offset(fdt, "/rtas"); + if (rtas_node < 0) { + return 0; + } + + rtas_data =3D fdt_getprop(fdt, rtas_node, "linux,rtas-base", NULL); + if (!rtas_data) { + return 0; + } + + /* + * We assume that the OS called RTAS instantiate-rtas, but some other + * OS might call RTAS instantiate-rtas-64 instead. This fine as of now + * as SLOF only supports 32-bit variant. + */ + return (hwaddr)fdt32_to_cpu(*rtas_data); +} + static void core_rtas_register_types(void) { spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 909d3976f9..652a5514e8 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -727,6 +727,9 @@ void spapr_load_rtas(SpaprMachineState *spapr, void *fd= t, hwaddr addr); =20 #define RTAS_ERROR_LOG_MAX 2048 =20 +/* Offset from rtas-base where error log is placed */ +#define RTAS_ERROR_LOG_OFFSET 0x30 + #define RTAS_EVENT_SCAN_RATE 1 =20 /* This helper should be used to encode interrupt specifiers when the rela= ted @@ -813,7 +816,7 @@ void spapr_clear_pending_events(SpaprMachineState *spap= r); int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); -void spapr_mce_req_event(PowerPCCPU *cpu); +void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); @@ -904,4 +907,5 @@ void spapr_check_pagesize(SpaprMachineState *spapr, hwa= ddr pagesize, #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform = */ =20 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); +hwaddr spapr_get_rtas_addr(void); #endif /* HW_SPAPR_H */ diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 21a4c79d41..8fd4298372 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2804,9 +2804,11 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) =20 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) { + bool recovered =3D run->flags & KVM_RUN_PPC_NMI_DISP_FULLY_RECOV; + cpu_synchronize_state(CPU(cpu)); =20 - spapr_mce_req_event(cpu); + spapr_mce_req_event(cpu, recovered); =20 return 0; } --=20 2.17.2 From nobody Wed May 1 19:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1579254557; cv=none; d=zohomail.com; s=zohoarc; b=AVOY0JrIjnWYxeSlI0AzjIjIu1IiQWmjw3W/fbd8yEjra8+zfDXHspN60zbiwO8MajoYUFRegdOch+gnmvqjKMhck+rosFeGcpbnU9C8en295B78LcUoD+84rWaYS1eErfSeDOB5c34jHPAOFZBnzw9PuR73jdUPshNIubz3tUg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1579254557; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=tld4hkjijVKjjFTlmzUEh7uAkecb/K0YDYmK5lA0snI=; b=U6Dhly7r9svQ3Sk0lFs6v3Lfuzo2VrvuxdNaTbeAvUwa3/rz4k34dNa7xwPSY0QAb+ohmMyTtxM5874SkWnlx7J7ocglLrt76zQpSrw/ActiTZ0FasXdNLBvNhudoWnu7LAvFjxK17z5XGnsq7MOGUqXjKK67a0u9XxrJRDqAVk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1579254557035566.0594382434302; Fri, 17 Jan 2020 01:49:17 -0800 (PST) Received: from localhost ([::1]:54630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1isOFf-0000xZ-Ts for importer@patchew.org; Fri, 17 Jan 2020 04:49:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49622) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1isO6W-0007MP-3B for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1isO6S-0007FH-0u for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:47 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:13542) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1isO6R-0007EZ-P0 for qemu-devel@nongnu.org; Fri, 17 Jan 2020 04:39:43 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00H9b9BX056888 for ; Fri, 17 Jan 2020 04:39:43 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xk0qsxsyr-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 17 Jan 2020 04:39:42 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:37 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dbX161145192 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:37 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0B47FAE053; Fri, 17 Jan 2020 09:39:37 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7E99AAE045; Fri, 17 Jan 2020 09:39:35 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:35 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 5/7] ppc: spapr: Handle "ibm, nmi-register" and "ibm, nmi-interlock" RTAS calls Date: Fri, 17 Jan 2020 15:08:53 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-0028-0000-0000-000003D1EF82 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-0029-0000-0000-000024961A52 Message-Id: <20200117093855.19074-6-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad This patch adds support in QEMU to handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls. The machine check notification address is saved when the OS issues "ibm,nmi-register" RTAS call. This patch also handles the case when multiple processors experience machine check at or about the same time by handling "ibm,nmi-interlock" call. In such cases, as per PAPR, subsequent processors serialize waiting for the first processor to issue the "ibm,nmi-interlock" call. The second processor that also received a machine check error waits till the first processor is done reading the error log. The first processor issues "ibm,nmi-interlock" call when the error log is consumed. Signed-off-by: Aravinda Prasad [Register fwnmi RTAS calls in core_rtas_register_types() where other RTAS calls are registered] Signed-off-by: Ganesh Goudar --- hw/ppc/spapr_caps.c | 7 +++++ hw/ppc/spapr_rtas.c | 59 ++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 4 ++- 3 files changed, 69 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 3001098601..c43498da49 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -502,6 +502,13 @@ static void cap_fwnmi_mce_apply(SpaprMachineState *spa= pr, uint8_t val, if (!val) { return; /* Disabled by default */ } + + if (kvm_enabled()) { + if (kvmppc_set_fwnmi() < 0) { + error_report("Could not enable fwnmi capability"); + exit(1); + } + } } =20 SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 2c066a372d..3f162d82f5 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -400,6 +400,61 @@ static void rtas_get_power_level(PowerPCCPU *cpu, Spap= rMachineState *spapr, rtas_st(rets, 1, 100); } =20 +static void rtas_ibm_nmi_register(PowerPCCPU *cpu, + SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + hwaddr rtas_addr; + + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D SPAPR_CAP_OFF) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + rtas_addr =3D spapr_get_rtas_addr(); + if (!rtas_addr) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + spapr->guest_machine_check_addr =3D rtas_ld(args, 1); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + +static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, + SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D SPAPR_CAP_OFF) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + if (spapr->guest_machine_check_addr =3D=3D -1) { + /* NMI register not called */ + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + if (spapr->mc_status !=3D cpu->vcpu_id) { + /* The vCPU that hit the NMI should invoke "ibm,nmi-interlock" */ + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + /* + * vCPU issuing "ibm,nmi-interlock" is done with NMI handling, + * hence unset mc_status. + */ + spapr->mc_status =3D -1; + qemu_cond_signal(&spapr->mc_delivery_cond); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + static struct rtas_call { const char *name; spapr_rtas_fn fn; @@ -528,6 +583,10 @@ static void core_rtas_register_types(void) rtas_set_power_level); spapr_rtas_register(RTAS_GET_POWER_LEVEL, "get-power-level", rtas_get_power_level); + spapr_rtas_register(RTAS_IBM_NMI_REGISTER, "ibm,nmi-register", + rtas_ibm_nmi_register); + spapr_rtas_register(RTAS_IBM_NMI_INTERLOCK, "ibm,nmi-interlock", + rtas_ibm_nmi_interlock); } =20 type_init(core_rtas_register_types) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 652a5514e8..f6f82d88aa 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -656,8 +656,10 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_u= long opcode, #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) +#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) +#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2B) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 --=20 2.17.2 From nobody Wed May 1 19:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:44 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dhNu43909314 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:43 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A31CAE057; Fri, 17 Jan 2020 09:39:43 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CCF9DAE045; Fri, 17 Jan 2020 09:39:41 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:41 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 6/7] migration: Include migration support for machine check handling Date: Fri, 17 Jan 2020 15:08:54 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-0012-0000-0000-0000037E33B2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-0013-0000-0000-000021BA69FC Message-Id: <20200117093855.19074-7-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 impostorscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad This patch includes migration support for machine check handling. Especially this patch blocks VM migration requests until the machine check error handling is complete as these errors are specific to the source hardware and is irrelevant on the target hardware. Signed-off-by: Aravinda Prasad [Do not set FWNMI cap in post_load, now its done in .apply hook] Signed-off-by: Ganesh Goudar --- hw/ppc/spapr.c | 47 ++++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_events.c | 16 +++++++++++++- hw/ppc/spapr_rtas.c | 2 ++ include/hw/ppc/spapr.h | 2 ++ 4 files changed, 66 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 46bac1a83c..c8bc2fa9f3 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -46,6 +46,7 @@ #include "migration/qemu-file-types.h" #include "migration/global_state.h" #include "migration/register.h" +#include "migration/blocker.h" #include "mmu-hash64.h" #include "mmu-book3s-v3.h" #include "cpu-models.h" @@ -1683,6 +1684,8 @@ static void spapr_machine_reset(MachineState *machine) =20 /* Signal all vCPUs waiting on this condition */ qemu_cond_broadcast(&spapr->mc_delivery_cond); + + migrate_del_blocker(spapr->fwnmi_migration_blocker); } =20 static void spapr_create_nvram(SpaprMachineState *spapr) @@ -1965,6 +1968,42 @@ static const VMStateDescription vmstate_spapr_dtb = =3D { }, }; =20 +static bool spapr_fwnmi_needed(void *opaque) +{ + SpaprMachineState *spapr =3D (SpaprMachineState *)opaque; + + return spapr->guest_machine_check_addr !=3D -1; +} + +static int spapr_fwnmi_pre_save(void *opaque) +{ + SpaprMachineState *spapr =3D (SpaprMachineState *)opaque; + + /* + * Check if machine check handling is in progress and print a + * warning message. + */ + if (spapr->mc_status !=3D -1) { + warn_report("A machine check is being handled during migration. Th= e" + "handler may run and log hardware error on the destination= "); + } + + return 0; +} + +static const VMStateDescription vmstate_spapr_machine_check =3D { + .name =3D "spapr_machine_check", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D spapr_fwnmi_needed, + .pre_save =3D spapr_fwnmi_pre_save, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), + VMSTATE_INT32(mc_status, SpaprMachineState), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_spapr =3D { .name =3D "spapr", .version_id =3D 3, @@ -1999,6 +2038,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_cap_large_decr, &vmstate_spapr_cap_ccf_assist, &vmstate_spapr_cap_fwnmi, + &vmstate_spapr_machine_check, NULL } }; @@ -2814,6 +2854,13 @@ static void spapr_machine_init(MachineState *machine) spapr_create_lmb_dr_connectors(spapr); } =20 + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D SPAPR_CAP_ON) { + /* Create the error string for live migration blocker */ + error_setg(&spapr->fwnmi_migration_blocker, + "A machine check is being handled during migration. The handle= r" + "may run and log hardware error on the destination"); + } + /* Set up RTAS event infrastructure */ spapr_events_init(spapr); =20 diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index 54eaf28a9e..884e455f02 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -43,6 +43,7 @@ #include "qemu/main-loop.h" #include "hw/ppc/spapr_ovec.h" #include +#include "migration/blocker.h" =20 #define RTAS_LOG_VERSION_MASK 0xff000000 #define RTAS_LOG_VERSION_6 0x06000000 @@ -843,6 +844,8 @@ void spapr_mce_req_event(PowerPCCPU *cpu, bool recovere= d) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); CPUState *cs =3D CPU(cpu); + int ret; + Error *local_err =3D NULL; =20 if (spapr->guest_machine_check_addr =3D=3D -1) { /* @@ -872,8 +875,19 @@ void spapr_mce_req_event(PowerPCCPU *cpu, bool recover= ed) return; } } - spapr->mc_status =3D cpu->vcpu_id; =20 + ret =3D migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err= ); + if (ret =3D=3D -EBUSY) { + /* + * We don't want to abort so we let the migration to continue. + * In a rare case, the machine check handler will run on the targe= t. + * Though this is not preferable, it is better than aborting + * the migration or killing the VM. + */ + warn_report("Received a fwnmi while migration was in progress"); + } + + spapr->mc_status =3D cpu->vcpu_id; spapr_mce_dispatch_elog(cpu, recovered); } =20 diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 3f162d82f5..4ce8e48d2a 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -50,6 +50,7 @@ #include "hw/ppc/fdt.h" #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" +#include "migration/blocker.h" =20 static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -453,6 +454,7 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, spapr->mc_status =3D -1; qemu_cond_signal(&spapr->mc_delivery_cond); rtas_st(rets, 0, RTAS_OUT_SUCCESS); + migrate_del_blocker(spapr->fwnmi_migration_blocker); } =20 static struct rtas_call { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index f6f82d88aa..a1fba95c82 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -218,6 +218,8 @@ struct SpaprMachineState { =20 unsigned gpu_numa_id; SpaprTpmProxy *tpm_proxy; + + Error *fwnmi_migration_blocker; }; =20 #define H_SUCCESS 0 --=20 2.17.2 From nobody Wed May 1 19:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1579254127; cv=none; d=zohomail.com; s=zohoarc; b=VhknaBlWg1jLdGU1irxuf5ISZ/oUy7X36oqbSGitPlXFB9ehWtAwO2mdXYh7/s1MJOFk5R6RDkjSWMcVCHikIx68lka5ZBdA/ANWY2+Ps6BmvIpGlRLwFMtIHuWAiAJ3pkPNdfslB5C8xOGjlcz6ddDRHpx772maZ/yQ6Mn4rJc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1579254127; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 17 Jan 2020 09:39:49 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00H9dm9750331676 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Jan 2020 09:39:48 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 62E7EAE055; Fri, 17 Jan 2020 09:39:48 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CD8C4AE056; Fri, 17 Jan 2020 09:39:46 +0000 (GMT) Received: from localhost.in.ibm.com (unknown [9.124.35.97]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 17 Jan 2020 09:39:46 +0000 (GMT) From: Ganesh Goudar To: aik@ozlabs.ru, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Subject: [PATCH v20 7/7] ppc: spapr: Activate the FWNMI functionality Date: Fri, 17 Jan 2020 15:08:55 +0530 X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200117093855.19074-1-ganeshgr@linux.ibm.com> References: <20200117093855.19074-1-ganeshgr@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 20011709-0016-0000-0000-000002DE3303 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011709-0017-0000-0000-00003340CE37 Message-Id: <20200117093855.19074-8-ganeshgr@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_02:2020-01-16, 2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 mlxscore=0 impostorscore=0 malwarescore=0 phishscore=0 adultscore=0 mlxlogscore=781 priorityscore=1501 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001170074 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, Ganesh Goudar , Aravinda Prasad , groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aravinda Prasad This patch sets the default value of SPAPR_CAP_FWNMI_MCE to SPAPR_CAP_ON for machine type 4.2. Signed-off-by: Aravinda Prasad Signed-off-by: Ganesh Goudar --- hw/ppc/spapr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c8bc2fa9f3..a81c18b6b6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4454,7 +4454,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; - smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_ON; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; @@ -4544,6 +4544,7 @@ static void spapr_machine_4_1_class_options(MachineCl= ass *mc) smc->smp_threads_vsmt =3D false; compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_OFF; } =20 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); --=20 2.17.2