From nobody Sun Feb 22 22:09:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1578022536; cv=none; d=zohomail.com; s=zohoarc; b=Cz5ofs5VxYfan0QWbtKA3wcusT+Lx7abqJlEMZREhzsGjuvultcmecQ+TzQonbXYSjvxPFff3z9N0QT2tFD/KH7wNXEDq0MDokscpur1GDmFccBJSzrWijhvuV2Ay0k5X/XjD0GQVb28685IeASpUllOWGR/FZcgQMuL0zts0J4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578022536; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bcxwg+BPU51zioNab4Be8f7/ET7mdgc1UaJbv39BFIU=; b=WYBATRExCABFVtN8npLZC/lZlEiV2lQJzORLCmPyuZmUJIF8H3zOB11puTV4phyOA5RKj/6IyItIyRaqIqpA+qUQmA6+NcvPwjzwmr0f4FYHVG/Ap/G0H9LQxXOgP+h6yT5xYeVpoKu33y/b+YpPnfdUtlBsZyjr5PF0syFXhP0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1578022535759476.2783665195377; Thu, 2 Jan 2020 19:35:35 -0800 (PST) Received: from localhost ([::1]:48286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inDkM-0006Mg-3u for importer@patchew.org; Thu, 02 Jan 2020 22:35:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43892) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inDj0-000519-Vx for qemu-devel@nongnu.org; Thu, 02 Jan 2020 22:34:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1inDiy-000378-QQ for qemu-devel@nongnu.org; Thu, 02 Jan 2020 22:34:10 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:50815) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1inDiy-0002xJ-7k for qemu-devel@nongnu.org; Thu, 02 Jan 2020 22:34:08 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GV9YvOJ_1578022440) by smtp.aliyun-inc.com(10.147.42.16); Fri, 03 Jan 2020 11:34:02 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.652223-0.0139949-0.333782; DS=||; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16370; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GV9YvOJ_1578022440; From: LIU Zhiwei To: alistair23@gmail.com, richard.henderson@linaro.org, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v3 4/4] RISC-V: add vector extension configure instruction Date: Fri, 3 Jan 2020 11:33:47 +0800 Message-Id: <20200103033347.20909-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200103033347.20909-1-zhiwei_liu@c-sky.com> References: <20200103033347.20909-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART =3D=3D 0 && VL =3D=3D VLMAX) will be placed within t= b_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 55 ++++++++++++++++++++----- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 52 +++++++++++++++++++++++ target/riscv/translate.c | 17 +++++++- target/riscv/vector_helper.c | 51 +++++++++++++++++++++++ 8 files changed, 172 insertions(+), 13 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index b1c79bc1d1..d577cef9e0 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,4 +1,4 @@ -obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o g= dbstub.o pmp.o +obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o v= ector_helper.o gdbstub.o pmp.o =20 DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c2370a0a57..3ff7b50bff 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -347,6 +347,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } } if (cpu->cfg.vext_spec) { + env->vext.vtype =3D ~((target_ulong)-1 >> 1); if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { vext_version =3D VEXT_VERSION_0_07_1; } else { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0b106583a..152a96f1fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -23,6 +23,7 @@ #include "qom/cpu.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#include "hw/registerfields.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -98,6 +99,20 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 4096 =20 +struct VTYPE { +#ifdef HOST_WORDS_BIGENDIAN + target_ulong vill:1; + target_ulong reserved:sizeof(target_ulong) * 8 - 7; + target_ulong sew:3; + target_ulong lmul:2; +#else + target_ulong lmul:2; + target_ulong sew:3; + target_ulong reserved:sizeof(target_ulong) * 8 - 7; + target_ulong vill:1; +#endif +}; + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ @@ -309,19 +324,44 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVStat= e *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_MSTATUS_FS MSTATUS_FS +typedef CPURISCVState CPUArchState; +typedef RISCVCPU ArchCPU; +#include "exec/cpu-all.h" + +FIELD(TB_FLAGS, MMU, 0, 2) +FIELD(TB_FLAGS, FS, 13, 2) +FIELD(TB_FLAGS, VL_EQ_VLMAX, 16, 1) +FIELD(TB_FLAGS, LMUL, 17, 2) +FIELD(TB_FLAGS, SEW, 19, 3) +FIELD(TB_FLAGS, VILL, 22, 1) =20 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *= pc, - target_ulong *cs_base, uint32_t *f= lags) + target_ulong *cs_base, uint32_t *p= flags) { + RISCVCPU *cpu =3D env_archcpu(env); + struct VTYPE *vtype =3D (struct VTYPE *)&env->vext.vtype; + uint32_t vlmax; + uint8_t vl_eq_vlmax; + uint32_t flags =3D 0; + *pc =3D env->pc; *cs_base =3D 0; + vlmax =3D (1 << vtype->lmul) * cpu->cfg.vlen / (8 * (1 << vtype->sew)); + vl_eq_vlmax =3D (env->vext.vstart =3D=3D 0) && (vlmax =3D=3D env->vext= .vl); + + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, vtype->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vtype->sew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, vtype->lmul); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + #ifdef CONFIG_USER_ONLY - *flags =3D TB_FLAGS_MSTATUS_FS; + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, MSTATUS_FS); #else - *flags =3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + flags =3D FIELD_DP32(flags, TB_FLAGS, MMU, cpu_mmu_index(env, 0)); + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, (env->mstatus & MSTATUS_FS)); #endif + *pflags =3D flags; + *cs_base =3D 0; } =20 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, @@ -362,9 +402,4 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 -typedef CPURISCVState CPUArchState; -typedef RISCVCPU ArchCPU; - -#include "exec/cpu-all.h" - #endif /* RISCV_CPU_H */ diff --git a/target/riscv/helper.h b/target/riscv/helper.h index debb22a480..000b5aa3d1 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -76,3 +76,5 @@ DEF_HELPER_2(mret, tl, env, tl) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif +/* Vector functions */ +DEF_HELPER_3(vector_vsetvli, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 77f794ed70..5dc009c3cd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -62,6 +62,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd =20 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -203,3 +204,7 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm + +# *** RV32V Extension *** +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm +vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c new file mode 100644 index 0000000000..5d80144502 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -0,0 +1,52 @@ +/* + * RISC-V translation routines for the RVV Standard Extension. + * + * Copyright (c) 2019 C-SKY Limited. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl * a) +{ + TCGv s1, s2, d; + d =3D tcg_temp_new(); + s1 =3D tcg_temp_new(); + s2 =3D tcg_temp_new(); + gen_get_gpr(s1, a->rs1); + gen_get_gpr(s2, a->rs2); + gen_helper_vector_vsetvli(d, cpu_env, s1, s2); + tcg_gen_st_tl(d, cpu_env, offsetof(CPURISCVState, vext.vl)); + exit_tb(ctx); + ctx->base.is_jmp =3D DISAS_NORETURN; + tcg_temp_free(s1); + tcg_temp_free(s2); + tcg_temp_free(d); + return true; +} + +static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli * a) +{ + TCGv s1, s2, d; + d =3D tcg_temp_new(); + s1 =3D tcg_temp_new(); + s2 =3D tcg_const_tl(a->zimm); + gen_get_gpr(s1, a->rs1); + gen_helper_vector_vsetvli(d, cpu_env, s1, s2); + tcg_gen_st_tl(d, cpu_env, offsetof(CPURISCVState, vext.vl)); + exit_tb(ctx); + ctx->base.is_jmp =3D DISAS_NORETURN; + tcg_temp_free(s1); + tcg_temp_free(s2); + tcg_temp_free(d); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8d6ab73258..beb283b735 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,6 +55,12 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + /* vector extension */ + bool vill; + uint8_t lmul; + uint8_t sew; + uint16_t vlen; + bool vl_eq_vlmax; } DisasContext; =20 #ifdef TARGET_RISCV64 @@ -706,6 +712,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvd.inc.c" +#include "insn_trans/trans_rvv.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 /* @@ -754,14 +761,20 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cs->env_ptr; RISCVCPU *cpu =3D RISCV_CPU(cs); + uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->pc_succ_insn =3D ctx->base.pc_first; - ctx->mem_idx =3D ctx->base.tb->flags & TB_FLAGS_MMU_MASK; - ctx->mstatus_fs =3D ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; + ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MMU); + ctx->mstatus_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, FS); ctx->priv_ver =3D env->priv_ver; ctx->misa =3D env->misa; ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; + ctx->vlen =3D cpu->cfg.vlen; + ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); + ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); + ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c new file mode 100644 index 0000000000..4e394207ce --- /dev/null +++ b/target/riscv/vector_helper.c @@ -0,0 +1,51 @@ +/* + * RISC-V Vectore Extension Helpers for QEMU. + * + * Copyright (c) 2019 C-SKY Limited. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include + +#define VECTOR_HELPER(name) HELPER(glue(vector_, name)) + +target_ulong VECTOR_HELPER(vsetvli)(CPURISCVState *env, target_ulong s1, + target_ulong s2) +{ + int vlmax, vl; + RISCVCPU *cpu =3D env_archcpu(env); + struct VTYPE *vtype =3D (struct VTYPE *)&s2; + + if (vtype->sew > cpu->cfg.elen) { /* only set vill bit. */ + env->vext.vtype =3D ~((target_ulong)-1 >> 1); + return 0; + } + + vlmax =3D (1 << vtype->lmul) * cpu->cfg.vlen / (8 * (1 << vtype->sew)); + if (s1 =3D=3D 0) { + vl =3D vlmax; + } else if (s1 <=3D vlmax) { + vl =3D s1; + } else { + vl =3D vlmax; + } + env->vext.vl =3D vl; + env->vext.vtype =3D s2; + env->vext.vstart =3D 0; + return vl; +} --=20 2.23.0