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[194.223.58.9]) by smtp.gmail.com with ESMTPSA id c18sm21077186pfr.40.2019.12.28.15.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Dec 2019 15:12:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=urRb0uR9O/6+SJM1ppmaD8oGu/FOyRk842uyqGR7Ev0=; b=f2qn5DIYdgooPOi9Qkb1YAco3Mc5/CxypjNZiaSOaQEIFUXSlyLFpw5nhtZw1TkCFy i8bPo01usKnObeXsIKh3jHx39IC0y1351l2JYipgzl16gbG5ySyJ+3UJ52k6X17DUW8X W2OILLkRdFkb/XknAkWUAKEb+mAj1od8VOKlm84uJkKgJYSDOYOft6O/RMklDKYabk6x Yy8sPo+Po1aLJJVOvc1ro9iIJrgWKyruFvkda7SX0XoRy05/xhb9S32YHuaGJ5YHB6FD kHdOlEBMwyuxGXaZoeyLsPOkNlYFjS0Sm0cxCZq4Ijhpor2D5kczGJsp9vp3d3WdX3LM vIsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=urRb0uR9O/6+SJM1ppmaD8oGu/FOyRk842uyqGR7Ev0=; b=ZW8Ctnw3+ERsOfL5k38DGaOsqV3gYZPWc8E3hOk/+evucdoEUHto2HzgpukOCtGafA ZZ+BrcGGFrR1k0R6FCWil/dT9iDXD/r3yvDCaP/Jo6LyJaMPfGI9LhP4/gvoXtkxVcyi jgpPE8hqGw5+IJra8zZOmnl7eCrXgmzP1YzRCuyTbN0fMPgAnkyci5IZzcjGXzb5AK3n e6SZxhlJ+dbtgYPbmEITZgDrgmwaaZD//7zshIdg5Tk0zh4dpPh4ZqQluO40HL64XYgj BBsNWzSeOdukG14SXLVjilieGjQyTkSfOPUvJnvYyEH7dDqe/O8UHxaCk1soHD3y8yJL i5PQ== X-Gm-Message-State: APjAAAX663k4IQW8XcbOFBOUJXoZbnkqQt2sjc+X4gQUI4JmZh5PJfzY Fk0QO+OHvNjdBpVDyYLyTpWt/v4txCk= X-Google-Smtp-Source: APXvYqzDLB0Cdc6haliHp39GwLXxJ8NSLhx5Hz5myqZtm7u0mMFvaoNnOlp7708Gc5dUCOPGnGqWLg== X-Received: by 2002:a17:90a:f314:: with SMTP id ca20mr34091890pjb.112.1577574765446; Sat, 28 Dec 2019 15:12:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/29] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX Date: Sun, 29 Dec 2019 10:11:20 +1100 Message-Id: <20191228231124.18307-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191228231124.18307-1-richard.henderson@linaro.org> References: <20191228231124.18307-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aleksandar Markovic , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The separate suffixed functions were used to construct some do_##insn function switched on mmu_idx. The interface is exactly identical to the *_mmuidx_ra functions. Replace them directly and remove the constructions. Cc: Aurelien Jarno Cc: Aleksandar Rikalo Reviewed-by: Aleksandar Markovic Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/mips/cpu.h | 4 - target/mips/op_helper.c | 182 +++++++++++++--------------------------- 2 files changed, 60 insertions(+), 126 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index ca00f41daf..c218ccc4a8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1147,10 +1147,6 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPS= State *env); * MMU modes definitions. We carefully match the indices with our * hflags layout. */ -#define MMU_MODE0_SUFFIX _kernel -#define MMU_MODE1_SUFFIX _super -#define MMU_MODE2_SUFFIX _user -#define MMU_MODE3_SUFFIX _error #define MMU_USER_IDX 2 =20 static inline int hflags_mmu_index(uint32_t hflags) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 18fcee4a78..79d44da6fa 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -52,69 +52,6 @@ static void raise_exception(CPUMIPSState *env, uint32_t = exception) do_raise_exception(env, exception, 0); } =20 -#if defined(CONFIG_USER_ONLY) -#define HELPER_LD(name, insn, type) \ -static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ - int mem_idx, uintptr_t retaddr) \ -{ \ - return (type) cpu_##insn##_data_ra(env, addr, retaddr); \ -} -#else -#define HELPER_LD(name, insn, type) \ -static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ - int mem_idx, uintptr_t retaddr) \ -{ \ - switch (mem_idx) { \ - case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \ - case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \ - default: \ - case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \ - case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \ - } \ -} -#endif -HELPER_LD(lw, ldl, int32_t) -#if defined(TARGET_MIPS64) -HELPER_LD(ld, ldq, int64_t) -#endif -#undef HELPER_LD - -#if defined(CONFIG_USER_ONLY) -#define HELPER_ST(name, insn, type) \ -static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ - type val, int mem_idx, uintptr_t retaddr) \ -{ \ - cpu_##insn##_data_ra(env, addr, val, retaddr); \ -} -#else -#define HELPER_ST(name, insn, type) \ -static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ - type val, int mem_idx, uintptr_t retaddr) \ -{ \ - switch (mem_idx) { \ - case 0: \ - cpu_##insn##_kernel_ra(env, addr, val, retaddr); \ - break; \ - case 1: \ - cpu_##insn##_super_ra(env, addr, val, retaddr); \ - break; \ - default: \ - case 2: \ - cpu_##insn##_user_ra(env, addr, val, retaddr); \ - break; \ - case 3: \ - cpu_##insn##_error_ra(env, addr, val, retaddr); \ - break; \ - } \ -} -#endif -HELPER_ST(sb, stb, uint8_t) -HELPER_ST(sw, stl, uint32_t) -#if defined(TARGET_MIPS64) -HELPER_ST(sd, stq, uint64_t) -#endif -#undef HELPER_ST - /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { @@ -379,12 +316,12 @@ target_ulong helper_##name(CPUMIPSState *env, target_= ulong arg, int mem_idx) \ } = \ env->CP0_LLAddr =3D do_translate_address(env, arg, 0, GETPC()); = \ env->lladdr =3D arg; = \ - env->llval =3D do_##insn(env, arg, mem_idx, GETPC()); = \ + env->llval =3D cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); = \ return env->llval; = \ } -HELPER_LD_ATOMIC(ll, lw, 0x3) +HELPER_LD_ATOMIC(ll, ldl, 0x3) #ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ld, 0x7) +HELPER_LD_ATOMIC(lld, ldq, 0x7) #endif #undef HELPER_LD_ATOMIC #endif @@ -400,42 +337,42 @@ HELPER_LD_ATOMIC(lld, ld, 0x7) void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); =20 if (GET_LMASK(arg2) <=3D 2) { - do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); } =20 if (GET_LMASK(arg2) <=3D 1) { - do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); } =20 if (GET_LMASK(arg2) =3D=3D 0) { - do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + mem_idx, GETPC()); } } =20 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); =20 if (GET_LMASK(arg2) >=3D 1) { - do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); } =20 if (GET_LMASK(arg2) >=3D 2) { - do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); } =20 if (GET_LMASK(arg2) =3D=3D 3) { - do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); } } =20 @@ -453,82 +390,82 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1,= target_ulong arg2, void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); =20 if (GET_LMASK64(arg2) <=3D 6) { - do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) <=3D 5) { - do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) <=3D 4) { - do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) <=3D 3) { - do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) <=3D 2) { - do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) <=3D 1) { - do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) <=3D 0) { - do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + mem_idx, GETPC()); } } =20 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); =20 if (GET_LMASK64(arg2) >=3D 1) { - do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) >=3D 2) { - do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) >=3D 3) { - do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) >=3D 4) { - do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) >=3D 5) { - do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) >=3D 6) { - do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); } =20 if (GET_LMASK64(arg2) =3D=3D 7) { - do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx, - GETPC()); + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + mem_idx, GETPC()); } } #endif /* TARGET_MIPS64 */ @@ -546,14 +483,14 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, =20 for (i =3D 0; i < base_reglist; i++) { env->active_tc.gpr[multiple_regs[i]] =3D - (target_long)do_lw(env, addr, mem_idx, GETPC()); + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); addr +=3D 4; } } =20 if (do_r31) { - env->active_tc.gpr[31] =3D (target_long)do_lw(env, addr, mem_idx, - GETPC()); + env->active_tc.gpr[31] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); } } =20 @@ -567,14 +504,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { - do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx, - GETPC()); + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); addr +=3D 4; } } =20 if (do_r31) { - do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); } } =20 @@ -589,14 +526,15 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D do_ld(env, addr, mem_= idx, - GETPC()); + env->active_tc.gpr[multiple_regs[i]] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); addr +=3D 8; } } =20 if (do_r31) { - env->active_tc.gpr[31] =3D do_ld(env, addr, mem_idx, GETPC()); + env->active_tc.gpr[31] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); } } =20 @@ -610,14 +548,14 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { - do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx, - GETPC()); + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); addr +=3D 8; } } =20 if (do_r31) { - do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); } } #endif --=20 2.20.1