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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t5sm9741814wrr.35.2019.12.20.06.26.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 06:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2KUP15f7qeOWW1oxuca3zmV/3aT0vejsyXqh6o12C1s=; b=nwisGP7sTkpQRSQOd5ibYJljXAKb3ExWypM5ZSRaidLBclrPXBIRCY/pZi0gBnBxgq h8YQjAy0GbDY/v8NVfm7KVt+O1MxmJ9A9lTcaDYYLMiEgEHdd0/QfObjbTqu/VnqX7YG RPam1vL1cHlDp1fuQBRLR1a/7rmHWFcwHu356IU9WGke5XAGeZwoCP3Kx66B8rXikh4z f1pJSTOoS7O+eQn53OMr+sqBUlFi049b2cPsflzt/4ipcyKP3p749cDhR81kjvQ/F7ch jqVB9qgyQv9KMYpUAy0ruJ/iYFPLA2zMZRvf/wDxTTy95BOD8EeDkQrUfNN2qlctMkcB 3I7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2KUP15f7qeOWW1oxuca3zmV/3aT0vejsyXqh6o12C1s=; b=Wau0W30bUHabz9X3jJnk8LCEz9ZVl8Cu/vuD657357h0pQX9KaMBqTb5ep04xhO/9D liblpTgs5utNR72xKGMuK3chRx6XgQuDoVCrtm+jovucdVZodfqIaVbQD3IZwvI71RFD xuMMIN514MGFiz+fESKRk/7W/OyuMMiAVmYsyiEoF8Rulfr3zfDlX7gBtGGZEnh2xLSw 47+9zldMJQEO3PoNE6mQakf5zk8ezzusYhqNNWBWN7aWJtNL2Ng5Y0D/u9PnhvZ1UzYe mgWACjXL4UbpCJq+LQXvO0MPx17pGiQk5aRr3XJFYbSL0YixQ+gVeUHgmOI3/6ZPz/l2 lP4A== X-Gm-Message-State: APjAAAUcIbmJGc2GnwTPY9+J6/TAWwC2Tl0tdvcq/xN8cMKJRXZiC3/P St41j+fsZNjt0MOC8EqQ9BLaZh9gTMcW2A== X-Google-Smtp-Source: APXvYqyNjgZ64L/MbX+DQ6HqvYld7yo8L2xt/Y3+Uo6vInIDksE0vl7J3M30kB7pbOesLp9Wy7Xx+Q== X-Received: by 2002:adf:ea8a:: with SMTP id s10mr15258900wrm.278.1576852018159; Fri, 20 Dec 2019 06:26:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/12] hw/arm/smmuv3: Align stream table base address to table size Date: Fri, 20 Dec 2019 14:26:40 +0000 Message-Id: <20191220142644.31076-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220142644.31076-1-peter.maydell@linaro.org> References: <20191220142644.31076-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Simon Veith Per the specification, and as observed in hardware, the SMMUv3 aligns the SMMU_STRTAB_BASE address to the size of the table by masking out the respective least significant bits in the ADDR field. Apply this masking logic to our smmu_find_ste() lookup function per the specification. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Acked-by: Eric Auger Tested-by: Eric Auger Message-id: 1576509312-13083-5-git-send-email-sveith@amazon.de Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 727558bcfa5..31ac3ca32eb 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -376,8 +376,9 @@ bad_ste: static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { - dma_addr_t addr; + dma_addr_t addr, strtab_base; uint32_t log2size; + int strtab_size_shift; int ret; =20 trace_smmuv3_find_ste(sid, s->features, s->sid_split); @@ -391,10 +392,16 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid= , STE *ste, } if (s->features & SMMU_FEATURE_2LVL_STE) { int l1_ste_offset, l2_ste_offset, max_l2_ste, span; - dma_addr_t strtab_base, l1ptr, l2ptr; + dma_addr_t l1ptr, l2ptr; STEDesc l1std; =20 - strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK; + /* + * Align strtab base address to table size. For this purpose, assu= me it + * is not bounded by SMMU_IDR1_SIDSIZE. + */ + strtab_size_shift =3D MAX(5, (int)log2size - s->sid_split - 1 + 3); + strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK & + ~MAKE_64BIT_MASK(0, strtab_size_shift); l1_ste_offset =3D sid >> s->sid_split; l2_ste_offset =3D sid & ((1 << s->sid_split) - 1); l1ptr =3D (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)= ); @@ -433,7 +440,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid,= STE *ste, } addr =3D l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr =3D (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*st= e); + strtab_size_shift =3D log2size + 5; + strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK & + ~MAKE_64BIT_MASK(0, strtab_size_shift); + addr =3D strtab_base + sid * sizeof(*ste); } =20 if (smmu_get_ste(s, addr, ste, event)) { --=20 2.20.1