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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t5sm9741814wrr.35.2019.12.20.06.26.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 06:26:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Lo7PUw1ERbHRyrus/NtQMRXglB5e3q+im5wQRdibHpo=; b=jgGbRcOUMiW7l8/UU/fw/TiMf/wyeqYA6yPJmKQLMpmauK3e0oWWa4ppOFgDKh7bZ5 V3rzZbYmD9474kGA2YQzRebe9pEEiWTiXRrSYwKdn8y7Z9kzB+b7FgdIHHXzqWeE41Py bb7oGXddS6bp/UOMXxpl1vhmM0mBzKXuesfZDNVXIpkakQ3jfxYxdOQRPGUzI4+gyIGA iqzim2Q/iT4zj1YAyAgE+CNkWOgPNiV7miKRTShDbN1j7QdZ3E10lkH7cwVSzhfQOsVv bYi9WYyQ4d5ZIjjxY54D9HoQRWcbYDRLxsGAsYY8SPZ9PLI8IH14TKxSBZUg7eEPGqCj 9jfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lo7PUw1ERbHRyrus/NtQMRXglB5e3q+im5wQRdibHpo=; b=evuFTFVsAE8kYRLkvdz4zUagByVUWP6Ug8mC6vrMPf2iACUymUX1qtWaqTMgPbvUCu jUpA3wj/0hP8mUFNuRtSyJ8a2UMKbkugfNaaRwST0/elCX/lqACbFTCaH9UBCJExWUSS lC5aBeSqEx2ndTJttPdSqXqAydsrX2BtfGxcs+/ffZBu+ATziUuB+y1QyEYJUJi1Nq/5 Sk18S7E6GjpZgfavOBQm7iSW5d/C8Ene1Mvq5jMMangJcIpQIHuaez/UEUmth9ZG9Hi2 BDFotra7exb2la6+0kmuhRL4q5Ser1RWMMwwrqanDrFrhULNTRfJTGW49kzKDtCZwFQE DvXQ== X-Gm-Message-State: APjAAAU//HeBp43/5Vf/Lo/cfoDLdoG4WVuP9hdogK4pwJtAjgBb/pBG /TXlD0YHsqUcD7Ra6UoWAUXc1IUlo1YDtg== X-Google-Smtp-Source: APXvYqy3PVMRLCOdt8JGn+/z7DMPTiFGVV+UzXPIL3JmX10hrxH7l9ly0XRoaUmEMq1B2P9SAlOSrA== X-Received: by 2002:a05:600c:218b:: with SMTP id e11mr15737180wme.121.1576852019796; Fri, 20 Dec 2019 06:26:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/12] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro Date: Fri, 20 Dec 2019 14:26:41 +0000 Message-Id: <20191220142644.31076-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220142644.31076-1-peter.maydell@linaro.org> References: <20191220142644.31076-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Simon Veith The bit offsets in the EVT_SET_ADDR2 macro do not match those specified in the ARM SMMUv3 Architecture Specification. In all events that use this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually occupies the 32-bit words 6 and 7 in the event record contiguously, with the upper and lower unused bits clear due to alignment or maximum supported address bits. How many bits are clear depends on the individual event type. Update the macro to write to the correct words in the event record so that guest drivers can obtain accurate address information on events. ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16. Signed-off-by: Simon Veith Acked-by: Eric Auger Tested-by: Eric Auger Message-id: 1576509312-13083-6-git-send-email-sveith@amazon.de Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 042b4358084..4112394129e 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -461,8 +461,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - (x)->word[7] =3D deposit32((x)->word[7], 3, 29, addr >> 16); = \ - (x)->word[7] =3D deposit32((x)->word[7], 0, 16, addr & 0xffff)= ;\ + (x)->word[7] =3D (uint32_t)(addr >> 32); \ + (x)->word[6] =3D (uint32_t)(addr & 0xffffffff); \ } while (0) =20 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); --=20 2.20.1