From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576781606; cv=none; d=zohomail.com; s=zohoarc; b=IWlKaunE48kJ1Ktao7YrEHApkR2+BXD81VfLvIEZ8K4tBEdh8SvZNuf6MmDWb/F5LS/4HROI/FZO3S7B5fQkNpLMT+y8bY7EPAD+HmPVQ+iTKp3xGhCTKEYivmMuksV0GEhpmMVQ99a89qAaQt6wYgFdW6c/pCe5RMMOp7zETyw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576781606; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=lZ9qIjWIY5ZTVOYswTpL01Wbf68dBexQhuavHUiZt3acTvLiFEbB6/RtKkhrHCATEU7F88fTBB1/YG2kIhBWXcqof2PndQw48rtUnE2SulmTLNi3c0ZebCnlQyvc3sxQ6nM2EbYypIvqPgIRLGRY6hX0ZPCGLzxNOTkVLBK9e40= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576781606533354.47858074338706; Thu, 19 Dec 2019 10:53:26 -0800 (PST) Received: from localhost ([::1]:46636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0vM-0008VF-I0 for importer@patchew.org; Thu, 19 Dec 2019 13:53:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39067) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0ta-0006zd-Mx for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tZ-0007PI-IQ for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:34 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:45402) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tZ-0007F6-9M; Thu, 19 Dec 2019 13:51:33 -0500 Received: by mail-wr1-x433.google.com with SMTP id j42so7019940wrj.12; Thu, 19 Dec 2019 10:51:32 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=rzuwWUvW7fxrR8Q8rS5X13OM54/eLmN+zTAKxDRco/Oq+BgWmNrUIl1hDDIWXer+Fy L8YnYjYdzu/VREz33h1DmdVp1ZV1AaGR3fO9NBba+UOJNV1pQdpBbqAuC6dumVMl6qZP UlGW6/h5H1PWsw/K4YpyEoRngGgWynIlAal3ptwF+FFioIhDWpw+Nq8o5FPwZrYlr7ar RnhS792N/crlExsgvEPRX4/UKZi+f9ovgG6Jb2hguh3dgpmivk+BHr6KLFHkKHrWyiuZ 1Srq0elLFhgW9+pZ9HOj/JnX1wLx8CeNIT5NUZhw64eSIcTOLtRs4lFRTlIbMI0qA6pc JTTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=f8DydsLICYizaAkKFyJFFmJB+Lu4/GBxutH+i2NeRTYCPzGUiatAsi1WtJoFdaSD5W XiiofyIQlmJY3gbourO/156bVSCQlSHWgf1Bh22xgurwjyK0fTWGsej0jcrJWnWRQWZn uyhvtRNEf2iuTXKGMgL6zvTEc8iRuLnegl/1vz0gSgBA3zWdutVo3SZudvvEkq6JPEtS 3L+gI+JuHGI7XkK8PoiDRQ9Z0fqkiUhKYcsh/sJ8fgXd0/4+SyHcmiA/ilJmFOFnFWf8 tnf2KkYiC43kx5jziqrsCbeVd/QXEvhjPOCe2XsMCDg790BTgKE9iMWO/pAzZUwP8q8k AYUQ== X-Gm-Message-State: APjAAAVcnU76KWeiUNlDt/eI6/YzskyYRDTXQZyw5Zxa8GD8mFNLYScB drQWW4G6qaQ0mfN4OpTTZzjB850g X-Google-Smtp-Source: APXvYqznBI30MLzRunuvTH94RbArJIo8XyU1MvwcT9Wtl4G1B96s4+YMJ9L6JV0fFjxe8mEQ6WjUCw== X-Received: by 2002:adf:c746:: with SMTP id b6mr10451458wrh.298.1576781490780; Thu, 19 Dec 2019 10:51:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 01/13] hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition Date: Thu, 19 Dec 2019 19:51:15 +0100 Message-Id: <20191219185127.24388-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We have a definition for this magic value '6', use it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index 871c95b512..6aceda81ee 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -32,7 +32,7 @@ =20 #define AW_A10_PIT_TIMER_BASE 0x10 #define AW_A10_PIT_TIMER_BASE_END \ - (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT) + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) =20 #define AW_A10_PIT_DEFAULT_CLOCK 0x4 =20 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index aae880f5b3..117e5c7bf8 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -225,7 +225,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status =3D 0; a10_pit_update_irq(s); =20 - for (i =3D 0; i < 6; i++) { + for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { s->control[i] =3D AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] =3D 0; s->count[i] =3D 0; --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576781777; cv=none; d=zohomail.com; s=zohoarc; b=HBeM2Oc5QFyNrqjkUmho90EyZer0GcpLcZjmPD5QHfpJGdzUzh5PZDAD0Fh1sk863EyK4zOSo66ppHInLJ1UZpr0CZLPtY6CFrtb8bMjAf8GGXu027f1ypIJz2p+2D3UyvYBkrHzKTtvWspiCZUWpx+ZcUQv/nJWGqFXFJESzZQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576781777; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fXYp8lEUsOTs8WcsQwwp+b/Rx/W+yTQjD5EmKm5HZkQ=; b=l4V2TLuBeKfHSpX//TMNojVOmVGes3kQYdnE06+xJt/pqXlmaMbGZEtGDvOaqeX/PGfGevwrazACTvO6n1c8dJGi9QYmQOHf0FdXasZ2cVaLKvC9tt+Hz8DRnro0N1OFniLopatuZh33CyGZrMLPYFkv63Wqcx+6g/+T7CYlSMw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157678177786467.55260724115692; Thu, 19 Dec 2019 10:56:17 -0800 (PST) Received: from localhost ([::1]:46688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0y8-0004KJ-Dt for importer@patchew.org; Thu, 19 Dec 2019 13:56:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0td-00070O-BU for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tc-0007cs-1E for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:55406) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0ta-0007JT-OD; Thu, 19 Dec 2019 13:51:35 -0500 Received: by mail-wm1-x341.google.com with SMTP id q9so6525516wmj.5; Thu, 19 Dec 2019 10:51:34 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fXYp8lEUsOTs8WcsQwwp+b/Rx/W+yTQjD5EmKm5HZkQ=; b=CiqPXITD7Q6zjfjsVt8EFYgzvZiiPThER8xHaLyNLRpa42ZGuYzQ0RWvJzRYg/v564 wbF/PUl806Sb8yrqrkQPrnyYdmh7JEelLgNbMH/TR+EtdcL5E96Mcfh+h9OrIvrjcv8K IAaVUWzFVnImTSfDERTduPXzw0OZCA6y7tNs6+6A7DHnN8/d2FYiOAg6zSC553C7IVeG bXFIhQFAqQ747RPP93c0P+LhUOD3snmkEO81gDtzbDSmowFruBhwzqHhkj1DWMfrQyBU fn+OcjRJz1OKZQfxVnJRVMvtIolHAMjpq+kbdHsrXESFRDaI1o+VoY4TNy0QLXg2UjDe Um9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fXYp8lEUsOTs8WcsQwwp+b/Rx/W+yTQjD5EmKm5HZkQ=; b=kuIDvQ5S7BkonxO0HFl/5gaztqoBEi+BVVM8p2cC2mp8+bBYStKx3S3Q9A2xKa5+Y1 MDhHPSE1GUR+RRcIBJz4wqGLYxhOJJ2Kjhx7bYGSZx3ynuaTgVjOcJn4N71GqkqV/l/f K9XTpSPJ2/+OU8nJZ/n9KJRVgmErdx9rZopklCtmg+eW6C9F2oveSRKl6q7Ym2V03PI3 VwK//mm/3WBa1CIXnx1EZ+tSZfr0GG397f6WQ7ce/84OMXjfCX1WiQs0AkB7lGHZQUKT orYIwjWDmBX6XvyLyMI3kXky6GIQfKK6E3wW3XGv/tA15Mt8adDMkVQNmT5LXSKnGqWe TQXA== X-Gm-Message-State: APjAAAXUQzijNjMiE2FABUbqYWsUeKqUIPO2NgcnKiN9DpiTl/jpr5Ix Y+mKP/Bm5/aQ+1c+ej3grON0COsW X-Google-Smtp-Source: APXvYqyBP+csHZWV31aWT9PUtc9oSAzojq4IR+0YaAAAV132U+rS7oQtg+AaY6Qgehx1lhQ+kKItYg== X-Received: by 2002:a1c:4d03:: with SMTP id o3mr11881092wmh.164.1576781491873; Thu, 19 Dec 2019 10:51:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 02/13] hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition Date: Thu, 19 Dec 2019 19:51:16 +0100 Message-Id: <20191219185127.24388-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This controller is able to use up to 6 timers. Later we will reuse part of it to model other similar controllers but with less timers. To simplify the VMSTATE, we'll keep a max of 6 timers. Add a definition for that value. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank --- include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------ hw/timer/allwinner-a10-pit.c | 8 ++++---- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index 6aceda81ee..54c40c7db6 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -7,6 +7,8 @@ #define TYPE_AW_A10_PIT "allwinner-A10-timer" #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) =20 +#define AW_PIT_TIMER_MAX 6 + #define AW_A10_PIT_TIMER_NR 6 #define AW_A10_PIT_TIMER_IRQ 0x1 #define AW_A10_PIT_WDOG_IRQ 0x100 @@ -47,17 +49,17 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_A10_PIT_TIMER_NR]; - ptimer_state * timer[AW_A10_PIT_TIMER_NR]; - AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; + qemu_irq irq[AW_PIT_TIMER_MAX]; + ptimer_state * timer[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; =20 uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_A10_PIT_TIMER_NR]; - uint32_t interval[AW_A10_PIT_TIMER_NR]; - uint32_t count[AW_A10_PIT_TIMER_NR]; + uint32_t control[AW_PIT_TIMER_MAX]; + uint32_t interval[AW_PIT_TIMER_MAX]; + uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 117e5c7bf8..b31a0bcd43 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VamSeBNb0W35YTaE5KKNIilAYQcTaYH0JIGT88S7LVU=; b=lGlEoLZ4HCVjqxq5Zd6ssPum8e5x3eIbiQJpheWrOxKN3wrx+79F/RLx/vlxq+4i7W LpOCvnyKz6ylR8adNjWfnacEyamkPFYJv87LZbZH1mtuIfQ6/qF6hZgUZHZqdxymdxhB uBrVjYLtfnTPlTg09rViCGByK7IlCKgql+jqlMiKO9hPtKry/mJ4KHe1ca2wiH8tjyZi rovV5W1qLoXynRm9FveDA38efOUnPnJ9dKnvQDnkksSzerFb2Ek6QKmijmdBalS0x0R9 9GzPMSVLz0kLhshbDTOeTbggNB2T75Z+pnO3IQbdvmdbumKrSCAOnzF7gfkvCrC9zsZX 3x+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VamSeBNb0W35YTaE5KKNIilAYQcTaYH0JIGT88S7LVU=; b=jbYRrjmLStT2+Rs4M9x9byoNx4hf8LsLriyG2wvjvAOhITDWs8BZVCVPUQB9m+FreT AUGo7OuFQKlZItpTZObApyhY/4qaJ/6VsYM2qYJJWqNMYqKO0TTA3vg0rTRIXslFRVEN lr3s62HvNLbJciOYP9hFUCc3TLyBKNTKpiM9U+1hfhaFokuAUubVEgBkjRIcBCfwMaIA qHSLPhCU0ZDwFRRJHck6Rr7GnBPw2wBMmkXnYe6TV1Q+395zalqdfUD2w53rdSVUfsKU JhxOHRx4zpewnXsCU1UlD1fle4vaSuPQgBhbGsUSrFJgFhUgtdaOu45b8hgNIgTXq515 S52Q== X-Gm-Message-State: APjAAAUV5SCG7VvdKACPH90pL+mowS4rXmV6+mHFcxWtfLDPaCh8jezF 5q49i8DlDuA25SCHOJEze4pF16d9 X-Google-Smtp-Source: APXvYqwKapHrfvD9zEOM0bF3NslhKK+w/LqCR67Y4N46elVy09iw3Y9Tf8OT2pQqLTSwycC32rZ/yg== X-Received: by 2002:a1c:cc06:: with SMTP id h6mr11140075wmb.118.1576781493163; Thu, 19 Dec 2019 10:51:33 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 03/13] hw/timer/allwinner: Remove unused definitions Date: Thu, 19 Dec 2019 19:51:17 +0100 Message-Id: <20191219185127.24388-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Keeping unused definition is rather confusing when reviewing. Remove them. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Niek Linnenbank --- include/hw/timer/allwinner-a10-pit.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index 54c40c7db6..e4a644add9 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -10,8 +10,6 @@ #define AW_PIT_TIMER_MAX 6 =20 #define AW_A10_PIT_TIMER_NR 6 -#define AW_A10_PIT_TIMER_IRQ 0x1 -#define AW_A10_PIT_WDOG_IRQ 0x100 =20 #define AW_A10_PIT_TIMER_IRQ_EN 0 #define AW_A10_PIT_TIMER_IRQ_ST 0x4 --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576781950; cv=none; d=zohomail.com; s=zohoarc; b=Z6p2rY1y67YTj5cjfDu2GdjKTdRZe+uYGEK+U5/Tw8gakEOgrSl+lc/A8Dh2IApfsebvQmvUH3Z8NInZT4i014gpWEb6vjo72Rx/vAh7ghyU22xTsJqF6VpWAjNhJzHaijphz5oG4NGmLJtUxf8p4abMUK1lKzjC1pQe7M53JIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576781950; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=NxKwcXYtp86/Z6l6ugCaznuJ5EDflWOrvDErZxkM55RJiVKwDDL/M0ZGGKQI/mok9rj8yYjOjwWb2w8WXMVetCnnVBkd0GeG+BmFG5XYvh18n0BT5LaEsQjyu2/sWF0MPrX078qBnH7muUMOlc3IoxotAtK2M1r1oIDPeGLxKQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576781950861958.9482497500121; Thu, 19 Dec 2019 10:59:10 -0800 (PST) Received: from localhost ([::1]:46726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii10u-0007tG-IR for importer@patchew.org; Thu, 19 Dec 2019 13:59:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39372) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0td-00070L-BC for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tc-0007cm-0Q for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53867) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tb-0007Xp-PD; Thu, 19 Dec 2019 13:51:35 -0500 Received: by mail-wm1-x343.google.com with SMTP id m24so6507350wmc.3; Thu, 19 Dec 2019 10:51:35 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=DOOoXp7wOhfRVuo831S05oCEi09rbGM+mhvGwoAW9kVI0AW+Oi4238dlMdG1HOQLPi fv1sR8UjxVUOg9aff+Rn+lxEEBAqc4IWv8QwbdkXnkjj1xZMT8iYSKrthF2l7zzOTr+f kSuwqJcEKaudzWgZISsd9EjkoaD+uKrDdGo54li47kwOPP/+gvfVHoNifBXg9VmFaeUm wIqWtyMYSnb/S/bYWWX3fNHNxI1dnDqTD5KQhO61QRvJOZmWmqYvUwrVYoBqSmnmQ/tw Ltilcsgh3Db1J+pjsZg4GO1nShWstMrzDDMz/AbdPwCOLkQgcINIA0f1COTK23QyDxzg mwow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=g6rH1vb0qUz2V/LctLMY0bRjoukLHEKNrHaJ5/wLhWJ8MuOxvwZ+jhR2yDn3FBFFf9 jZgEDXd69zznrvo4Z8Flrx0xTOhh/dftH8xmWMes3uVprBFqi3AWIz/dMOqpPaqgnax3 +zo4yTfyv9CjtrPS+4ZHBk06kcdo8UPK58ugH2GaEObtn6SaupRLMHthjVKm/h0iS4T7 Eqv2a+6L5J1zM1fjK/bl+kUhWGl2QszMZkr6CQqnQiCS6jU+tzUuX+rm+Tv15uDOhruy dORsHThzVzmBkeA1FjVAV1pgJH5Urbfjat7HYUWGJtnABkXff61myXZj8TsWBDa3wjZr kdHw== X-Gm-Message-State: APjAAAXXO31ZbwhRw2O7PQ2k958YCFObxARqlVSTJdPEnGkvH/cKntAh 22H4gY1KGRjy466RmVvvKAWc3pSm X-Google-Smtp-Source: APXvYqx4/zuBzYIXCe0BcvOfXwN1MN94M8leEwqrgzY3pRbmv0q7FlOQyPpkYLKO5pfpunluWXKUUA== X-Received: by 2002:a1c:4b09:: with SMTP id y9mr12136089wma.103.1576781494368; Thu, 19 Dec 2019 10:51:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 04/13] hw/timer/allwinner: Move definitions from header to source Date: Thu, 19 Dec 2019 19:51:18 +0100 Message-Id: <20191219185127.24388-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) These definitions are only used in the implementation, thus don't need to be exported. Move them in the source file. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/allwinner-a10-pit.h | 28 -------------------------- hw/timer/allwinner-a10-pit.c | 30 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 28 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index e4a644add9..c28ee5ca47 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -5,37 +5,9 @@ #include "hw/sysbus.h" =20 #define TYPE_AW_A10_PIT "allwinner-A10-timer" -#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) =20 #define AW_PIT_TIMER_MAX 6 =20 -#define AW_A10_PIT_TIMER_NR 6 - -#define AW_A10_PIT_TIMER_IRQ_EN 0 -#define AW_A10_PIT_TIMER_IRQ_ST 0x4 - -#define AW_A10_PIT_TIMER_CONTROL 0x0 -#define AW_A10_PIT_TIMER_EN 0x1 -#define AW_A10_PIT_TIMER_RELOAD 0x2 -#define AW_A10_PIT_TIMER_MODE 0x80 - -#define AW_A10_PIT_TIMER_INTERVAL 0x4 -#define AW_A10_PIT_TIMER_COUNT 0x8 -#define AW_A10_PIT_WDOG_CONTROL 0x90 -#define AW_A10_PIT_WDOG_MODE 0x94 - -#define AW_A10_PIT_COUNT_CTL 0xa0 -#define AW_A10_PIT_COUNT_RL_EN 0x2 -#define AW_A10_PIT_COUNT_CLR_EN 0x1 -#define AW_A10_PIT_COUNT_LO 0xa4 -#define AW_A10_PIT_COUNT_HI 0xa8 - -#define AW_A10_PIT_TIMER_BASE 0x10 -#define AW_A10_PIT_TIMER_BASE_END \ - (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) - -#define AW_A10_PIT_DEFAULT_CLOCK 0x4 - typedef struct AwA10PITState AwA10PITState; =20 typedef struct AwA10TimerContext { diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b31a0bcd43..00f7cc492d 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -24,6 +24,36 @@ #include "qemu/log.h" #include "qemu/module.h" =20 +#define AW_A10_PIT_TIMER_NR 6 + +#define AW_A10_PIT_TIMER_IRQ_EN 0 +#define AW_A10_PIT_TIMER_IRQ_ST 0x4 + +#define AW_A10_PIT_TIMER_CONTROL 0x0 +#define AW_A10_PIT_TIMER_EN 0x1 +#define AW_A10_PIT_TIMER_RELOAD 0x2 +#define AW_A10_PIT_TIMER_MODE 0x80 + +#define AW_A10_PIT_TIMER_INTERVAL 0x4 +#define AW_A10_PIT_TIMER_COUNT 0x8 +#define AW_A10_PIT_WDOG_CONTROL 0x90 +#define AW_A10_PIT_WDOG_MODE 0x94 + +#define AW_A10_PIT_COUNT_CTL 0xa0 +#define AW_A10_PIT_COUNT_RL_EN 0x2 +#define AW_A10_PIT_COUNT_CLR_EN 0x1 +#define AW_A10_PIT_COUNT_LO 0xa4 +#define AW_A10_PIT_COUNT_HI 0xa8 + +#define AW_A10_PIT_TIMER_BASE 0x10 +#define AW_A10_PIT_TIMER_BASE_END \ + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) + +#define AW_A10_PIT_DEFAULT_CLOCK 0x4 + +#define AW_A10_PIT(obj) \ + OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) + static void a10_pit_update_irq(AwA10PITState *s) { int i; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JsHtfge5h+5q2LZhmNIpaj2lzwktX3gFRpdUNeSwNQI=; b=AxqVhc0AEZh1OEee/AvnEa+KucuM+1JvChO4bzf1IaK0NMw5Oluazg5ZXm+As+ki/r GRBOh8OwvUfomKIztwEauMgbCIV4GWs/nXTVh1IYG63uzuLGiMLOKvhgyBdRD6a9ExTr BW/OAqhnZH6rIxNJGzCcVdZCBUDr7ekksShf4lG3rRy7n71M5hcdfnejebT3xGi48flk //ynxSxEVIVoWMUg2EwESTsawVVVZnADKFQpOyoHEfqQZaz6SRYEk9gQzLT9lTBDGi+7 rMcUb/Ml0z4XNL4H0cjurPaDrolA0OvTuKPF1n2kR/YB27oafAv4FVdpcN8xMzCDTOM0 UE8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JsHtfge5h+5q2LZhmNIpaj2lzwktX3gFRpdUNeSwNQI=; b=gIcVtE2Xe6O/DDYyGgS0mPT7HKUlVO0s/hToe50722XWi08KOO+1DxMVQXYHPklFn0 eRUe7k+2ssUKr7NuEV1WypUi/gbZUTpyNXAFJDgUB4lqaRaT5MrJvnsS3rVOFY/skHJt q1lFipGQR5yc+nWPkLHn+CPxKONsD0bhbsSyggDJgH9U/oVPUUNHxlczPHPwh2AT2p8q /c86qGUDgr5bZb6RWFW+eTqoY0L9zy+FmNjQ+8cjGi2qQGbOJZLDe7HCLe2/08xQRF29 coI7D2rs6A1HIF4Zsi742n7UqDk6km4TO4kZbdDOo0fDmKWuRKq06yWlybA9GsSvO2Zj fG9w== X-Gm-Message-State: APjAAAWvehfFsVpY0iX08Rq/++yKoUXQ6uWvYOnwoTpBA3z4kkwmxn+Y GYv4Q5GlcTFZA9b2y3CQUIRNp0UG X-Google-Smtp-Source: APXvYqwWRKu9WQ9vVRJb36FShcdSAo7xQFL8A2h3uVIibUKhG9vH+y7w0fPBXskoRo9posLcaJ2sbw== X-Received: by 2002:a05:600c:54c:: with SMTP id k12mr11859443wmc.124.1576781495869; Thu, 19 Dec 2019 10:51:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 05/13] hw/timer/allwinner: Rename the ptimer field Date: Thu, 19 Dec 2019 19:51:19 +0100 Message-Id: <20191219185127.24388-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We will later use the 'timer' field name to access all the timer related fields. The name is already use, we need to rename first. 'ptimer' is a good name. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 34 ++++++++++++++-------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index c28ee5ca47..a60b9f3031 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -20,7 +20,7 @@ struct AwA10PITState { SysBusDevice parent_obj; /*< public >*/ qemu_irq irq[AW_PIT_TIMER_MAX]; - ptimer_state * timer[AW_PIT_TIMER_MAX]; + ptimer_state * ptimer[AW_PIT_TIMER_MAX]; AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 00f7cc492d..effdf91344 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -83,7 +83,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset,= unsigned size) case AW_A10_PIT_TIMER_INTERVAL: return s->interval[index]; case AW_A10_PIT_TIMER_COUNT: - s->count[index] =3D ptimer_get_count(s->timer[index]); + s->count[index] =3D ptimer_get_count(s->ptimer[index]); return s->count[index]; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -109,7 +109,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offse= t, unsigned size) return 0; } =20 -/* Must be called inside a ptimer transaction block for s->timer[index] */ +/* Must be called inside a ptimer transaction block for s->ptimer[index] */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; @@ -119,7 +119,7 @@ static void a10_pit_set_freq(AwA10PITState *s, int inde= x) source_freq =3D s->clk_freq[source]; =20 if (source_freq) { - ptimer_set_freq(s->timer[index], source_freq / prescaler); + ptimer_set_freq(s->ptimer[index], source_freq / prescaler); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", __func__, source); @@ -148,27 +148,27 @@ static void a10_pit_write(void *opaque, hwaddr offset= , uint64_t value, switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: s->control[index] =3D value; - ptimer_transaction_begin(s->timer[index]); + ptimer_transaction_begin(s->ptimer[index]); a10_pit_set_freq(s, index); if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { - ptimer_set_count(s->timer[index], s->interval[index]); + ptimer_set_count(s->ptimer[index], s->interval[index]); } if (s->control[index] & AW_A10_PIT_TIMER_EN) { int oneshot =3D 0; if (s->control[index] & AW_A10_PIT_TIMER_MODE) { oneshot =3D 1; } - ptimer_run(s->timer[index], oneshot); + ptimer_run(s->ptimer[index], oneshot); } else { - ptimer_stop(s->timer[index]); + ptimer_stop(s->ptimer[index]); } - ptimer_transaction_commit(s->timer[index]); + ptimer_transaction_commit(s->ptimer[index]); break; case AW_A10_PIT_TIMER_INTERVAL: s->interval[index] =3D value; - ptimer_transaction_begin(s->timer[index]); - ptimer_set_limit(s->timer[index], s->interval[index], 1); - ptimer_transaction_commit(s->timer[index]); + ptimer_transaction_begin(s->ptimer[index]); + ptimer_set_limit(s->ptimer[index], s->interval[index], 1); + ptimer_transaction_commit(s->ptimer[index]); break; case AW_A10_PIT_TIMER_COUNT: s->count[index] =3D value; @@ -241,7 +241,7 @@ static const VMStateDescription vmstate_a10_pit =3D { VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_PTIMER_ARRAY(ptimer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; @@ -259,10 +259,10 @@ static void a10_pit_reset(DeviceState *dev) s->control[i] =3D AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] =3D 0; s->count[i] =3D 0; - ptimer_transaction_begin(s->timer[i]); - ptimer_stop(s->timer[i]); + ptimer_transaction_begin(s->ptimer[i]); + ptimer_stop(s->ptimer[i]); a10_pit_set_freq(s, i); - ptimer_transaction_commit(s->timer[i]); + ptimer_transaction_commit(s->ptimer[i]); } s->watch_dog_mode =3D 0; s->watch_dog_control =3D 0; @@ -280,7 +280,7 @@ static void a10_pit_timer_cb(void *opaque) if (s->control[i] & AW_A10_PIT_TIMER_EN) { s->irq_status |=3D 1 << i; if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); + ptimer_stop(s->ptimer[i]); s->control[i] &=3D ~AW_A10_PIT_TIMER_EN; } a10_pit_update_irq(s); @@ -305,7 +305,7 @@ static void a10_pit_init(Object *obj) =20 tc->container =3D s; tc->index =3D i; - s->timer[i] =3D ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DE= FAULT); + s->ptimer[i] =3D ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_D= EFAULT); } } =20 --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576782187; cv=none; d=zohomail.com; s=zohoarc; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EvN7owG5HPoEIvZGOHW50DRqlmt77IJjf48sxQbIWC8=; b=iQN0Ey6TvoUdvQhGvT3+wzjLpiqH49Soc8MMq9/2F18zlaA3ixJrdSQHcbQZMDUGaa EU9frq4JchJFigdK3xQy4N/UEYQUL5kWlIsGIEupClQxX1zZuBfvZzyATVefvtn6XC2o FsNwwihiNerV0zn7OO/AZLIbAVfwnw+2GUTPyo8Z6rFUXCoUp/Z/Q96gJnffvCG01Tis OR9uOWl8v23oBrLlLZTKGfE1QWcbL4XWtVueuN+xbyNhYJ4pQbpQlDNewDIPK9Wu2izU ZYr4Mu4UYQ8gDsLJgIEy7m4VXMz4ab5KL06ast+ZlbAracfi/CyMV8aGbr2aTKJel1P6 GTNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EvN7owG5HPoEIvZGOHW50DRqlmt77IJjf48sxQbIWC8=; b=WuGJVqmYolxpuoh4B5Zzsr1TjjsLKLonvI09rPh4ZxVsL6zrHg1KFNbRpppGBkcj98 0Gj1IULYi+fTJaN3jMG/4TqjKjsnQj0tDUxs4d7YG8ZNUagzCRlhhO60Ktu2PxWHnQcp 7rBiIQN+cfM3KeqwH8foDY7quvQ/+q7o2v7fpWaRTe3hwLVXKtGe79D6NHcVGz8TArl7 xJJVYVd3yLm+QZeHz4uJZYs2A1VDB/xyN2bQN47eCS8/YESRiWIzhuGUt7dSP+hJZRj9 cNVynoSV+ipazEPyx9oy9Hs0pvg3rVFx7RV4Zh14AhBoXUcGKj9RvSNco57iJHUjvThn C+Rw== X-Gm-Message-State: APjAAAUqnpoF41E+GDfU+tv0E+GJbOVCYjEY+mGU/ABH3ciThPKu2T27 Vr8Q09q/2yqGtcQfNdlZq0vSYLU6 X-Google-Smtp-Source: APXvYqw9XQSwqS46Sp/Xh8kZUtnRV4WfPSCwWth8x8BajCzCyGJiyXXbtmQlP2TAUocuawJcJJfw7Q== X-Received: by 2002:a1c:8055:: with SMTP id b82mr11828185wmd.127.1576781497017; Thu, 19 Dec 2019 10:51:37 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 06/13] hw/timer/allwinner: Rename 'timer_context' as 'timer' Date: Thu, 19 Dec 2019 19:51:20 +0100 Message-Id: <20191219185127.24388-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The previous 'timer' field has been renamed as 'ptimer'. The 'timer_context' can now be simplified as 'timer'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index a60b9f3031..b5ac6898fa 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -21,7 +21,7 @@ struct AwA10PITState { /*< public >*/ qemu_irq irq[AW_PIT_TIMER_MAX]; ptimer_state * ptimer[AW_PIT_TIMER_MAX]; - AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; =20 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index effdf91344..44e6eee3a8 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -301,7 +301,7 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); =20 for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { - AwA10TimerContext *tc =3D &s->timer_context[i]; + AwA10TimerContext *tc =3D &s->timer[i]; =20 tc->container =3D s; tc->index =3D i; --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576782309; cv=none; d=zohomail.com; s=zohoarc; b=FWrTgiAraPoVh8uJkYcuf+8YodeJ9Mz9E1Y93pG+TPmPrcv6oO/elI1IKIZJ1cIxqj4yAlfYm+9qOVX3JXqNWwjK7UTnAarrTBZgObR0DmmDpBgK0F5uws5D79TBZ7a+7BFuGaoTKDPDFCPHH0e0KCzQquStfK7xHxyoAk3Qi8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576782309; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=F0kiIbIZh2hpTU926tVBzFigq5BCxfMgI96wuDOtzCBrWBIlaJZtwKCs5uuuvelxCBF+4qmnhf/ZVP6iMIPhLIwK6mUphlRuGNbT+r36octKAJYbSKPwIch6tHXGbak9ThUT25wou+NTYWTnfUxb3Yx2jfyROHAXFE8cHScw4rc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576782309553518.6709901861976; Thu, 19 Dec 2019 11:05:09 -0800 (PST) Received: from localhost ([::1]:46838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii16h-00067R-FG for importer@patchew.org; Thu, 19 Dec 2019 14:05:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39968) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0ti-00078R-GQ for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tg-00083J-Nj for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:42 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52233) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tg-0007yc-F1; Thu, 19 Dec 2019 13:51:40 -0500 Received: by mail-wm1-x343.google.com with SMTP id p9so6523558wmc.2; Thu, 19 Dec 2019 10:51:40 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=tlF1dLp9sSYb8LMXVv7K7cDXZlqumuq9LifLg45AsPkz5CeM5+i6LSNjhc8gBBXPDo YsEcvuQ8Zx/AmvldOwOmHna/+YAIB1HQt/zbvalN2mgZNZof0MwB/fK6D99EhA7nowgx 1E6IWPASbpIk38Ci6t+AJRXyg7MuuJwNrDQ3ANnKhifhOH7r3hgihgFScbtwzqDebmsu Yh8PVGvAktM9Ot0bgGIFC4MxZCH/nyUU4fwJpE7+IGLIHX/PbMy+LXqyFD+hovWemJtu LP7BvI8zCl4Ju2l4vZUfsL2uRXassV8+/zdX81E7lTF8Yb0qIo+1Cxs2slS8jDuw9Vzp lasw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=l0nyZCRyJ6JkbBfp8AXW56Y5d9CQVflpNOYHa3iG3c5t3AbwsZ6lAA0HEW9fIiubng voFHB12Ou6yeuT4uzhY8t1c6zyejgmIWjlRgydWZfdsebX53/tVYO7siNwKn3Ka01pZR JLOfx2AtTcVUwB8HhOBO/R2iesjb2WfAqDeWyPuOIyi5SbytsyUu7yPFbMmrZBEYJ5El 9nfZLTL9EAcDttU2ZSBU92IpZeM8xt3X/m5S9GVnSduNmnn8Qgw+JXF0s+zMwGgaQ9H5 uluXlsmCo43se1kzDKVCXqk2PUhk3DuJW+D7TnBnfIYWNZRW0W4AbqRZqbd5tmltEskM eOIQ== X-Gm-Message-State: APjAAAUKXEtbDxsitxP1haJHg0GnOm9KrcYn2ZGDggMN2w/5mU/W0ql/ zFV2Cs2wUv0yGdDSnsG/aQn1BMlx X-Google-Smtp-Source: APXvYqwFJu/ocP0dt38fiw9hi6XsBa0pFZ0dZoHv5eBxSfExfizRYD91ZAkeJ4XoRUjOGNkp7kTN1A== X-Received: by 2002:a1c:7215:: with SMTP id n21mr12019344wmc.154.1576781498236; Thu, 19 Dec 2019 10:51:38 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 07/13] hw/timer/allwinner: Move timer specific fields into AwA10TimerContext Date: Thu, 19 Dec 2019 19:51:21 +0100 Message-Id: <20191219185127.24388-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Move all the timer-related fields into the same structure. We scrambled the migration structure, so we need to increase the version_id. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Before I was using g_new(), now I keep AW_PIT_TIMER_MAX so We might avoid this patch. --- include/hw/timer/allwinner-a10-pit.h | 10 +-- hw/timer/allwinner-a10-pit.c | 99 ++++++++++++++++------------ 2 files changed, 63 insertions(+), 46 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index b5ac6898fa..e0f864a954 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -13,23 +13,23 @@ typedef struct AwA10PITState AwA10PITState; typedef struct AwA10TimerContext { AwA10PITState *container; int index; + ptimer_state *ptimer; + qemu_irq irq; + uint32_t control; + uint32_t interval; + uint32_t count; } AwA10TimerContext; =20 struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_PIT_TIMER_MAX]; - ptimer_state * ptimer[AW_PIT_TIMER_MAX]; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; =20 uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_PIT_TIMER_MAX]; - uint32_t interval[AW_PIT_TIMER_MAX]; - uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 44e6eee3a8..ea92fdda32 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -59,7 +59,8 @@ static void a10_pit_update_irq(AwA10PITState *s) int i; =20 for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { - qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i= ))); + qemu_set_irq(s->timer[i].irq, + !!(s->irq_status & s->irq_enable & (1 << i))); } } =20 @@ -79,12 +80,12 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offse= t, unsigned size) index -=3D 1; switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: - return s->control[index]; + return s->timer[index].control; case AW_A10_PIT_TIMER_INTERVAL: - return s->interval[index]; + return s->timer[index].interval; case AW_A10_PIT_TIMER_COUNT: - s->count[index] =3D ptimer_get_count(s->ptimer[index]); - return s->count[index]; + s->timer[index].count =3D ptimer_get_count(s->timer[index].pti= mer); + return s->timer[index].count; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__, (int)offset); @@ -109,17 +110,17 @@ static uint64_t a10_pit_read(void *opaque, hwaddr off= set, unsigned size) return 0; } =20 -/* Must be called inside a ptimer transaction block for s->ptimer[index] */ +/* Must be called inside a ptimer transaction block for s->timer[idx].ptim= er */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; =20 - prescaler =3D 1 << extract32(s->control[index], 4, 3); - source =3D extract32(s->control[index], 2, 2); + prescaler =3D 1 << extract32(s->timer[index].control, 4, 3); + source =3D extract32(s->timer[index].control, 2, 2); source_freq =3D s->clk_freq[source]; =20 if (source_freq) { - ptimer_set_freq(s->ptimer[index], source_freq / prescaler); + ptimer_set_freq(s->timer[index].ptimer, source_freq / prescaler); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", __func__, source); @@ -147,31 +148,33 @@ static void a10_pit_write(void *opaque, hwaddr offset= , uint64_t value, index -=3D 1; switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: - s->control[index] =3D value; - ptimer_transaction_begin(s->ptimer[index]); + s->timer[index].control =3D value; + ptimer_transaction_begin(s->timer[index].ptimer); a10_pit_set_freq(s, index); - if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { - ptimer_set_count(s->ptimer[index], s->interval[index]); + if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { + ptimer_set_count(s->timer[index].ptimer, + s->timer[index].interval); } - if (s->control[index] & AW_A10_PIT_TIMER_EN) { + if (s->timer[index].control & AW_A10_PIT_TIMER_EN) { int oneshot =3D 0; - if (s->control[index] & AW_A10_PIT_TIMER_MODE) { + if (s->timer[index].control & AW_A10_PIT_TIMER_MODE) { oneshot =3D 1; } - ptimer_run(s->ptimer[index], oneshot); + ptimer_run(s->timer[index].ptimer, oneshot); } else { - ptimer_stop(s->ptimer[index]); + ptimer_stop(s->timer[index].ptimer); } - ptimer_transaction_commit(s->ptimer[index]); + ptimer_transaction_commit(s->timer[index].ptimer); break; case AW_A10_PIT_TIMER_INTERVAL: - s->interval[index] =3D value; - ptimer_transaction_begin(s->ptimer[index]); - ptimer_set_limit(s->ptimer[index], s->interval[index], 1); - ptimer_transaction_commit(s->ptimer[index]); + s->timer[index].interval =3D value; + ptimer_transaction_begin(s->timer[index].ptimer); + ptimer_set_limit(s->timer[index].ptimer, + s->timer[index].interval, 1); + ptimer_transaction_commit(s->timer[index].ptimer); break; case AW_A10_PIT_TIMER_COUNT: - s->count[index] =3D value; + s->timer[index].count =3D value; break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -226,22 +229,35 @@ static Property a10_pit_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static const VMStateDescription vmstate_aw_timer =3D { + .name =3D "aw_timer", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(control, AwA10TimerContext), + VMSTATE_UINT32(interval, AwA10TimerContext), + VMSTATE_UINT32(count, AwA10TimerContext), + VMSTATE_PTIMER(ptimer, AwA10TimerContext), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_a10_pit =3D { .name =3D "a10.pit", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, + AW_PIT_TIMER_MAX, + 0, vmstate_aw_timer, + AwA10TimerContext), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(ptimer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; @@ -256,13 +272,13 @@ static void a10_pit_reset(DeviceState *dev) a10_pit_update_irq(s); =20 for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { - s->control[i] =3D AW_A10_PIT_DEFAULT_CLOCK; - s->interval[i] =3D 0; - s->count[i] =3D 0; - ptimer_transaction_begin(s->ptimer[i]); - ptimer_stop(s->ptimer[i]); + s->timer[i].control =3D AW_A10_PIT_DEFAULT_CLOCK; + s->timer[i].interval =3D 0; + s->timer[i].count =3D 0; + ptimer_transaction_begin(s->timer[i].ptimer); + ptimer_stop(s->timer[i].ptimer); a10_pit_set_freq(s, i); - ptimer_transaction_commit(s->ptimer[i]); + ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode =3D 0; s->watch_dog_control =3D 0; @@ -277,11 +293,11 @@ static void a10_pit_timer_cb(void *opaque) AwA10PITState *s =3D tc->container; uint8_t i =3D tc->index; =20 - if (s->control[i] & AW_A10_PIT_TIMER_EN) { + if (s->timer[i].control & AW_A10_PIT_TIMER_EN) { s->irq_status |=3D 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->ptimer[i]); - s->control[i] &=3D ~AW_A10_PIT_TIMER_EN; + if (s->timer[i].control & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i].ptimer); + s->timer[i].control &=3D ~AW_A10_PIT_TIMER_EN; } a10_pit_update_irq(s); } @@ -294,7 +310,7 @@ static void a10_pit_init(Object *obj) uint8_t i; =20 for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { - sysbus_init_irq(sbd, &s->irq[i]); + sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); @@ -305,7 +321,8 @@ static void a10_pit_init(Object *obj) =20 tc->container =3D s; tc->index =3D i; - s->ptimer[i] =3D ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_D= EFAULT); + s->timer[i].ptimer =3D ptimer_init(a10_pit_timer_cb, tc, + PTIMER_POLICY_DEFAULT); } } =20 --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tW8l9xeWxnpc6CHLbxLBaneaw92aGrVjK1sQT+wYwbY=; b=AzQc9jaV4e6K0Ae50LqzRDyN7zrg+wj6NVaot8/qY7K0pLOCo5Rtp6tqvjqbpKDTm2 fTMIBzM4FVzuxpO4hMGutBUi6Xtqsf5SCwaMtXnojiuWtGe1SQlPnN5T1M4DSmy02EVH +A4hMFZkYsWYA3Vf24mB1dt8CmzD0Ea+fwKGbipdPQt5xkPdzWQ2/uUT3lWwqQolPJ0l d67XERN8WOFO2PaAn0jElM+Uc/fSmnkniVPKv4hQTRIS2j7Aw8kw0N3Rd94FECsCwU+3 FDEUY0zCisGQxzl027f9YOjQAWIOPw26U17WPwIg9ube9s8fXcC4Z65PdCgcDFI73bUi ymJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tW8l9xeWxnpc6CHLbxLBaneaw92aGrVjK1sQT+wYwbY=; b=jExws7hmiQOIEbiG9DqZohrad8oW7iCu5GddJHa5sJLtDf9KRV0aZvZU0MologoHml xSgm7R8BConv1XVLDF4yFqJD/OalcRqKXLLrCkTLJsUArWRT9HKaQ4T/Lm3bqnB27aE1 xMpRkWomCHqLP4KbtPi0uEzy5RBlW++Vi/DHghfYDPaDHFLcG7tTRFcwnvPuhtablHYM iVMSs6hyX1AFq8fEUftxOKQg8wDjezm8CbmaGeJyzOQVGrXoIxVMjBu3SxN2bPyNaeIp qc0qtUFN0tgH1q4OVTJcRAj7NJlU+BeohIU/O/rC/BVnmjEXhb/F+P65S4g6+YjM9IWf qTgQ== X-Gm-Message-State: APjAAAUecWFvhAd9saLav/LdBq4e6WIvzjr6o+nrhCNOSTy0aYoEgcEp tidnso+5czSMmyKLbEUUmF/LLeJt X-Google-Smtp-Source: APXvYqzS0NVHipIhcYaLjA7fvBbKiu9b6OCALSCEevmOk+oHbcvaEqyp9DFVU0bR9Gict0k9lljKnQ== X-Received: by 2002:a5d:6b88:: with SMTP id n8mr11401748wrx.288.1576781499364; Thu, 19 Dec 2019 10:51:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 08/13] hw/timer/allwinner: Add a timer_count field Date: Thu, 19 Dec 2019 19:51:22 +0100 Message-Id: <20191219185127.24388-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) To be able to support controllers with less than 6 timers, we need a field to be able to iterate over the different count. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index e0f864a954..8c64c33f01 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -24,6 +24,7 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ + size_t timer_count; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ea92fdda32..3f47588703 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -58,7 +58,7 @@ static void a10_pit_update_irq(AwA10PITState *s) { int i; =20 - for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i =3D 0; i < s->timer_count; i++) { qemu_set_irq(s->timer[i].irq, !!(s->irq_status & s->irq_enable & (1 << i))); } @@ -271,7 +271,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status =3D 0; a10_pit_update_irq(s); =20 - for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i =3D 0; i < s->timer_count; i++) { s->timer[i].control =3D AW_A10_PIT_DEFAULT_CLOCK; s->timer[i].interval =3D 0; s->timer[i].count =3D 0; @@ -309,14 +309,16 @@ static void a10_pit_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); uint8_t i; =20 - for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { + s->timer_count =3D AW_A10_PIT_TIMER_NR; + + for (i =3D 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); sysbus_init_mmio(sbd, &s->iomem); =20 - for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i =3D 0; i < s->timer_count; i++) { AwA10TimerContext *tc =3D &s->timer[i]; =20 tc->container =3D s; --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576782419; cv=none; d=zohomail.com; s=zohoarc; b=EvxZMbCCTLMJqF0UWPPXr5lEtSXyfhGP4Ekz0k5UMIXqDMpYOXT8X9t7TcMKjdZA8VP9FsAhXfMxrH1SLPvSNqDipxc2MS8pxQhRZPBipgVSsiB86k4eNRo94dNbQIEk9iaJ9/aDT5ysVLiJkQgBIu6a1yncGVY59xFxQl6bJLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576782419; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xqTqck0MunQzlvW3fvG1Eh5JVsO+310wsc6ir4XWOg8=; b=MfWy7tw0O/lTaLMPfN0dXUBZJsWwG0WujGV+KGU8d0h/eb1Hat0/Mk6biXVFr5POGBVcfd0KKWQTyxArEYsDm2vjZemsv6oMyJgjeon2FOBU+iX6frexTEsXdGuFY1YfjSalMWMz+1PYgWd1c2ED4zT6aTAoEC1x+dS61mb6B1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576782419717679.610001585267; Thu, 19 Dec 2019 11:06:59 -0800 (PST) Received: from localhost ([::1]:46862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii18T-0007cv-Qe for importer@patchew.org; Thu, 19 Dec 2019 14:06:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40084) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tj-0007AO-JS for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0ti-0008BU-5L for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:43 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45868) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0th-00085U-R3; Thu, 19 Dec 2019 13:51:42 -0500 Received: by mail-wr1-x442.google.com with SMTP id j42so7020432wrj.12; Thu, 19 Dec 2019 10:51:41 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xqTqck0MunQzlvW3fvG1Eh5JVsO+310wsc6ir4XWOg8=; b=DbT48iy/7ZvB5pfzW11tJNj8wYlfwPabB00bOKJ0VQCM46ByzLZ4a49Xm0UmmMz/Gk BGzwYIr+W3WolPSvYe9MMm2oHybcm/jmi0jszdd7i557I3GQ8/ltFe9RruaamPmLfoT4 4K9qkxJazaD2em1FwLUI1ZgEiOG4Xr8mXmYLBhkIZwAX/ZGsvPCvMEa8vu6jWHGFP0PL O+xvyO5ZZTE8Hes37CPKCnSis217ZDk27eSmewXK8UAnA3FEL4qSTxfQfTJda/nPg9P8 yaXQlotZOlEeiz77X81NBHRWjEV+39FKZ1wBvsb8kXvsvscMZ6XMp5zazNLXq+f9fbf2 bY7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xqTqck0MunQzlvW3fvG1Eh5JVsO+310wsc6ir4XWOg8=; b=d2OQgjyq82a1PfZoGPtPp3E0PZoBd+NU15oX7Yxg0aKBoWwPbtEWxH/SLftSsNIUgf 3b/xdxUqhcjxrNtvWM857PcTeKAGtWoQJiZo9YlZzdE8h6RG/UbvZqN5sI98hpH8olDq Pq7wlLJ53QaneO4IhYMV0x9Q18EcgAfs+wyShfJTCOIKcP3et0zx9HuDs3QAEVF3Wrhu 7F7pwsO35d/6IPWU0KQ5Ho1QMSPxpJu1RQ8Zl3S9sOfBKUMrPqJRivaurVKhKA3dTAam oDw+J38GqZaspBh1xk25rPIeYgOgEV+BC3SrrH5jS3bZNpeSqzzf5KLLr828AufvYeFV qfLQ== X-Gm-Message-State: APjAAAUn3ZFZnEY+xycK7s/WBPyufXVtWZIsYIeVwJg8MlSFM+4NG6T6 U9FTqCdIMIoVKWbC73/Gla6VDdQu X-Google-Smtp-Source: APXvYqx/VGHdVWsKIJFPURExgJ03KjIrRp4uQuR5eGkcfc5bbnhAU+9EE5LXjLtXy9fSJPgB7ME4Ig== X-Received: by 2002:a5d:6144:: with SMTP id y4mr11215374wrt.367.1576781500573; Thu, 19 Dec 2019 10:51:40 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 09/13] hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState Date: Thu, 19 Dec 2019 19:51:23 +0100 Message-Id: <20191219185127.24388-10-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This structure will be common to various Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/allwinner-a10-pit.h | 6 +++--- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index 8c64c33f01..3a47633cc4 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -10,7 +10,7 @@ =20 typedef struct AwA10PITState AwA10PITState; =20 -typedef struct AwA10TimerContext { +typedef struct AllwinnerTmrState { AwA10PITState *container; int index; ptimer_state *ptimer; @@ -18,14 +18,14 @@ typedef struct AwA10TimerContext { uint32_t control; uint32_t interval; uint32_t count; -} AwA10TimerContext; +} AllwinnerTmrState; =20 struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ size_t timer_count; - AwA10TimerContext timer[AW_PIT_TIMER_MAX]; + AllwinnerTmrState timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; =20 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 3f47588703..ecfc198937 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -234,10 +234,10 @@ static const VMStateDescription vmstate_aw_timer =3D { .version_id =3D 0, .minimum_version_id =3D 0, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(control, AwA10TimerContext), - VMSTATE_UINT32(interval, AwA10TimerContext), - VMSTATE_UINT32(count, AwA10TimerContext), - VMSTATE_PTIMER(ptimer, AwA10TimerContext), + VMSTATE_UINT32(control, AllwinnerTmrState), + VMSTATE_UINT32(interval, AllwinnerTmrState), + VMSTATE_UINT32(count, AllwinnerTmrState), + VMSTATE_PTIMER(ptimer, AllwinnerTmrState), VMSTATE_END_OF_LIST() } }; @@ -252,7 +252,7 @@ static const VMStateDescription vmstate_a10_pit =3D { VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX, 0, vmstate_aw_timer, - AwA10TimerContext), + AllwinnerTmrState), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), @@ -289,7 +289,7 @@ static void a10_pit_reset(DeviceState *dev) =20 static void a10_pit_timer_cb(void *opaque) { - AwA10TimerContext *tc =3D opaque; + AllwinnerTmrState *tc =3D opaque; AwA10PITState *s =3D tc->container; uint8_t i =3D tc->index; =20 @@ -319,7 +319,7 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); =20 for (i =3D 0; i < s->timer_count; i++) { - AwA10TimerContext *tc =3D &s->timer[i]; + AllwinnerTmrState *tc =3D &s->timer[i]; =20 tc->container =3D s; tc->index =3D i; --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2xjfAFFEWDuI/P26T2zoS1xiDMGAz867DMgCQ/oLVWQ=; b=O+aNElJZM9BZIgZZ4qEWZvovUiVVhHa4bCbUzxy5LYpTL3dqp4lLuEpV0sCoYvSrsp R0mShX3Xsx0HkQXTfhWU4syLH9eIbzXIR+sunvozdbl34YVGZ44f7XMR9BbY2Tdo+/Zc fRWNPgGOxyBBBmrdKxat+Igs2PEZPQyhDzr+pZXbnpPTiX2jit0XF6aRhZ16T6HOgmkI pOnhokvGEfkUdTJXbADc+2gULgsGZpLHTWYzklcgXqWtTUKF2mfme0JUrFYpDOF3nKoX GYZX0/NrKCevHSV8ZblrJvRYjXknSN26XWDVpUPOkGNqYSNLYex0S2BHq1B/48+dZtVM V8xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2xjfAFFEWDuI/P26T2zoS1xiDMGAz867DMgCQ/oLVWQ=; b=ZXcTsPE/MNNEteuC6fdO76HfMF+Fi+x28zFFM2DAhJWSSZRdL/G190JnkELzje1jkb GKZLEGzxqKKla7klhZTJjvU0yc/yzqnk3kYKgxfZnhinN9+Hvdp8owMCNB3W5odD6w00 xDiUBLUi9OpWZYl+dRGsbDGM1k5K2jhR1k+P64FcXcG4mHkJ68/yTCrXl0xeKo/OJQd1 DkOuEL/Gs6y3L994AYcH0Z5JOCupMvD21uGEFO0lcCJCyZGk/T4GFAu5A85cuF3+tA/9 ZWJI9NxAiJMPwWHq2pyxNsArx3lFqedd9s214dFALKQsGYEYKw3XP+KHII8kw+clwuhT sEWA== X-Gm-Message-State: APjAAAWGJmtFAv3HXB+qXttV7Zph9xfLH6NwJejwN9n/FOrWXbSm7Jta WOnUn6gx/Dvk7P5r7CbTdsPsb7B6 X-Google-Smtp-Source: APXvYqydFAnJ4hd8urMS8wcjdPKs7mvlWIMWKFjb7Kon0j1BLY3xh/b4iEBJr4aqbjcH43/HZhjvDw== X-Received: by 2002:a5d:4602:: with SMTP id t2mr10796119wrq.37.1576781501829; Thu, 19 Dec 2019 10:51:41 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 10/13] hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState Date: Thu, 19 Dec 2019 19:51:24 +0100 Message-Id: <20191219185127.24388-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This structure will be common to various Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/allwinner-a10.h | 2 +- include/hw/timer/allwinner-a10-pit.h | 6 ++-- hw/timer/allwinner-a10-pit.c | 42 ++++++++++++++-------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 7d2d215630..28c043db39 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -30,7 +30,7 @@ typedef struct AwA10State { =20 ARMCPU cpu; qemu_irq irq[AW_A10_PIC_INT_NR]; - AwA10PITState timer; + AllwinnerTmrCtrlState timer; AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index 3a47633cc4..9e28c6697a 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -8,10 +8,10 @@ =20 #define AW_PIT_TIMER_MAX 6 =20 -typedef struct AwA10PITState AwA10PITState; +typedef struct AllwinnerTmrCtrlState AllwinnerTmrCtrlState; =20 typedef struct AllwinnerTmrState { - AwA10PITState *container; + AllwinnerTmrCtrlState *container; int index; ptimer_state *ptimer; qemu_irq irq; @@ -20,7 +20,7 @@ typedef struct AllwinnerTmrState { uint32_t count; } AllwinnerTmrState; =20 -struct AwA10PITState { +struct AllwinnerTmrCtrlState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ecfc198937..f2ac271e80 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -52,9 +52,9 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 =20 #define AW_A10_PIT(obj) \ - OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) =20 -static void a10_pit_update_irq(AwA10PITState *s) +static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) { int i; =20 @@ -66,7 +66,7 @@ static void a10_pit_update_irq(AwA10PITState *s) =20 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AwA10PITState *s =3D AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s =3D AW_A10_PIT(opaque); uint8_t index; =20 switch (offset) { @@ -111,7 +111,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offse= t, unsigned size) } =20 /* Must be called inside a ptimer transaction block for s->timer[idx].ptim= er */ -static void a10_pit_set_freq(AwA10PITState *s, int index) +static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; =20 @@ -130,7 +130,7 @@ static void a10_pit_set_freq(AwA10PITState *s, int inde= x) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AwA10PITState *s =3D AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s =3D AW_A10_PIT(opaque); uint8_t index; =20 switch (offset) { @@ -222,10 +222,10 @@ static const MemoryRegionOps a10_pit_ops =3D { }; =20 static Property a10_pit_properties[] =3D { - DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), - DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), - DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), - DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), + DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), + DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), + DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), + DEFINE_PROP_UINT32("clk3-freq", AllwinnerTmrCtrlState, clk_freq[3], 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -247,24 +247,24 @@ static const VMStateDescription vmstate_a10_pit =3D { .version_id =3D 2, .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(irq_enable, AwA10PITState), - VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, + VMSTATE_UINT32(irq_enable, AllwinnerTmrCtrlState), + VMSTATE_UINT32(irq_status, AllwinnerTmrCtrlState), + VMSTATE_STRUCT_ARRAY(timer, AllwinnerTmrCtrlState, AW_PIT_TIMER_MAX, 0, vmstate_aw_timer, AllwinnerTmrState), - VMSTATE_UINT32(watch_dog_mode, AwA10PITState), - VMSTATE_UINT32(watch_dog_control, AwA10PITState), - VMSTATE_UINT32(count_lo, AwA10PITState), - VMSTATE_UINT32(count_hi, AwA10PITState), - VMSTATE_UINT32(count_ctl, AwA10PITState), + VMSTATE_UINT32(watch_dog_mode, AllwinnerTmrCtrlState), + VMSTATE_UINT32(watch_dog_control, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_lo, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_hi, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_ctl, AllwinnerTmrCtrlState), VMSTATE_END_OF_LIST() } }; =20 static void a10_pit_reset(DeviceState *dev) { - AwA10PITState *s =3D AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s =3D AW_A10_PIT(dev); uint8_t i; =20 s->irq_enable =3D 0; @@ -290,7 +290,7 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { AllwinnerTmrState *tc =3D opaque; - AwA10PITState *s =3D tc->container; + AllwinnerTmrCtrlState *s =3D tc->container; uint8_t i =3D tc->index; =20 if (s->timer[i].control & AW_A10_PIT_TIMER_EN) { @@ -305,7 +305,7 @@ static void a10_pit_timer_cb(void *opaque) =20 static void a10_pit_init(Object *obj) { - AwA10PITState *s =3D AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s =3D AW_A10_PIT(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); uint8_t i; =20 @@ -341,7 +341,7 @@ static void a10_pit_class_init(ObjectClass *klass, void= *data) static const TypeInfo a10_pit_info =3D { .name =3D TYPE_AW_A10_PIT, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(AwA10PITState), + .instance_size =3D sizeof(AllwinnerTmrCtrlState), .instance_init =3D a10_pit_init, .class_init =3D a10_pit_class_init, }; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EUHgqN5LBpAPTBRZ9G6aJDxWyEcBGmSlmJWyOyX8iGE=; b=C9XvGLU36y3C2NHjYPgZZvJRY0Di1d6uhh+ByZM9sPVnpIcRWurK+nc1NkWG6KhhYl AqIdsKBSp0rFLyU8qOWy/T/g3t44mS3GBcrDC4nf29+qfPRtCqswddeUWkJoqLABniBf A74RXxUFN8S9HG5aEJI+mVdFGq5js5Li5FQXeGKHovaxbNkDUlWQQ7NSsdHqQUe+qPsO f9p9kgkZSm4lk1Oyi8qbfdYMdGS1l3vyA4KzKnfD+uFmFvF78lEfPODm7xzRMju7DCg7 X5tvQ8yLGzcZ9vV7cEBDpuBdQVWoUTCcLl3EGlHjcQ8wkbTl3xoj3+0IM6rQlAfZX+qa hAlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EUHgqN5LBpAPTBRZ9G6aJDxWyEcBGmSlmJWyOyX8iGE=; b=IcvhRptTPccKFt4HXN6yfzLDy1DEmPS7DjYkO8yUG5skF4rkJ6yCMYdjw79wH4J3Yl X86RA2qE/r7sREmtM6Ocsf7sUaD0sPKrbL9NmmXCOxUtAvf1xsVAm3mIHCC3/ydwa845 UeAUIQpO+IeOCdDXVqbUFlNPpYzQXPn36fCiATgy+IRVrnqihoNwoXS9gLQ/rYi7ENj3 eKIcHh2KZp+fXABvA2duKi6w1UFQ2eA5H9XL+WBmft0jhRrKXylY4gLRhPI1NeItBOFu xxscc3z05KZNM4nUx5EBEBWiyDGk3almBsmYEMkdGxbNxdK3/FpFLdYHQwc+0R+6ei5F q6Yg== X-Gm-Message-State: APjAAAUKrh/rBIALRcsPGEKh9r5ux5o7Q/sBS0AXIMbLm7jcUWFUnlm+ U0g78dhjsmgd1B2Pkz6cXxHJlUno X-Google-Smtp-Source: APXvYqyUPse6Ucmkvok5w7yVpLadtdEF7/ACSG9oSf4lyHFc0HsctOIAx4Xp3T6L060ZH2dKgtxZPg== X-Received: by 2002:a5d:6349:: with SMTP id b9mr11469419wrw.346.1576781502942; Thu, 19 Dec 2019 10:51:42 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 11/13] hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device Date: Thu, 19 Dec 2019 19:51:25 +0100 Message-Id: <20191219185127.24388-12-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Extract the common code from the TYPE_AW_A10_PIT device into a new abstract device: TYPE_AW_COMMON_PIT, then use it as parent, so we inherit the same functionalities. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- At this point, the only fields we can modify are the timer_count and the region_size. Not enough to implement the H3 timer, since we need to move the WDOG register. Still some progress, so Niek can continue ;) --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 50 +++++++++++++++++++++++----- 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwin= ner-a10-pit.h index 9e28c6697a..8453a62706 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -4,6 +4,7 @@ #include "hw/ptimer.h" #include "hw/sysbus.h" =20 +#define TYPE_AW_COMMON_PIT "allwinner-timer-controller" #define TYPE_AW_A10_PIT "allwinner-A10-timer" =20 #define AW_PIT_TIMER_MAX 6 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index f2ac271e80..ad409b96a1 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -54,6 +54,20 @@ #define AW_A10_PIT(obj) \ OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) =20 +typedef struct AllwinnerTmrCtrlClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + size_t timer_count; + size_t region_size; +} AllwinnerTmrCtrlClass; + +#define AW_TIMER_CLASS(klass) \ + OBJECT_CLASS_CHECK(AllwinnerTmrCtrlClass, (klass), TYPE_AW_COMMON_PIT) +#define AW_TIMER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) + static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -303,19 +317,20 @@ static void a10_pit_timer_cb(void *opaque) } } =20 -static void a10_pit_init(Object *obj) +static void aw_pit_instance_init(Object *obj) { AllwinnerTmrCtrlState *s =3D AW_A10_PIT(obj); + AllwinnerTmrCtrlClass *c =3D AW_TIMER_GET_CLASS(s); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); uint8_t i; =20 - s->timer_count =3D AW_A10_PIT_TIMER_NR; + s->timer_count =3D c->timer_count; =20 for (i =3D 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, 0x400); + TYPE_AW_A10_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); =20 for (i =3D 0; i < s->timer_count; i++) { @@ -328,26 +343,45 @@ static void a10_pit_init(Object *obj) } } =20 -static void a10_pit_class_init(ObjectClass *klass, void *data) +static void aw_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->reset =3D a10_pit_reset; dc->props =3D a10_pit_properties; - dc->desc =3D "allwinner a10 timer"; + dc->desc =3D "Allwinner Timer Controller"; dc->vmsd =3D &vmstate_a10_pit; } =20 +static const TypeInfo allwinner_pit_info =3D { + .name =3D TYPE_AW_COMMON_PIT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D aw_pit_instance_init, + .instance_size =3D sizeof(AllwinnerTmrCtrlState), + .class_init =3D aw_timer_class_init, + .class_size =3D sizeof(AllwinnerTmrCtrlClass), + .abstract =3D true, +}; + +static void a10_pit_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AllwinnerTmrCtrlClass *atc =3D AW_TIMER_CLASS(klass); + + dc->desc =3D "Allwinner A10 Timer Controller"; + atc->timer_count =3D AW_A10_PIT_TIMER_NR; + atc->region_size =3D 0x400; +} + static const TypeInfo a10_pit_info =3D { .name =3D TYPE_AW_A10_PIT, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(AllwinnerTmrCtrlState), - .instance_init =3D a10_pit_init, + .parent =3D TYPE_AW_COMMON_PIT, .class_init =3D a10_pit_class_init, }; =20 static void a10_register_types(void) { + type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } =20 --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576782516; cv=none; d=zohomail.com; s=zohoarc; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qyhQROH0zglq4XFW1HtOmFf0aWLykn31mbrW4dYgWlw=; b=i5YwH8bvSKpQxpoKJrLWZAqXtF9THcvR3lEO9kEGOQsJFg93pncnTmCvOGe+0LRMJI VJNcEjLRMfudXXBAbr5e0GFY2tuLHKzM5A44Jve7P5OjusD5ul3eNGhz3vb+TZADDYmC GAwl7ozdCO+amGeMBP604ChVmVJRjW3EGR/HBGTQLJVcrjr+06dNRXmAa5oNLt3MY80l OYIZi/TW95hb5+pOXo4zTRoks3G7IUPkIkT7Oo2/9RynfzlEf6gZD1tYm4EdzG49Cod0 mqJdH1feN8TDjQ8vRZyJQT87WxD8135vpWsbOb8osGZOeK2IjFJoO+zaBjxF5XcN5JSH +Bjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qyhQROH0zglq4XFW1HtOmFf0aWLykn31mbrW4dYgWlw=; b=Q6L3yPFW83z/JeKG5NkXpFEXrMD7UpMUQAG3fs8ZbqcrQ6NHlfyjvMRFooQmTReIKP 3rk9diS17YzXubB/zGsTtzlc6+Tv0Ix3ebDKsxl0K1EG9RvaxyYLqRlOMOoOfdzoY22+ n/LJOK7bz8kRrEW2zbgkpiEnZA5BdV00qm40Xtrn10PMnZqEPILNjeG5G7CUCP3yBnh5 Es6MSuPgIqRzHHd5/txNkhxllIdIb/rIxPWNRQHo43IN1HEwx+VBEoh7ElFgyh9AwoRh Oc8O2L04T5zAEUV7XJKc88fmimboHKztZ/Td190f3kxkQ2K83Z9Dh4toJdongtrSyZ+s xH4Q== X-Gm-Message-State: APjAAAVH62bM50N9Cd9FyPHIbA6oItdYdRNX8Sj0K1WYjVgSuws0B0E8 y4uEUBEe7CAaCKX6sna36FD11G56 X-Google-Smtp-Source: APXvYqwfViom5RRGMotWWzFz7ZtejLLvnO4yQepB8PTG9RICXrSIdBWCsQnRweCWjT0yyeFDztq8Pg== X-Received: by 2002:a5d:4807:: with SMTP id l7mr11320272wrq.64.1576781504198; Thu, 19 Dec 2019 10:51:44 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 12/13] hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() Date: Thu, 19 Dec 2019 19:51:26 +0100 Message-Id: <20191219185127.24388-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This macro is now used by different Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ad409b96a1..7413f046cc 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -51,8 +51,8 @@ =20 #define AW_A10_PIT_DEFAULT_CLOCK 0x4 =20 -#define AW_A10_PIT(obj) \ - OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) +#define AW_TIMER_CTRL(obj) \ + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_COMMON_PIT) =20 typedef struct AllwinnerTmrCtrlClass { /*< private >*/ @@ -80,7 +80,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) =20 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AllwinnerTmrCtrlState *s =3D AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(opaque); uint8_t index; =20 switch (offset) { @@ -144,7 +144,7 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, = int index) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AllwinnerTmrCtrlState *s =3D AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(opaque); uint8_t index; =20 switch (offset) { @@ -278,7 +278,7 @@ static const VMStateDescription vmstate_a10_pit =3D { =20 static void a10_pit_reset(DeviceState *dev) { - AllwinnerTmrCtrlState *s =3D AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(dev); uint8_t i; =20 s->irq_enable =3D 0; @@ -319,7 +319,7 @@ static void a10_pit_timer_cb(void *opaque) =20 static void aw_pit_instance_init(Object *obj) { - AllwinnerTmrCtrlState *s =3D AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c =3D AW_TIMER_GET_CLASS(s); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); uint8_t i; @@ -330,7 +330,7 @@ static void aw_pit_instance_init(Object *obj) sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, c->region_size); + TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); =20 for (i =3D 0; i < s->timer_count; i++) { --=20 2.21.0 From nobody Thu May 2 08:33:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576782584; cv=none; d=zohomail.com; s=zohoarc; b=m6pWSZejg4aaeWrE+SNxhcApjLFgtKjXBmzo+NP/wdwcdCvIhenECaBNQ6f12p3Fa02Z8xI3A9yWpPqNVCWml6mwQa1guCoFB3kdDt0ffrnxLt/EYKFTaIr2a06/EdWnHs6yEencQ2pR1KYVOx/7TQoaq+DLF1eMpQv1Z973xMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576782584; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YyPr5A6rnL1yXh0BplYIOMYBILGoNVomOgJvBtF2zv8=; b=dXpIvtyw5jmOsjobqOVDXDJC20feiDW3/J/ExWPb7AOiPefQvkjJFVGJ3XiW1AQ/YvDvniflM7o+XibIXwyQI37y7ku7Qnjldy+lvQCi/+Sq4sTVvawJZv+iwVW9pQJAK9s9Tax3gHvhGKgABBvexX+8IKLJgIi5FwDb9Cd9I1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576782584913862.689505401737; Thu, 19 Dec 2019 11:09:44 -0800 (PST) Received: from localhost ([::1]:46900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii1B9-0002KU-Rd for importer@patchew.org; Thu, 19 Dec 2019 14:09:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40670) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0tp-0007M1-6b for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tn-0000DQ-DO for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:48 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:34084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tm-00007T-UD; Thu, 19 Dec 2019 13:51:47 -0500 Received: by mail-wr1-x442.google.com with SMTP id t2so7079099wrr.1; Thu, 19 Dec 2019 10:51:46 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YyPr5A6rnL1yXh0BplYIOMYBILGoNVomOgJvBtF2zv8=; b=gUuO85EmTJkhrApzSOHS/sPi8S4du85fP8278KxyPehzc58JtzuXRUDCRLHkbiuvp3 NPazvAgtkPY9ecZf5T0lc7UizXq/gbCP/e70LfomtWKylgfOUoWoig1KNrPvqKdjTVut kj4T5ALd+fG02eGAUgloEo/sTga7V1oWywzZXCmyYy/XtgytdRuvGZz+D0Bvf19x/EXk ZP/lw86I7jo9M4e6zkHA9y4I2guuaSO4Tula4t3nu6W8Foa3lL1D7/miOnbr9lrICrvB PYp1a7J1Pdew9MiHsTcWogWyYLKMKiqXu0FmbzU6APBcnc2YOW+zCerMqrPuxJO9fBcN GWLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YyPr5A6rnL1yXh0BplYIOMYBILGoNVomOgJvBtF2zv8=; b=bDf3O4bo4QDGUDPRcTShc3X1Di+4fJN8pA/VOFJj+25oQVS9kVzdDb3s+HU1hAYuhq kON0/utza1Q7536jopm/IMYZPMpHomldISpEON3E1bWNi9SlhLvmVp4nZsgphXavVr06 268AiIu/mtNoA/hMc7Ju+Lkbts2e3X41aCDLxiCswMWIMXOTm8K84py6YIrI8A7MI8pq 6gVXt+KFd6+7oU9h7/YbG1aa9G05qedlCitXsDvc9XoSb9Mwk+2FHyN9/5UUMHFaXlY6 ECNYZleXvFnfdllRTPPhU1PN4xytQJ4arVr1YCaHzwaunF6ybxQrjeQxnaKMd8d94DTJ 2K3A== X-Gm-Message-State: APjAAAU8kHw3/qFbu1Ip0A/2901COuryXBYofBpXotztEvrM5sleL8Fg yw1YJW6O7qySU5Pbp/qp17TB5BC4 X-Google-Smtp-Source: APXvYqyLyNogYXoyqkJOSnD1UD2EBFCbaWURl03eELNPKujhSBXoRXU2zHSTo8NDkUW5Kqs2meGf+A== X-Received: by 2002:a05:6000:cb:: with SMTP id q11mr10656214wrx.14.1576781505386; Thu, 19 Dec 2019 10:51:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 13/13] hw/timer/allwinner: Rename functions not specific to the A10 SoC Date: Thu, 19 Dec 2019 19:51:27 +0100 Message-Id: <20191219185127.24388-14-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) These functions are used by different Allwinner timer controllers, rename them. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/allwinner-a10-pit.c | 52 ++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 7413f046cc..dff534cfef 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -68,7 +68,7 @@ typedef struct AllwinnerTmrCtrlClass { #define AW_TIMER_GET_CLASS(obj) \ OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) =20 -static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) +static void allwinner_timer_update_irq(AllwinnerTmrCtrlState *s) { int i; =20 @@ -78,7 +78,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) } } =20 -static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) +static uint64_t allwinner_timer_read(void *opaque, hwaddr offset, unsigned= size) { AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(opaque); uint8_t index; @@ -125,7 +125,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offse= t, unsigned size) } =20 /* Must be called inside a ptimer transaction block for s->timer[idx].ptim= er */ -static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) +static void allwinner_ptimer_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; =20 @@ -141,8 +141,8 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, = int index) } } =20 -static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void allwinner_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) { AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(opaque); uint8_t index; @@ -150,11 +150,11 @@ static void a10_pit_write(void *opaque, hwaddr offset= , uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable =3D value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &=3D ~value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index =3D offset & 0xf0; @@ -164,7 +164,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, = uint64_t value, case AW_A10_PIT_TIMER_CONTROL: s->timer[index].control =3D value; ptimer_transaction_begin(s->timer[index].ptimer); - a10_pit_set_freq(s, index); + allwinner_ptimer_set_freq(s, index); if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { ptimer_set_count(s->timer[index].ptimer, s->timer[index].interval); @@ -229,13 +229,13 @@ static void a10_pit_write(void *opaque, hwaddr offset= , uint64_t value, } } =20 -static const MemoryRegionOps a10_pit_ops =3D { - .read =3D a10_pit_read, - .write =3D a10_pit_write, +static const MemoryRegionOps allwinner_timer_ops =3D { + .read =3D allwinner_timer_read, + .write =3D allwinner_timer_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static Property a10_pit_properties[] =3D { +static Property allwinner_timer_properties[] =3D { DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), @@ -276,14 +276,14 @@ static const VMStateDescription vmstate_a10_pit =3D { } }; =20 -static void a10_pit_reset(DeviceState *dev) +static void allwinner_timer_reset(DeviceState *dev) { AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(dev); uint8_t i; =20 s->irq_enable =3D 0; s->irq_status =3D 0; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); =20 for (i =3D 0; i < s->timer_count; i++) { s->timer[i].control =3D AW_A10_PIT_DEFAULT_CLOCK; @@ -291,7 +291,7 @@ static void a10_pit_reset(DeviceState *dev) s->timer[i].count =3D 0; ptimer_transaction_begin(s->timer[i].ptimer); ptimer_stop(s->timer[i].ptimer); - a10_pit_set_freq(s, i); + allwinner_ptimer_set_freq(s, i); ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode =3D 0; @@ -301,7 +301,7 @@ static void a10_pit_reset(DeviceState *dev) s->count_ctl =3D 0; } =20 -static void a10_pit_timer_cb(void *opaque) +static void allwinner_ptimer_cb(void *opaque) { AllwinnerTmrState *tc =3D opaque; AllwinnerTmrCtrlState *s =3D tc->container; @@ -313,11 +313,11 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i].ptimer); s->timer[i].control &=3D ~AW_A10_PIT_TIMER_EN; } - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); } } =20 -static void aw_pit_instance_init(Object *obj) +static void allwinner_timer_instance_init(Object *obj) { AllwinnerTmrCtrlState *s =3D AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c =3D AW_TIMER_GET_CLASS(s); @@ -329,8 +329,8 @@ static void aw_pit_instance_init(Object *obj) for (i =3D 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } - memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_COMMON_PIT, c->region_size); + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_timer_ops, + s, TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); =20 for (i =3D 0; i < s->timer_count; i++) { @@ -338,7 +338,7 @@ static void aw_pit_instance_init(Object *obj) =20 tc->container =3D s; tc->index =3D i; - s->timer[i].ptimer =3D ptimer_init(a10_pit_timer_cb, tc, + s->timer[i].ptimer =3D ptimer_init(allwinner_ptimer_cb, tc, PTIMER_POLICY_DEFAULT); } } @@ -347,8 +347,8 @@ static void aw_timer_class_init(ObjectClass *klass, voi= d *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - dc->reset =3D a10_pit_reset; - dc->props =3D a10_pit_properties; + dc->reset =3D allwinner_timer_reset; + dc->props =3D allwinner_timer_properties; dc->desc =3D "Allwinner Timer Controller"; dc->vmsd =3D &vmstate_a10_pit; } @@ -356,7 +356,7 @@ static void aw_timer_class_init(ObjectClass *klass, voi= d *data) static const TypeInfo allwinner_pit_info =3D { .name =3D TYPE_AW_COMMON_PIT, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_init =3D aw_pit_instance_init, + .instance_init =3D allwinner_timer_instance_init, .instance_size =3D sizeof(AllwinnerTmrCtrlState), .class_init =3D aw_timer_class_init, .class_size =3D sizeof(AllwinnerTmrCtrlClass), @@ -379,10 +379,10 @@ static const TypeInfo a10_pit_info =3D { .class_init =3D a10_pit_class_init, }; =20 -static void a10_register_types(void) +static void allwinner_timer_register_types(void) { type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } =20 -type_init(a10_register_types); +type_init(allwinner_timer_register_types); --=20 2.21.0