From nobody Tue Feb 10 03:38:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576561942; cv=none; d=zohomail.com; s=zohoarc; b=Qb9uUQwfwikvohn8sdgFg+knJsPYJBy3aiw3BlIKp7BYk2X9TMVvV3u1e/OQaDwn8TV0K66qa/H98/bgSTTHP+EHhlMCnV9geao2mUNT3+I7nHS1IRUdWs6vagzMu/XBU02D/9o+0WiDC/AXaVD5JvPS8pAOeA4DOyQli7JY2ng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576561942; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xK5T83sEeN601FKoU0oS3c1MZKMPDPVsS00+H8l6LiQ=; b=nApyqBmKRX9Y5hmC8G5UwvXbZvhH7Y6Qj2W35gHVdnLbno+chuZDy/xbcovCUKTCkh8L9704w0wfhExjpGCIssd3t3E505ZV9G7fKSAzTN2uvBiEQd7Pb5MfFFsH8fzsO3uOY8nqdoab501L3+IcggXRfas/9ng3HcI/kp40E6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576561942151997.4516816442682; Mon, 16 Dec 2019 21:52:22 -0800 (PST) Received: from localhost ([::1]:36248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5mN-0004F5-TP for importer@patchew.org; Tue, 17 Dec 2019 00:52:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36156) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kn-0003Mk-Kw for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4km-0000wd-7t for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:37 -0500 Received: from ozlabs.org ([203.11.71.1]:39065) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kl-0008WV-SX; Mon, 16 Dec 2019 23:46:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl0k8gz9sTn; Tue, 17 Dec 2019 15:43:44 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=erWSHyC5lwCGEGfTSMrCkh+lwueXLVKO1d9GXDjoZFg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UbLl3kzQV+63G/sw/RVkDN06ZYKPIIMJ2yC5f8Hss5pIffV6kPshKynzPtot83MPM QbU7mMsdZwNE7KIaEYF5VkIbERinOn8u/WqwEiycShmGmQyJi1NKspH4qd+oMi+6ZL vjvbZI+swxf3Nfxq2RrpjHFeD+gV4wOo6f2WjFHw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method Date: Tue, 17 Dec 2019 15:43:16 +1100 Message-Id: <20191217044322.351838-83-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Greg Kurz The pnv_chip_core_realize() function configures the XSCOM MMIO subregion for each core of a single chip. The base address of the subregion depends on the CPU type. Its computation is currently open-code using the pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. Signed-off-by: Greg Kurz Message-Id: <157623841311.360005.4705705734873339545.stgit@bahia.lan> Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 31 ++++++++++++++++++++++++------- include/hw/ppc/pnv.h | 1 + 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 35416d1b3f..16f4e407ee 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -615,6 +615,24 @@ static void pnv_chip_power9_pic_print_info(PnvChip *ch= ip, Monitor *mon) pnv_psi_pic_print_info(&chip9->psi, mon); } =20 +static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV_XSCOM_EX_BASE(core_id); +} + +static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV9_XSCOM_EC_BASE(core_id); +} + +static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV10_XSCOM_EC_BASE(core_id); +} + static bool pnv_match_cpu(const char *default_type, const char *cpu_type) { PowerPCCPUClass *ppc_default =3D @@ -1106,6 +1124,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; + k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; dc->desc =3D "PowerNV Chip POWER8E"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1128,6 +1147,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; + k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; dc->desc =3D "PowerNV Chip POWER8"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1150,6 +1170,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->isa_create =3D pnv_chip_power8nvl_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; + k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; dc->desc =3D "PowerNV Chip POWER8NVL"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1322,6 +1343,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->isa_create =3D pnv_chip_power9_isa_create; k->dt_populate =3D pnv_chip_power9_dt_populate; k->pic_print_info =3D pnv_chip_power9_pic_print_info; + k->xscom_core_base =3D pnv_chip_power9_xscom_core_base; dc->desc =3D "PowerNV Chip POWER9"; =20 device_class_set_parent_realize(dc, pnv_chip_power9_realize, @@ -1403,6 +1425,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) k->isa_create =3D pnv_chip_power10_isa_create; k->dt_populate =3D pnv_chip_power10_dt_populate; k->pic_print_info =3D pnv_chip_power10_pic_print_info; + k->xscom_core_base =3D pnv_chip_power10_xscom_core_base; dc->desc =3D "PowerNV Chip POWER10"; =20 device_class_set_parent_realize(dc, pnv_chip_power10_realize, @@ -1490,13 +1513,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Err= or **errp) &error_fatal); =20 /* Each core has an XSCOM MMIO region */ - if (pnv_chip_is_power10(chip)) { - xscom_core_base =3D PNV10_XSCOM_EC_BASE(core_hwid); - } else if (pnv_chip_is_power9(chip)) { - xscom_core_base =3D PNV9_XSCOM_EC_BASE(core_hwid); - } else { - xscom_core_base =3D PNV_XSCOM_EX_BASE(core_hwid); - } + xscom_core_base =3D pcc->xscom_core_base(chip, core_hwid); =20 pnv_xscom_add_subregion(chip, xscom_core_base, &pnv_core->xscom_regs); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7d2402784d..17ca9a14ac 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -137,6 +137,7 @@ typedef struct PnvChipClass { ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP --=20 2.23.0