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Mon, 16 Dec 2019 19:38:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576525116; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=juymJHEO7Dq1mNyWmoAiZX/S+P7Tk+Bgtm+EHc4pPGI=; b=gifKuGnhMH30NX94jFX7p66guD7/xXxTuq+8hfGaMtx2X9EMwMEZhz+83tlZGxsPVinQvl JaL+h/GaM0wCnol32T7UBIHAslE3NgjCCb6zs7WMlfpGgNyxtKV/q1rWdIcfZ6gYy9Jh11 srGhddXur05E0WB2d09ZNwcSwKRHXG0= From: Eduardo Habkost To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 1/4] i386: Add MSR feature bit for MDS-NO Date: Mon, 16 Dec 2019 16:38:22 -0300 Message-Id: <20191216193825.1794153-2-ehabkost@redhat.com> In-Reply-To: <20191216193825.1794153-1-ehabkost@redhat.com> References: <20191216193825.1794153-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: wstoBMZJMHykNMIz9Hw_IA-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Tao Xu , Xiaoyao Li , Paolo Bonzini , Cathy Zhang , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Cathy Zhang Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow CPU models to report the feature when host supports it. Signed-off-by: Cathy Zhang Reviewed-by: Xiaoyao Li Reviewed-by: Tao Xu Message-Id: <1571729728-23284-2-git-send-email-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cde2a16b94..39d37e1225 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -838,6 +838,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define MSR_ARCH_CAP_RSBA (1U << 2) #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) #define MSR_ARCH_CAP_SSB_NO (1U << 4) +#define MSR_ARCH_CAP_MDS_NO (1U << 5) =20 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) =20 --=20 2.23.0