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Mon, 16 Dec 2019 19:38:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576525116; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=juymJHEO7Dq1mNyWmoAiZX/S+P7Tk+Bgtm+EHc4pPGI=; b=gifKuGnhMH30NX94jFX7p66guD7/xXxTuq+8hfGaMtx2X9EMwMEZhz+83tlZGxsPVinQvl JaL+h/GaM0wCnol32T7UBIHAslE3NgjCCb6zs7WMlfpGgNyxtKV/q1rWdIcfZ6gYy9Jh11 srGhddXur05E0WB2d09ZNwcSwKRHXG0= From: Eduardo Habkost To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 1/4] i386: Add MSR feature bit for MDS-NO Date: Mon, 16 Dec 2019 16:38:22 -0300 Message-Id: <20191216193825.1794153-2-ehabkost@redhat.com> In-Reply-To: <20191216193825.1794153-1-ehabkost@redhat.com> References: <20191216193825.1794153-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: wstoBMZJMHykNMIz9Hw_IA-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Tao Xu , Xiaoyao Li , Paolo Bonzini , Cathy Zhang , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Cathy Zhang Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow CPU models to report the feature when host supports it. Signed-off-by: Cathy Zhang Reviewed-by: Xiaoyao Li Reviewed-by: Tao Xu Message-Id: <1571729728-23284-2-git-send-email-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cde2a16b94..39d37e1225 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -838,6 +838,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define MSR_ARCH_CAP_RSBA (1U << 2) #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) #define MSR_ARCH_CAP_SSB_NO (1U << 4) +#define MSR_ARCH_CAP_MDS_NO (1U << 5) =20 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) =20 --=20 2.23.0 From nobody Thu Nov 13 02:01:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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bh=awU1QKKLg8eVSkA+topw8q8tnD6Jtyr7XMVPpT/Xrko=; b=Z+v51UkygdEBrRX1N+CI7SOGQXBMXTHvUStxvzI2pufEssNnwW393z4zVR0aoEPO0f3T/m ALDi44ogTBGqgdgDGSzdN3Gkw/QH0yKtSY6WvKJbmIIPh61rjlJY/AVPsCFHDImaIBZW7b mhFc6AzOPY5OLl8DJ9/jVXE8agbbVwI= From: Eduardo Habkost To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 2/4] i386: Add macro for stibp Date: Mon, 16 Dec 2019 16:38:23 -0300 Message-Id: <20191216193825.1794153-3-ehabkost@redhat.com> In-Reply-To: <20191216193825.1794153-1-ehabkost@redhat.com> References: <20191216193825.1794153-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: c1Jg1C6GPEiU7cjvA-ILWQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Tao Xu , Xiaoyao Li , Paolo Bonzini , Cathy Zhang , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Cathy Zhang stibp feature is already added through the following commit. https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955 Add a macro for it to allow CPU models to report it when host supports. Signed-off-by: Cathy Zhang Reviewed-by: Xiaoyao Li Reviewed-by: Tao Xu Message-Id: <1571729728-23284-3-git-send-email-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 39d37e1225..af282936a7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -771,6 +771,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) +/* Single Thread Indirect Branch Predictors */ +#define CPUID_7_0_EDX_STIBP (1U << 27) /* Arch Capabilities */ #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /* Core Capability */ --=20 2.23.0 From nobody Thu Nov 13 02:01:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 16 Dec 2019 14:38:47 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-156-0_lBxl_mO8qdHLITsvVw3A-1; Mon, 16 Dec 2019 14:38:45 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 34C1D1809A2A; Mon, 16 Dec 2019 19:38:44 +0000 (UTC) Received: from localhost (ovpn-116-90.gru2.redhat.com [10.97.116.90]) by smtp.corp.redhat.com (Postfix) with ESMTP id B4D7660BE0; Mon, 16 Dec 2019 19:38:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576525126; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2KRVlkTwCbvvliHtCmwT53Exi2SBrUN96CRyUUn3RCs=; b=FMWOWhts3tsVJww+G3h/p8S/OKcklk1fhDBMjv1cKLoOZjua8/Qxlht0WbtsCBGb8Gfrvr NjiXfuNEWVORz4Jp8j1qXblIHYyopuK7nRlLhCvYsgV5dYd2fcISfSkz0fDxQrYWnaOEqC v9Hjnyz9Gi0j1Zh/0BUpUjKyf3TGIig= From: Eduardo Habkost To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 3/4] i386: Add new CPU model Cooperlake Date: Mon, 16 Dec 2019 16:38:24 -0300 Message-Id: <20191216193825.1794153-4-ehabkost@redhat.com> In-Reply-To: <20191216193825.1794153-1-ehabkost@redhat.com> References: <20191216193825.1794153-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 0_lBxl_mO8qdHLITsvVw3A-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Tao Xu , Xiaoyao Li , Bruce Rogers , Paolo Bonzini , Cathy Zhang , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Cathy Zhang Cooper Lake is intel's successor to Cascade Lake, the new CPU model inherits features from Cascadelake-Server, while add one platform associated new feature: AVX512_BF16. Meanwhile, add STIBP for speculative execution. Signed-off-by: Cathy Zhang Reviewed-by: Xiaoyao Li Reviewed-by: Tao Xu Message-Id: <1571729728-23284-4-git-send-email-cathy.zhang@intel.com> Reviewed-by: Bruce Rogers Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69f518a21a..de828e29d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3159,6 +3159,66 @@ static X86CPUDefinition builtin_x86_defs[] =3D { { /* end of list */ } } }, + { + .name =3D "Cooperlake", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 85, + .stepping =3D 10, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_PKU | + CPUID_7_0_ECX_AVX512VNNI, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | + CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, + .features[FEAT_ARCH_CAPABILITIES] =3D + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO, + .features[FEAT_7_1_EAX] =3D + CPUID_7_1_EAX_AVX512_BF16, + /* + * Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon Processor (Cooperlake)", + }, { .name =3D "Icelake-Client", .level =3D 0xd, --=20 2.23.0 From nobody Thu Nov 13 02:01:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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bh=mqy5KY9RhCMejzmBW4QX+G2laitf5m3Gxcgdjfc/Kcg=; b=RGo+E0MP9HYbl2WjWHN0z4JvomCcQL5ie82LGM9G3v5xzM+iqbHUMJ2/RyMYGNz05aKjTv xAu/p4Cnta3CoN0aNAV2jNiu08b2yYIiYVStKSFksSYpH9sir7V4KNsJTqqY7pcZsox7mo 1cdfQIi0fY7ZncrPmZuujz9cinGdcGs= From: Eduardo Habkost To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 4/4] i386: Use g_autofree in a few places Date: Mon, 16 Dec 2019 16:38:25 -0300 Message-Id: <20191216193825.1794153-5-ehabkost@redhat.com> In-Reply-To: <20191216193825.1794153-1-ehabkost@redhat.com> References: <20191216193825.1794153-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: DekmTOiDM8GEkQqOPHhvkw-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Stefano Garzarella , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Get rid of 12 explicit g_free() calls. Signed-off-by: Eduardo Habkost Message-Id: <20191025025632.5928-1-ehabkost@redhat.com> Reviewed-by: Stefano Garzarella Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 41 +++++++++++++---------------------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index de828e29d8..0a9ac65974 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1671,11 +1671,8 @@ static char *x86_cpu_type_name(const char *model_nam= e) =20 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) { - ObjectClass *oc; - char *typename =3D x86_cpu_type_name(cpu_model); - oc =3D object_class_by_name(typename); - g_free(typename); - return oc; + g_autofree char *typename =3D x86_cpu_type_name(cpu_model); + return object_class_by_name(typename); } =20 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) @@ -4226,7 +4223,6 @@ static void mark_unavailable_features(X86CPU *cpu, Fe= atureWord w, uint64_t mask, CPUX86State *env =3D &cpu->env; FeatureWordInfo *f =3D &feature_word_info[w]; int i; - char *feat_word_str; =20 if (!cpu->force_features) { env->features[w] &=3D ~mask; @@ -4239,13 +4235,12 @@ static void mark_unavailable_features(X86CPU *cpu, = FeatureWord w, uint64_t mask, =20 for (i =3D 0; i < 64; ++i) { if ((1ULL << i) & mask) { - feat_word_str =3D feature_word_description(f, i); + g_autofree char *feat_word_str =3D feature_word_description(f,= i); warn_report("%s: %s%s%s [bit %d]", verbose_prefix, feat_word_str, f->feat_names[i] ? "." : "", f->feat_names[i] ? f->feat_names[i] : "", i); - g_free(feat_word_str); } } } @@ -4747,17 +4742,14 @@ static gint x86_cpu_list_compare(gconstpointer a, g= constpointer b) ObjectClass *class_b =3D (ObjectClass *)b; X86CPUClass *cc_a =3D X86_CPU_CLASS(class_a); X86CPUClass *cc_b =3D X86_CPU_CLASS(class_b); - char *name_a, *name_b; int ret; =20 if (cc_a->ordering !=3D cc_b->ordering) { ret =3D cc_a->ordering - cc_b->ordering; } else { - name_a =3D x86_cpu_class_get_model_name(cc_a); - name_b =3D x86_cpu_class_get_model_name(cc_b); + g_autofree char *name_a =3D x86_cpu_class_get_model_name(cc_a); + g_autofree char *name_b =3D x86_cpu_class_get_model_name(cc_b); ret =3D strcmp(name_a, name_b); - g_free(name_a); - g_free(name_b); } return ret; } @@ -4795,9 +4787,9 @@ static void x86_cpu_list_entry(gpointer data, gpointe= r user_data) { ObjectClass *oc =3D data; X86CPUClass *cc =3D X86_CPU_CLASS(oc); - char *name =3D x86_cpu_class_get_model_name(cc); - char *desc =3D g_strdup(cc->model_description); - char *alias_of =3D x86_cpu_class_get_alias_of(cc); + g_autofree char *name =3D x86_cpu_class_get_model_name(cc); + g_autofree char *desc =3D g_strdup(cc->model_description); + g_autofree char *alias_of =3D x86_cpu_class_get_alias_of(cc); =20 if (!desc && alias_of) { if (cc->model && cc->model->version =3D=3D CPU_VERSION_AUTO) { @@ -4811,9 +4803,6 @@ static void x86_cpu_list_entry(gpointer data, gpointe= r user_data) } =20 qemu_printf("x86 %-20s %-48s\n", name, desc); - g_free(name); - g_free(desc); - g_free(alias_of); } =20 /* list available CPU models and flags */ @@ -5252,7 +5241,7 @@ static void x86_cpu_cpudef_class_init(ObjectClass *oc= , void *data) =20 static void x86_register_cpu_model_type(const char *name, X86CPUModel *mod= el) { - char *typename =3D x86_cpu_type_name(name); + g_autofree char *typename =3D x86_cpu_type_name(name); TypeInfo ti =3D { .name =3D typename, .parent =3D TYPE_X86_CPU, @@ -5261,14 +5250,12 @@ static void x86_register_cpu_model_type(const char = *name, X86CPUModel *model) }; =20 type_register(&ti); - g_free(typename); } =20 static void x86_register_cpudef_types(X86CPUDefinition *def) { X86CPUModel *m; const X86CPUVersionDefinition *vdef; - char *name; =20 /* AMD aliases are handled at runtime based on CPUID vendor, so * they shouldn't be set on the CPU model table. @@ -5288,11 +5275,11 @@ static void x86_register_cpudef_types(X86CPUDefinit= ion *def) =20 for (vdef =3D x86_cpu_def_get_versions(def); vdef->version; vdef++) { X86CPUModel *m =3D g_new0(X86CPUModel, 1); + g_autofree char *name =3D + x86_cpu_versioned_model_name(def, vdef->version); m->cpudef =3D def; m->version =3D vdef->version; - name =3D x86_cpu_versioned_model_name(def, vdef->version); x86_register_cpu_model_type(name, m); - g_free(name); =20 if (vdef->alias) { X86CPUModel *am =3D g_new0(X86CPUModel, 1); @@ -6364,9 +6351,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) =20 if (xcc->host_cpuid_required) { if (!accel_uses_host_cpuid()) { - char *name =3D x86_cpu_class_get_model_name(xcc); + g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); error_setg(&local_err, "CPU model '%s' requires KVM", name); - g_free(name); goto out; } =20 @@ -6482,10 +6468,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) /* Cache information initialization */ if (!cpu->legacy_cache) { if (!xcc->model || !xcc->model->cpudef->cache_info) { - char *name =3D x86_cpu_class_get_model_name(xcc); + g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); error_setg(errp, "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); - g_free(name); return; } env->cache_info_cpuid2 =3D env->cache_info_cpuid4 =3D env->cache_i= nfo_amd =3D --=20 2.23.0