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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KOuvuhSQj8eVtemKGzERysHw3TTzF7KdECnJyVpBO44=; b=L9UomrsiCIUENvz8DMMGlb1kRhNSSAIyCIk9XqREeCcPypLv628qQ9gUDMFDBBS8d7 KZ28E9uSTcOwn9mJgXx3yRdCA7pKZw9z5CJEDHfX6CLb0NTm/jP7/z7tTHuai8q0mbwW 6vqJrN9kkQB4PxbZ7pkNODoQ1WfnmZ+geYlOTn553PCmjGz//RXh5+zeR/JM0s3uADEv PATZzkuQDImdJKqdBkj5x+8eSv8T/n6QLBjcWnghWNLJhRQ0yabESoiDeuhq62Cas0tY rEvdQ2p7maLkG8imKLYVmwreW2BkODmbDCm20u73Jf5syOqG5SZutn5WSn1X+AgikPYg GKsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KOuvuhSQj8eVtemKGzERysHw3TTzF7KdECnJyVpBO44=; b=OfJL0kxm6nie43FITB/Xtpnl/mxpkH9uB+CqNFsp4i9FBB/LScuV+VDP+T6fRjjPJA fsXYdsJBMwwGer0AW3I6qP+Aymi61X9nEETBi0+DZX3pb1uneXyy61rWLQ68jqMPtZAY SlxNjg6Ja9SHEskhg0gOiVgylxDJCM695ppkyjQ0wWhT4uQw90Y/l61iLm3ssxZIjZRk q63K0Cx7ozWqAmT0bMSlbyzcFtQ759GQPepptxPVtNBkS5qesfcp3tlCNBNmncVeetWQ 3BuiU8Fy2WQM0Z35cxzqs1Ev0DcSlfQaBGygLynlUFvh3NoQcSxciN884ly3sEqheSUF NDjw== X-Gm-Message-State: APjAAAUP2JDQOP/oOuRUR+vtMu3CZVP7fMSuE5L87GFE+qe/oirW+cUx ypG25S/hpq7Beb8Ts5DP53U8ceBFr69oyw== X-Google-Smtp-Source: APXvYqylEoh8JbyhwbHouBrj5it3Z1rJA4SLQMlnLHslhust0lAauhOkqGuooNkFvxM0JLvXJSQNVw== X-Received: by 2002:adf:f80c:: with SMTP id s12mr29310022wrp.1.1576494573226; Mon, 16 Dec 2019 03:09:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/34] target/arm: Add support for missing Jazelle system registers Date: Mon, 16 Dec 2019 11:08:54 +0000 Message-Id: <20191216110904.30815-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Marc Zyngier QEMU lacks the minimum Jazelle implementation that is required by the architecture (everything is RAZ or RAZ/WI). Add it together with the HCR_EL2.TID0 trapping that goes with it. Signed-off-by: Marc Zyngier Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 20191201122018.25808-6-maz@kernel.org [PMM: moved ARMCPRegInfo array to file scope, marked it 'static global', moved new condition down in register_cp_regs_for_features() to go with other feature things rather than up with the v6/v7/v8 stuff] Signed-off-by: Peter Maydell --- target/arm/helper.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ba08d550aa..a4f7b61b4e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6040,6 +6040,30 @@ static CPAccessResult access_aa32_tid3(CPUARMState *= env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID0))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo jazelle_regs[] =3D { + { .name =3D "JIDR", + .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_jazelle, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "JOSCR", + .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "JMCR", + .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6699,6 +6723,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } + if (cpu_isar_feature(jazelle, cpu)) { + define_arm_cp_regs(cpu, jazelle_regs); + } /* Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld * be read-only (ie write causes UNDEF exception). --=20 2.20.1