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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YMTEMJh/emKVxwbHbtHlnAEduqLFBKcxuqgnspTaEPo=; b=hY+zSFhon4ZaEkZild+FK7ostL8Qbx+iMZpglJVYtq2zuCIjGuu5VyDD9fWONGXsQi dkbAdLGYjjQO5VeSPy40oORjyRLZZjhGgs7apCUv4TuhWqkKAPeI1+vbIR5K94yg3Be9 eUYb2qcZ6sF+ltSD+dWmOopZFcCoVb6ULsN/FbGhAPLB2eXz95OTMHmKxn2R0lTd4pnu uZOPSxD/MD9mtJD4dfuaG+jhnpxabztOWupemdkr6+rfAcs9SERu7KRpKD+cADdnti+t cPNY2JKh8pOtHYr/kySFtWtHn+/TvGnDtwBiicHxj6V+kvKpZopYf+L35oawIOm5XJLm Q6TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YMTEMJh/emKVxwbHbtHlnAEduqLFBKcxuqgnspTaEPo=; b=EFktFZuI8/P3Owp1iVmQGeV+IxCdoH5uzb4bINhbgXqKaCJOCWZdX9Dr/kRgMYCxWN iK8/7ccUX7e6cvlY2KCXNb2xnEzbgvBVKfi2DfeyYW301UL2yL6RajmW7DvcgCu42StW upbYtC97itq81KAyxeVZ1IQfDoFrj4jjv57KA0TW9Z4x5aLa2PStEVm5fLkXAYMlWmi4 shmui3704w/s7l4tHwCWlf2uO8sxyj2EsnWveWolf51GI5OvzGa1ZxuPjTEdzBzianK0 kOhNAKlGuhI2PJ1Wn1+jeuYajj8Kf/jSZLiGcCjG5WZ6Dsdb6Tm9JO7Dr9TOi2j9GauR p1nA== X-Gm-Message-State: APjAAAVGlRrt7yWJ/od+pJH0E3PqHWI8zwHSk0yvi26AfMNz2HqoXYTo VT7sr1r9elaJxbqo6Wnju7JWHLVIrPlWuA== X-Google-Smtp-Source: APXvYqwBWbiuFRE4U4nFWbd61CsWHFQguruHt4PUcEF+OZJi320svn0rOGGp5hP5XR73hx2ndRApdQ== X-Received: by 2002:a5d:65c5:: with SMTP id e5mr29450377wrw.311.1576494548852; Mon, 16 Dec 2019 03:09:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/34] target/arm: Add support for cortex-m7 CPU Date: Mon, 16 Dec 2019 11:08:31 +0000 Message-Id: <20191216110904.30815-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Christophe Lyon This is derived from cortex-m4 description, adding DP support and FPv5 instructions with the corresponding flags in isar and mvfr2. Checked that it could successfully execute vrinta.f32 s15, s15 while cortex-m4 emulation rejects it with "illegal instruction". Signed-off-by: Christophe Lyon Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-id: 20191025090841.10299-1-christophe.lyon@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf..dd51adac059 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1975,6 +1975,37 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.id_isar6 =3D 0x00000000; } =20 +static void cortex_m7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr =3D 0x411fc272; /* r1p2 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x00100030; + cpu->id_mmfr1 =3D 0x00000000; + cpu->id_mmfr2 =3D 0x01000000; + cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02112000; + cpu->isar.id_isar2 =3D 0x20232231; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2559,6 +2590,8 @@ static const ARMCPUInfo arm_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, + .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, --=20 2.20.1