From nobody Sun Apr 28 07:43:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576181043; cv=none; d=zohomail.com; s=zohoarc; b=iHgYeJuCSrkZwcDBtFRBTrVyHxKvF4ob7ry2+6syiVH6dh6f0p2WfbdmQnxtk8eM/hMqRVUg6uZ03pD2FfIvNDTbV7+MatjuOqaT1wr7dca52O+ES2c5TDfxUQcM55JJrzmwPuzZ1TL4sbz05KN0UtK6dcN6JkBcp3KOW+5IBfo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576181043; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eJu/bXuvlNsqHu84ADHlrIPch5OHryfxz478Tn38gYU=; b=U5cK23zk8rnx3ZIHp4GBWktehUQ2xFceFNPTMnQKOPNoLHEy2eS54B9rpJEI8vBMX8A8LmZ1Fv0adVH9r19GZWMYgcPGvCvhlJWyn0NNwgPEASjCf5Qb7ECiMhmyt6f26CJ69l/t9sSt//vcZFuKBpVS89B46JL3jboSGs+I6RU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15761810434690.5958587195932523; Thu, 12 Dec 2019 12:04:03 -0800 (PST) Received: from localhost ([::1]:36822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifUgr-0007ey-SE for importer@patchew.org; Thu, 12 Dec 2019 15:04:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47496) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifUel-0005x8-MN for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifUej-0004Br-Os for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:51 -0500 Received: from mout.kundenserver.de ([212.227.17.13]:40711) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifUeh-00044p-RP for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:49 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MwxNF-1hm89L2hHX-00yMRo; Thu, 12 Dec 2019 21:01:44 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PATCH 1/3] q800: fix ESCC base Date: Thu, 12 Dec 2019 21:01:40 +0100 Message-Id: <20191212200142.15688-2-laurent@vivier.eu> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191212200142.15688-1-laurent@vivier.eu> References: <20191212200142.15688-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:KwNe+eUQl1Ww4Y0vvfXrqZjcejk0ju1XGmCAc2nJz1TxqZBDdej kExVBOPe/LBQVy//d681qJLph6cM6WcCz7Z6I39PlvxAu+unV8C77ERhhHvn8ArgR663z2G UjKwvJn991dER5x2ILqCZnJpZL+k6neK/Gsm5Nf7PY7ggUKZXJaQM2AA0HTU9zXcwt8g472 vy6HbnDCszPYrRdpIY/zA== X-UI-Out-Filterresults: notjunk:1;V03:K0:+lGyNolFVvI=:ZkdVY8BgyL1qxWI3zL6ay8 53aG7ReD2yYXYfAS1qpjMUHATXaF64MmEBC79YvsJGVTJT+zG4QtHIRW6rpRZHHcYMxY3CLlQ QsCEmnaGXiNPCBfzE13FA+LrIwfZrBYq9r0yTlvHhvAtlfKDMXWF19a+Sgj27CIJCUthzZqIL iH2PzeVIDvkekpsS0Lqgjf9kV/iYe4tUgNPvjNKXXUoAw5tgV2935CNFQ3Mas7Y5PVxiswqzp AVQCtXY93Pj6V5/tO4javoJglqMTivzwyk5zRgTq4x/N6/tq2J/Te7pAAxtDvOeu9+AmAsnq7 E0NM6O+xqVfrWiFk83IHfFbH60gAagcm05y/Wk0rKdOrB2n2HKB7xN0OceQ62N5gLayGkeRI3 fb2mH8KM3bSza3vqby+wyKoT8K+Xbui6JLnuIT5c7uTBiJEfsU86782D1pml7m+4w66FNzjw1 yeY2xf4Xr2s+2Wquo7DoWz2xk8kBzqbHiK5nLJnPKesAqFZzPq693bhnIBDoze2XZvyN5rDvB 9zlHng8T1QaQRrLO4G5YfFiE2g52KMekz4Gmyow8M60gruMK2BNx7q4d4rZI8wvk9LLh05lkN GEWbas+hi++MbcutjrvCTW6L+WBaeR7ev0e9l6eccXf4lxbP3mq4d9RBSm6krr111kbWNGgPZ vMA4HE++gbqyiBBQfsxwn4/RjZfxVa9nLViy42nj+5g+JxZfjYhUhYFj+SgUvpct4kESmAxph yZDiehYa8Iwu9IRenmkZmyo90zEYbbfJvohOQElvCUBJ56QxFGCk8DtyfLtbESJolLvo60uXo N4HFL2rCWUueqg/Kpc+EyWZQ0VOa+yyMWGjsngwZH8D2e7GMmdTd41UUVVjfmTeq//51hSn5b zrhqWXuhxBrgTuQcImDg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.13 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" 0xc020 is for Q900/Q950, Q800 uses 0xc000. This value was provided to the kernel, this explains why it was working even with wrong value Signed-off-by: Laurent Vivier --- hw/m68k/q800.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 4ca8678007..ef0014f4c4 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -67,7 +67,7 @@ #define VIA_BASE (IO_BASE + 0x00000) #define SONIC_PROM_BASE (IO_BASE + 0x08000) #define SONIC_BASE (IO_BASE + 0x0a000) -#define SCC_BASE (IO_BASE + 0x0c020) +#define SCC_BASE (IO_BASE + 0x0c000) #define ESP_BASE (IO_BASE + 0x10000) #define ESP_PDMA (IO_BASE + 0x10100) #define ASC_BASE (IO_BASE + 0x14000) --=20 2.23.0 From nobody Sun Apr 28 07:43:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 12 Dec 2019 12:07:20 -0800 (PST) Received: from localhost ([::1]:36870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifUk3-00037K-GD for importer@patchew.org; Thu, 12 Dec 2019 15:07:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47607) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifUem-0005xd-6C for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifUej-0004C1-Ov for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:52 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:33977) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifUeh-00045b-RO for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:49 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1Mjjvp-1hzJP148uR-00lHYy; Thu, 12 Dec 2019 21:01:45 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PATCH 2/3] q800: add djMEMC memory controller Date: Thu, 12 Dec 2019 21:01:41 +0100 Message-Id: <20191212200142.15688-3-laurent@vivier.eu> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191212200142.15688-1-laurent@vivier.eu> References: <20191212200142.15688-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:rckPsMuIz66NrzkoGOeVBgBKKre9v7jjAxMUDx4vy58yXOsC4pj a1prVZuKn1doRN26ToyAcBu9Mh1LBYavGahTngLzdby49qda3eur+uG86N61tca3ia3eQ/7 KUPnh9h7Ep1eTrVSp0AUtmGoW1FtUw5NBFsMLuvoTvJkR0o4krPOlHTcFAQnHlZ2rmyVpSY EBjpbKQfSG2q3jabOuRjQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:1zpE9NDVjrQ=:YbpRoA0XRMPDyanNacOYHJ jNRR1CD4zubZmo22DXsNhE4Z5mTNecZjOKTz5RjjsqtKufGir4QDHNyUIx7RZJBjUb3dmfyAT Uk2S+U3LeQO3QQ+9u5unXf/DKwhicj/G21lx1FewkjKNXX75jss/1E4ubtVHvHbJ+Sdu/SHSm H1VgcsAEuOid+Pl/X78OVEwzqiS7Y+OCizuzpXPvUMf15wkPV1q4XjB9qh9VX+5qKqIEbWM8f BnPht5ssPPKcqPYJqVZpGu+n5JmQLGvxr998uvPZuQ/4cqqqV+txxz77lDRQpNrRZaPfQqifi oPkEyDY63Z41Iz1AmLf3tj2IVEjSDrqUUupjdCfgJ4f3qXoQ1rciokO1gVRyebovoqMZKbo0P okjjpo5Xvn7oPKQf1BCUkFUBLfaGtIo+px/DoHgame6LNI9GZEnwmeys1cobdIizgfAofGLk+ iQQXWTmIKcDY7Ln2QITTvUjTFOL8pLdaao2FPMKhfS9WQ7J6/WDxHGQIC4wuih6OzsqL+a5wA vk2UcD44Lhu9CAvVXfnEZF7YCzw7wcEmA3Vc6YqPVs8yzV8ApLPUlOqpCnRgRmTyAT63vxTSN Qybq4hLqx/1BfMwuD0RW7EbIyn34EUKLxnUS7h9v+4tpNqUcb0jJqlVBg8zro5KoIILwc+EHX MW03QJjFL5IaLepLRB4V3hzefto2Ep1gcQJI1oIUHtN0zeBEKKCmfFZSrMGA/RJN4c34LmC0R 2t/UCHSpzAEtqNqH/OFSxrbulN+gZpJD66tmykgr/ACXs4Ep9OfOB+NdTVSPQ8ZPauldWma6d KrxAPWReJaRmcEWOwOUB5Kh5KIGua1lDSX0ehU+mTc+lElVZdRhRMOzfAQHbdTNh9+Uk4yGdZ 5UeCwzq6R5f0OoBL7GmA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.72.192.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Current implementation is based on GLUE, an early implementation of the memory controller found in Macintosh II series. Quadra 800 uses in fact djMEMC: The djMEMC is an Apple custom integrated circuit chip that performs a variety of functions (RAM management, clock generation, ...). It receives interrupt requests from various devices, assign priority to each, and asserts one or more interrupt line to the CPU. Signed-off-by: Laurent Vivier --- MAINTAINERS | 2 + hw/m68k/Kconfig | 1 + hw/m68k/q800.c | 61 ++++---------- hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/djmemc.c | 176 +++++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 4 + include/hw/misc/djmemc.h | 34 ++++++++ 8 files changed, 237 insertions(+), 45 deletions(-) create mode 100644 hw/misc/djmemc.c create mode 100644 include/hw/misc/djmemc.h diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..07224a2fa2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -925,11 +925,13 @@ F: hw/misc/mac_via.c F: hw/nubus/* F: hw/display/macfb.c F: hw/block/swim.c +F: hw/misc/djmemc.c F: hw/m68k/bootinfo.h F: include/hw/misc/mac_via.h F: include/hw/nubus/* F: include/hw/display/macfb.h F: include/hw/block/swim.h +F: include/hw/misc/djmemc.c =20 MicroBlaze Machines ------------------- diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index c757e7dfa4..bdc43a798a 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -22,3 +22,4 @@ config Q800 select ESCC select ESP select DP8393X + select DJMEMC diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index ef0014f4c4..9ee0cb1141 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -46,6 +46,7 @@ #include "sysemu/qtest.h" #include "sysemu/runstate.h" #include "sysemu/reset.h" +#include "hw/misc/djmemc.h" =20 #define MACROM_ADDR 0x40000000 #define MACROM_SIZE 0x00100000 @@ -68,6 +69,7 @@ #define SONIC_PROM_BASE (IO_BASE + 0x08000) #define SONIC_BASE (IO_BASE + 0x0a000) #define SCC_BASE (IO_BASE + 0x0c000) +#define DJMEMC_BASE (IO_BASE + 0x0e000) #define ESP_BASE (IO_BASE + 0x10000) #define ESP_PDMA (IO_BASE + 0x10100) #define ASC_BASE (IO_BASE + 0x14000) @@ -85,39 +87,6 @@ =20 #define MAC_CLOCK 3686418 =20 -/* - * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip - * that performs a variety of functions (RAM management, clock generation,= ...). - * The GLUE chip receives interrupt requests from various devices, - * assign priority to each, and asserts one or more interrupt line to the - * CPU. - */ - -typedef struct { - M68kCPU *cpu; - uint8_t ipr; -} GLUEState; - -static void GLUE_set_irq(void *opaque, int irq, int level) -{ - GLUEState *s =3D opaque; - int i; - - if (level) { - s->ipr |=3D 1 << irq; - } else { - s->ipr &=3D ~(1 << irq); - } - - for (i =3D 7; i >=3D 0; i--) { - if ((s->ipr >> i) & 1) { - m68k_set_irq_level(s->cpu, i + 1, i + 25); - return; - } - } - m68k_set_irq_level(s->cpu, 0, 0); -} - static void main_cpu_reset(void *opaque) { M68kCPU *cpu =3D opaque; @@ -149,6 +118,7 @@ static void q800_init(MachineState *machine) const char *kernel_cmdline =3D machine->kernel_cmdline; hwaddr parameters_base; CPUState *cs; + DeviceState *djmemc_dev; DeviceState *dev; DeviceState *via_dev; SysBusESPState *sysbus_esp; @@ -156,8 +126,6 @@ static void q800_init(MachineState *machine) SysBusDevice *sysbus; BusState *adb_bus; NubusBus *nubus; - GLUEState *irq; - qemu_irq *pic; =20 linux_boot =3D (kernel_filename !=3D NULL); =20 @@ -191,11 +159,13 @@ static void q800_init(MachineState *machine) g_free(name); } =20 - /* IRQ Glue */ + /* djMEMC memory and interrupt controller */ =20 - irq =3D g_new0(GLUEState, 1); - irq->cpu =3D cpu; - pic =3D qemu_allocate_irqs(GLUE_set_irq, irq, 8); + djmemc_dev =3D qdev_create(NULL, TYPE_DJMEMC); + object_property_set_link(OBJECT(djmemc_dev), OBJECT(cpu), "cpu", + &error_abort); + qdev_init_nofail(djmemc_dev); + sysbus_mmio_map(SYS_BUS_DEVICE(djmemc_dev), 0, DJMEMC_BASE); =20 /* VIA */ =20 @@ -203,9 +173,10 @@ static void q800_init(MachineState *machine) qdev_init_nofail(via_dev); sysbus =3D SYS_BUS_DEVICE(via_dev); sysbus_mmio_map(sysbus, 0, VIA_BASE); - qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]); - qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]); - + qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, + qdev_get_gpio_in(djmemc_dev, 0)); + qdev_connect_gpio_out_named(DEVICE(sysbus), + "irq", 1, qdev_get_gpio_in(djmemc_dev, 1)); =20 adb_bus =3D qdev_get_child_bus(via_dev, "adb.0"); dev =3D qdev_create(adb_bus, TYPE_ADB_KEYBOARD); @@ -244,7 +215,7 @@ static void q800_init(MachineState *machine) sysbus =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(sysbus, 0, SONIC_BASE); sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); - sysbus_connect_irq(sysbus, 0, pic[2]); + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(djmemc_dev, 2)); =20 /* SCC */ =20 @@ -259,8 +230,8 @@ static void q800_init(MachineState *machine) qdev_prop_set_uint32(dev, "chnAtype", 0); qdev_init_nofail(dev); sysbus =3D SYS_BUS_DEVICE(dev); - sysbus_connect_irq(sysbus, 0, pic[3]); - sysbus_connect_irq(sysbus, 1, pic[3]); + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(djmemc_dev, 3)); + sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(djmemc_dev, 3)); sysbus_mmio_map(sysbus, 0, SCC_BASE); =20 /* SCSI */ diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 2164646553..4c68d20c18 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -125,4 +125,7 @@ config MAC_VIA select MOS6522 select ADB =20 +config DJMEMC + bool + source macio/Kconfig diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..598e46d7db 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -20,6 +20,7 @@ common-obj-$(CONFIG_ARM11SCU) +=3D arm11scu.o =20 # Mac devices common-obj-$(CONFIG_MOS6522) +=3D mos6522.o +obj-$(CONFIG_DJMEMC) +=3D djmemc.o =20 # PKUnity SoC devices common-obj-$(CONFIG_PUV3) +=3D puv3_pm.o diff --git a/hw/misc/djmemc.c b/hw/misc/djmemc.c new file mode 100644 index 0000000000..b494e82a60 --- /dev/null +++ b/hw/misc/djmemc.c @@ -0,0 +1,176 @@ +/* + * djMEMC, macintosh memory and interrupt controller + * (Quadra 610/650/800 & Centris 610/650) + * + * https://mac68k.info/wiki/display/mac68k/djMEMC+Information + * + * The djMEMC is an Apple custom integrated circuit chip that performs a + * variety of functions (RAM management, clock generation, ...). + * It receives interrupt requests from various devices, assign priority to + * each, and asserts one or more interrupt line to the CPU. + */ + +#include "qemu/osdep.h" +#include "migration/vmstate.h" +#include "hw/misc/djmemc.h" +#include "hw/qdev-properties.h" +#include "trace.h" + +#define DJMEMC_SIZE 0x2000 + +#define InterleaveConf 0 +#define Bank0Conf 1 +#define Bank1Conf 2 +#define Bank2Conf 3 +#define Bank3Conf 4 +#define Bank4Conf 5 +#define Bank5Conf 6 +#define Bank6Conf 7 +#define Bank7Conf 8 +#define Bank8Conf 9 +#define Bank9Conf 10 +#define MemTop 11 +#define Config 12 +#define Refresh 13 + +static const VMStateDescription vmstate_djMEMC =3D { + .name =3D "djMEMC", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(interleave, DjMEMCState), + VMSTATE_UINT32_ARRAY(bank, DjMEMCState, DjMEMCMaxBanks), + VMSTATE_UINT32(top, DjMEMCState), + VMSTATE_UINT32(config, DjMEMCState), + VMSTATE_UINT32(refresh_rate, DjMEMCState), + VMSTATE_END_OF_LIST() + } +}; + +static uint64_t djMEMC_read(void *opaque, hwaddr addr, + unsigned size) +{ + DjMEMCState *s =3D opaque; + uint64_t value =3D 0; + + switch (addr >> 2) { + case InterleaveConf: + value =3D s->interleave; + case Bank0Conf...Bank9Conf: + value =3D s->bank[(addr >> 2) - Bank0Conf]; + case MemTop: + value =3D s->top; + case Config: + value =3D s->config; + case Refresh: + value =3D s->refresh_rate; + } + trace_djMEMC_read((int)(addr >> 2), size, value); + + return value; +} + +static void djMEMC_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + DjMEMCState *s =3D opaque; + trace_djMEMC_write((int)(addr >> 2), size, value); + + switch (addr >> 2) { + case InterleaveConf: + s->interleave =3D value; + case Bank0Conf...Bank9Conf: + s->bank[(addr >> 2) - Bank0Conf] =3D value; + case MemTop: + s->top =3D value; + case Config: + s->config =3D value; + case Refresh: + s->refresh_rate =3D value; + } +} + +static const MemoryRegionOps djMEMC_mmio_ops =3D { + .read =3D djMEMC_read, + .write =3D djMEMC_write, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void djMEMC_set_irq(void *opaque, int irq, int level) +{ + DjMEMCState *s =3D opaque; + int i; + + + if (level) { + s->ipr |=3D 1 << irq; + } else { + s->ipr &=3D ~(1 << irq); + } + + for (i =3D 7; i >=3D 0; i--) { + if ((s->ipr >> i) & 1) { + m68k_set_irq_level(s->cpu, i + 1, i + 25); + return; + } + } + m68k_set_irq_level(s->cpu, 0, 0); +} + +static void djMEMC_init(Object *obj) +{ + DjMEMCState *s =3D DJMEMC(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mem_regs, NULL, &djMEMC_mmio_ops, s, "djMEMC= ", + DJMEMC_SIZE); + sysbus_init_mmio(sbd, &s->mem_regs); + + qdev_init_gpio_in(DEVICE(obj), djMEMC_set_irq, 8); + object_property_add_link(obj, "cpu", TYPE_M68K_CPU, + (Object **) &s->cpu, + qdev_prop_allow_set_link_before_realize, + 0, NULL); +} + +static void djMEMC_reset(DeviceState *d) +{ + DjMEMCState *s =3D DJMEMC(d); + int i; + + s->interleave =3D 0; + s->top =3D 0; + s->refresh_rate =3D 0; + s->config =3D 0; + + for (i =3D 0; i < DjMEMCMaxBanks; i++) { + s->bank[i] =3D 0; + } +} + +static void djMEMC_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->reset =3D djMEMC_reset; + dc->vmsd =3D &vmstate_djMEMC; +} + +static TypeInfo djMEMC_info =3D { + .name =3D TYPE_DJMEMC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DjMEMCState), + .instance_init =3D djMEMC_init, + .class_init =3D djMEMC_class_init, +}; + +static void djMEMC_register_types(void) +{ + type_register_static(&djMEMC_info); +} + +type_init(djMEMC_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1deb1d08c1..c9bcdd4a54 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -149,3 +149,7 @@ bcm2835_mbox_write(unsigned int size, uint64_t addr, ui= nt64_t value) "mbox write bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox = read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbo= x property tag:0x%08x in_sz:%u out_sz:%zu" + +# djmemc.c +djMEMC_read(int reg, unsigned size, uint64_t value) "reg=3D%d size=3D%u va= lue=3D0x%"PRIx64 +djMEMC_write(int reg, unsigned size, uint64_t value) "reg=3D%d size=3D%u v= alue=3D0x%"PRIx64 diff --git a/include/hw/misc/djmemc.h b/include/hw/misc/djmemc.h new file mode 100644 index 0000000000..0f29ac1cf3 --- /dev/null +++ b/include/hw/misc/djmemc.h @@ -0,0 +1,34 @@ +/* + * djMEMC, macintosh memory and interrupt controller + * (Quadra 610/650/800 & Centris 610/650) + */ + +#ifndef HW_MISC_DJMEMC_H +#define HW_MISC_DJMEMC_H + +#include "hw/sysbus.h" +#include "cpu.h" + +#define DjMEMCMaxBanks 10 + +typedef struct DjMEMCState { + SysBusDevice parent_obj; + + MemoryRegion mem_regs; + + /* Memory controller */ + uint32_t interleave; + uint32_t bank[DjMEMCMaxBanks]; + uint32_t top; + uint32_t config; + uint32_t refresh_rate; + + /* interrupt controller */ + M68kCPU *cpu; + uint8_t ipr; +} DjMEMCState; + +#define TYPE_DJMEMC "djMEMC" +#define DJMEMC(obj) OBJECT_CHECK(DjMEMCState, (obj), TYPE_DJMEMC) + +#endif --=20 2.23.0 From nobody Sun Apr 28 07:43:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576181042; cv=none; d=zohomail.com; s=zohoarc; b=Wfeq4ZOGPVb0bB7mIZ3WU6Y+Db34/dID17xmTgrPGi9f/KsCwXBTq07ELiITOijY9p4Zzz2kh4sJm8H7hjwUdEPt+uBnp/kE3UuyybTHPxE21oGYpkmEDDHAbWXCYddLU+ARDKKjBd5zKiIo8lSXjuiV2oxl+p2ilCMYUWqZqFU= ARC-Message-Signature: i=1; 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Thu, 12 Dec 2019 15:04:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47498) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifUel-0005x9-Na for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifUej-0004Bk-OE for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:51 -0500 Received: from mout.kundenserver.de ([212.227.17.10]:57803) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ifUeh-00045c-Rv for qemu-devel@nongnu.org; Thu, 12 Dec 2019 15:01:49 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1Mc0Aj-1i9Am62F1b-00dYKu; Thu, 12 Dec 2019 21:01:45 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PATCH 3/3] q800: add machine id register Date: Thu, 12 Dec 2019 21:01:42 +0100 Message-Id: <20191212200142.15688-4-laurent@vivier.eu> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191212200142.15688-1-laurent@vivier.eu> References: <20191212200142.15688-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:LHAt3RXFVpaySF64Kl9iPBd2yyjs6PJChFZ47pyeTU4QVdbLu3D c9UDqwQitq5X7o1nAMxnk+3ffYqE589wysy9/igmY/IRPvYhvvZqS0YO3Gxi0WUHke3o77s SDRlAEFcuJcob7Szrws2jHopfk5RCiXVnBu38xerDb6XAv6QyMZZNFbpe2i4cpqhA/dIQjc ZB8TVpdhaPa3PXOux4unw== X-UI-Out-Filterresults: notjunk:1;V03:K0:HEBpSguBOKU=:Evf6mzJ4WaMmoL/KM3Cflj MQVfeMwMAjL/8K+cbsO8zgwMStHi+GWmmjckALJV5vIoyWSiYxXpAqvWDzlwMgQyxG2C0TT1t 9yLABIX6xZF6O8GWQ49fDeBoboqSBvCjNbY+noP2N6KBV8u5sELEZ2sJzXKfHYvfMpqf06yPf hLiaA1NOlhrGMGGRVtYGdYUJ1fElN++g6XWgKm9gISliC2CcS0deOpwP2Q6dfiBTWjaZ20OqH +V/VPy36wGm7b4LjMqAyz8j3tWzdoWbDB9BxjvaHYq2K7FkSs3xClXK5m984zjeMrkgEWl5ok F62EuD2ODSBKl5dqACV0tst8pe6B9+22f0hHP/gWxkXD1rbAofYFf945c9Z6kUssEktXIHNcY qz2TEqNGLSaaKgtQaEtHfLfDudB4FgB+ETPrMTrnn5OCaov0At1R0orlaNFSp67jzkl1CWdmW Z0t+4TWlzg7KuRlhXWN+9pjWIF2HoAA8u4b+PcdBkeuAwy5CMhCbtXJfa8v7PjhyRz9+4tOTo uqswnDDGgAWmSCzfojixa1C+jcN+nCwrBUfYXobw1UFNhNBWwVhOFVaeAlMHFrV+TGa7htPVR FVwsxkUwRorCRczK9X2DMTDI6a8yfz83S3InkB4b05+ggG8x09Z8xO9h8kzE9TMTBT5mZZzE/ 9Q368rA9kckGzOcQgUVKO+8NsFjOSXCqnn7RRH7Ytb40TjbCtWYQK3fXjonV/b9xZSCMa8kxU GJ2esys++W/ZMIGCtFnzn/r9T210IdgI+WSp0ZwMNGLwRUAHALr6qRTbkON4hrDY+R0oIZdNP 7+CtQBi016kXd5pTSMQUO/n7v+VTjE8XrqhyRsCO+4f+bIs8m6hZzeokaCcNooWg0FEW/aBWl gu02HZX7wtbRwQch2/5w== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" MacOS reads this address to identify the hardware. This is a basic implementation returning the ID of Quadra 800. Details: http://mess.redump.net/mess/driver_info/mac_technical_notes "There are 3 ID schemes [...] The third and most scalable is a machine ID register at 0x5ffffffc. The top word must be 0xa55a to be valid. Then bits 15-11 are 0 for consumer Macs, 1 for portables, 2 for high-end 68k, and 3 for high-end PowerPC. Bit 10 is 1 if additional ID bits appear elsewhere (e.g. in VIA1). The rest of the bits are a per-model identifier. Model Lower 16 bits of ID ... Quadra/Centris 610/650/800 0x2BAD" Signed-off-by: Laurent Vivier Reviewed-by: Mark Cave-Ayland --- hw/m68k/q800.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 9ee0cb1141..c2b2aa779f 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -97,6 +97,23 @@ static void main_cpu_reset(void *opaque) cpu->env.pc =3D ldl_phys(cs->as, 4); } =20 +static uint64_t machine_id_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0xa55a2bad; /* Quadra 800 ID */ +} + +static void machine_id_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ +} + +static const MemoryRegionOps machine_id_ops =3D { + .read =3D machine_id_read, + .write =3D machine_id_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + static void q800_init(MachineState *machine) { M68kCPU *cpu =3D NULL; @@ -110,6 +127,7 @@ static void q800_init(MachineState *machine) MemoryRegion *rom; MemoryRegion *ram; MemoryRegion *io; + MemoryRegion *machine_id; const int io_slice_nb =3D (IO_SIZE / IO_SLICE) - 1; int i; ram_addr_t ram_size =3D machine->ram_size; @@ -159,6 +177,10 @@ static void q800_init(MachineState *machine) g_free(name); } =20 + machine_id =3D g_malloc(sizeof(*machine_id)); + memory_region_init_io(machine_id, NULL, &machine_id_ops, NULL, "Machin= e ID", 4); + memory_region_add_subregion(get_system_memory(), 0x5ffffffc, machine_i= d); + /* djMEMC memory and interrupt controller */ =20 djmemc_dev =3D qdev_create(NULL, TYPE_DJMEMC); --=20 2.23.0