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Wed, 11 Dec 2019 09:11:21 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers Date: Wed, 11 Dec 2019 17:05:12 +0000 Message-Id: <20191211170520.7747-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191211170520.7747-1-alex.bennee@linaro.org> References: <20191211170520.7747-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: damien.hedde@greensocs.com, Peter Maydell , luis.machado@linaro.org, richard.henderson@linaro.org, "open list:ARM TCG CPUs" , alan.hayward@arm.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We also expose a the helpers to read/write the the registers. Signed-off-by: Alex Benn=C3=A9e --- v2 - instead of zNpM expose zN at sve_max_vq width - wrap union in union q(us), d(usf), s(usf), h(usf), b(us) v3 - add a vg pseudo register for current width - spacing fixes - use switch/case for whole group - drop fpsr_pos marker - remove unused variables --- target/arm/cpu.h | 7 ++- target/arm/gdbstub.c | 133 +++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 121 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 256 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc7258d5f1d..25d34bc5197 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -755,6 +755,7 @@ struct ARMCPU { int32_t cpreg_vmstate_array_len; =20 DynamicGDBXMLInfo dyn_sysreg_xml; + DynamicGDBXMLInfo dyn_svereg_xml; =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; @@ -958,10 +959,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cp= u, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -/* Dynamically generates for gdb stub an XML description of the sysregs fr= om - * the cp_regs hashtable. Returns the registered sysregs number. +/* + * Helpers to dynamically generates XML descriptions of the sysregs + * and SVE registers. Returns the number of registers in each set. */ int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); =20 /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 69c35462a63..546906dbcb2 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -171,12 +171,145 @@ int arm_gen_dynamic_sysreg_xml(CPUState *cs, int bas= e_reg) return cpu->dyn_sysreg_xml.num; } =20 +struct TypeSize { + const char *gdb_type; + int size; + const char sz, suffix; +}; + +static struct TypeSize vec_lanes[] =3D { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + { "ieee_double", 64, 'd', 'f' }, + /* 32 bit */ + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + { "ieee_single", 32, 's', 'f' }, + /* 16 bit */ + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + { "ieee_half", 16, 'h', 'f' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, +}; + + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GString *s =3D g_string_new(NULL); + DynamicGDBXMLInfo *info =3D &cpu->dyn_svereg_xml; + g_autoptr(GString) ts =3D g_string_new(""); + int i, bits, reg_width =3D (cpu->sve_max_vq * 128); + info->num =3D 0; + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count =3D reg_width / vec_lanes[i].size; + g_string_printf(ts, "vq%d%c%c", count, + vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + /* + * Now define a union for each size group containing unsigned and + * signed and potentially float versions of each size from 128 to + * 8 bits. + */ + for (bits =3D 128; bits >=3D 8; bits /=3D 2) { + int count =3D reg_width / bits; + g_string_append_printf(s, "", count); + for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { + if (vec_lanes[i].size =3D=3D bits) { + g_string_append_printf(s, "", + vec_lanes[i].suffix, + count, + vec_lanes[i].sz, vec_lanes[i].suffi= x); + } + } + g_string_append(s, ""); + } + /* And now the final union of unions */ + g_string_append(s, ""); + for (bits =3D 128; bits >=3D 8; bits /=3D 2) { + int count =3D reg_width / bits; + for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { + if (vec_lanes[i].size =3D=3D bits) { + g_string_append_printf(s, "", + vec_lanes[i].sz, count); + break; + } + } + } + g_string_append(s, ""); + + /* Then define each register in parts for each vq */ + for (i =3D 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + info->num++; + } + /* fpscr & status registers */ + g_string_append_printf(s, "", base_reg++); + g_string_append_printf(s, "", base_reg++); + info->num +=3D 2; + /* + * Predicate registers aren't so big they are worth splitting up + * but we do need to define a type to hold the array of quad + * references. + */ + g_string_append_printf(s, + "", + cpu->sve_max_vq); + for (i =3D 0; i < 16; i++) { + g_string_append_printf(s, + "", + i, cpu->sve_max_vq * 16, base_reg++); + info->num++; + } + g_string_append_printf(s, + "", + cpu->sve_max_vq * 16, base_reg++); + g_string_append_printf(s, + "", base_reg++); + info->num +=3D 2; + g_string_append_printf(s, ""); + cpu->dyn_svereg_xml.desc =3D g_string_free(s, false); + + return cpu->dyn_svereg_xml.num; +} + + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu =3D ARM_CPU(cs); =20 if (strcmp(xmlname, "system-registers.xml") =3D=3D 0) { return cpu->dyn_sysreg_xml.desc; + } else if (strcmp(xmlname, "sve-registers.xml") =3D=3D 0) { + return cpu->dyn_svereg_xml.desc; } return NULL; } diff --git a/target/arm/helper.c b/target/arm/helper.c index d00e4fcca86..b6e1fe51d76 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -201,6 +201,15 @@ static void write_raw_cp_reg(CPUARMState *env, const A= RMCPRegInfo *ri, } } =20 +/** + * arm_get/set_gdb_*: get/set a gdb register + * @env: the CPU state + * @buf: a buffer to copy to/from + * @reg: register number (offset from start of group) + * + * We return the number of bytes copied + */ + static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu =3D env_archcpu(env); @@ -224,6 +233,98 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8_= t *buf, int reg) return 0; } =20 +#ifdef TARGET_AARCH64 +static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len =3D 0; + for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + len +=3D gdb_get_reg128(buf, + env->vfp.zregs[reg].d[vq * 2 + 1], + env->vfp.zregs[reg].d[vq * 2]); + } + return len; + } + case 32: + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + /* then 16 predicates and the ffr */ + case 34 ... 50: + { + int preg =3D reg - 34; + int vq, len =3D 0; + for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + } + return len; + } + case 51: + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); + default: + /* gdbstub asked for something out our range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* The first 32 registers are the zregs */ + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len =3D 0; + uint64_t *p =3D (uint64_t *) buf; + for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + env->vfp.zregs[reg].d[vq * 2 + 1] =3D *p++; + env->vfp.zregs[reg].d[vq * 2] =3D *p++; + len +=3D 16; + } + return len; + } + case 32: + vfp_set_fpsr(env, *(uint32_t *)buf); + return 4; + case 33: + vfp_set_fpcr(env, *(uint32_t *)buf); + return 4; + case 34 ... 50: + { + int preg =3D reg - 34; + int vq, len =3D 0; + uint64_t *p =3D (uint64_t *) buf; + for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + env->vfp.pregs[preg].p[vq / 4] =3D *p++; + len +=3D 8; + } + return len; + } + case 51: + { + uint64_t val =3D *(uint64_t *) buf; + cpu->env.vfp.zcr_el[1] =3D (val - 1) & 0xf; + return 8; + } + default: + /* gdbstub asked for something out our range */ + break; + } + + return 0; +} +#endif /* TARGET_AARCH64 */ + static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -6981,9 +7082,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *= cpu) CPUARMState *env =3D &cpu->env; =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, - 34, "aarch64-fpu.xml", 0); + /* + * The lower part of each SVE register aliases to the FPU + * registers so we don't need to include both. + */ +#ifdef TARGET_AARCH64 + if (isar_feature_aa64_sve(&cpu->isar)) { + gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_s= vereg, + arm_gen_dynamic_svereg_xml(cs, cs->gd= b_num_regs), + "sve-registers.xml", 0); + } else +#endif + { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); @@ -6997,6 +7111,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), "system-registers.xml", 0); + } =20 /* Sort alphabetically by type name, except for "any". */ --=20 2.20.1