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[79.180.52.3]) by smtp.gmail.com with ESMTPSA id h17sm25289717wrs.18.2019.12.08.10.40.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 08 Dec 2019 10:40:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D1CFu45Ji78GInCfgoXCAqlh1vy92VNoeIneSjkFFMU=; b=CO3cPQbIqK1ZwopDErODYVXmdwBvBStHPOTEqz0fgc/6g7c2ueyC2Uu0BWmP2jHvDF YNbgnGJW2Pv1DnTbj2L0L/vcELPSw6uMh2PmfFImTbgHAPpu37kh2tyArzvlPKpGTS3D LrmuLNS5qiB/Xkx7SvSh5Ag51dEYQ8dtdYHGsyPlZPEwZ8IWfPisQimyfj05XVroa/hm Uyyf8LuiY1DeNR29RRa/COmvStO76Wa4DCOngOcmsGPsNn/gF4bvYfC8lm/NTTUUI6Hp cp+2VFyT5XSPvu0U27NO0vwt7cKu5xArFITE1irh8jRAVbGqG9ySj0iPJGSvkrnQEsif FsFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D1CFu45Ji78GInCfgoXCAqlh1vy92VNoeIneSjkFFMU=; b=lN/epoid4p9+wDlAlrolRPcRmYZcKYxVM6TuJRUBtMaLSqAdtxnq37iuXIoAvdU6+y cwpAcnBxj9j8yPwYUDhFWzlqp5OXyyi3kJMbfiqQ7hS62Klea2NXsS9k/bJouDt55mGK 4sqPMN7I/ItaU5x45GnHH1/gy7wui2XWcZTpuaPcJ5U7rEmDXaxT4PWp4wL7/4n0wlua zqmdVWHMTZP2aq7P9YsoU8RpdlOxUUJ1mjUvsraWgXag5voYq8CGGACHiDhhcIIk9r90 F4o+/QGcL4nYgxSW+bA+U6vMj0TxYBrOUHc74Z2iScmt80Y2qIMBOR7P5yEbbr9Nw8gf 3UWg== X-Gm-Message-State: APjAAAU0u9dHu7Ch/wDOe+s3T8ktGF3nb5p7m8AFiluPAqVduSMnTpDb 77/CcR1hzWfwjvKbggRKPbVBcZtheT6XTMuR X-Google-Smtp-Source: APXvYqyqwHUfH4sQkaxUhWh7zfiBN6RS4wSAejewFuMYrpM7QJegw8hD4lBEYt9vSjemSaBZVJ8tBw== X-Received: by 2002:a5d:52c4:: with SMTP id r4mr9224500wrv.368.1575830411999; Sun, 08 Dec 2019 10:40:11 -0800 (PST) From: Michael Rolnik To: qemu-devel@nongnu.org Subject: [PATCH v38 10/22] target/avr: Add instruction translation - CPU main translation function Date: Sun, 8 Dec 2019 20:39:10 +0200 Message-Id: <20191208183922.13757-11-mrolnik@gmail.com> X-Mailer: git-send-email 2.17.2 (Apple Git-113) In-Reply-To: <20191208183922.13757-1-mrolnik@gmail.com> References: <20191208183922.13757-1-mrolnik@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Michael Rolnik , me@xcancerberox.com.ar, richard.henderson@linaro.org, dovgaluk@ispras.ru, imammedo@redhat.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/translate.c | 234 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 68025112ff..c8c6f798bf 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2690,3 +2690,237 @@ static bool trans_WDR(DisasContext *ctx, arg_WDR *a) =20 return true; } + + +void avr_cpu_tcg_init(void) +{ + int i; + +#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) + cpu_pc =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); + cpu_Cf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); + cpu_Zf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); + cpu_Nf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); + cpu_Vf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); + cpu_Sf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); + cpu_Hf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); + cpu_Tf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); + cpu_If =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); + cpu_rampD =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "ra= mpD"); + cpu_rampX =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "ra= mpX"); + cpu_rampY =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "ra= mpY"); + cpu_rampZ =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "ra= mpZ"); + cpu_eind =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind= "); + cpu_sp =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); + cpu_skip =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip= "); + + for (i =3D 0; i < NUMBER_OF_CPU_REGISTERS; i++) { + cpu_r[i] =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), + reg_names[i]); + } +#undef AVR_REG_OFFS +} + +static void translate(DisasContext *ctx) +{ + uint32_t opcode =3D next_word(ctx); + + if (!decode_insn(ctx, opcode)) { + gen_helper_unsupported(cpu_env); + ctx->bstate =3D DISAS_NORETURN; + } +} + +/* Standardize the cpu_skip condition to NE. */ +static bool canonicalize_skip(DisasContext *ctx) +{ + switch (ctx->skip_cond) { + case TCG_COND_NEVER: + /* Normal case: cpu_skip is known to be false. */ + return false; + + case TCG_COND_ALWAYS: + /* + * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKI= P. + * The breakpoint is on the instruction being skipped, at the start + * of the TranslationBlock. No need to update. + */ + return false; + + case TCG_COND_NE: + if (ctx->skip_var1 =3D=3D NULL) { + tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); + } else { + tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); + ctx->skip_var1 =3D NULL; + } + break; + + default: + /* Convert to a NE condition vs 0. */ + if (ctx->skip_var1 =3D=3D NULL) { + tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, = 0); + } else { + tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, + ctx->skip_var0, ctx->skip_var1); + ctx->skip_var1 =3D NULL; + } + ctx->skip_cond =3D TCG_COND_NE; + break; + } + if (ctx->free_skip_var0) { + tcg_temp_free(ctx->skip_var0); + ctx->free_skip_var0 =3D false; + } + ctx->skip_var0 =3D cpu_skip; + return true; +} + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +{ + CPUAVRState *env =3D cs->env_ptr; + DisasContext ctx =3D { + .tb =3D tb, + .cs =3D cs, + .env =3D env, + .memidx =3D 0, + .bstate =3D DISAS_NEXT, + .skip_cond =3D TCG_COND_NEVER, + .singlestep =3D cs->singlestep_enabled, + }; + target_ulong pc_start =3D tb->pc / 2; + int num_insns =3D 0; + + if (tb->flags & TB_FLAGS_FULL_ACCESS) { + /* + * This flag is set by ST/LD instruction we will regenerate it ONLY + * with mem/cpu memory access instead of mem access + */ + max_insns =3D 1; + } + if (ctx.singlestep) { + max_insns =3D 1; + } + + gen_tb_start(tb); + + ctx.npc =3D pc_start; + if (tb->flags & TB_FLAGS_SKIP) { + ctx.skip_cond =3D TCG_COND_ALWAYS; + ctx.skip_var0 =3D cpu_skip; + } + + do { + TCGLabel *skip_label =3D NULL; + + /* translate current instruction */ + tcg_gen_insn_start(ctx.npc); + num_insns++; + + /* + * this is due to some strange GDB behavior + * let's assume main has address 0x100 + * b main - sets breakpoint at address 0x00000100 (code) + * b *0x100 - sets breakpoint at address 0x00800100 (data) + */ + if (unlikely(!ctx.singlestep && + (cpu_breakpoint_test(cs, OFFSET_CODE + ctx.npc * 2, BP_ANY= ) || + cpu_breakpoint_test(cs, OFFSET_DATA + ctx.npc * 2, BP_ANY= )))) { + canonicalize_skip(&ctx); + tcg_gen_movi_tl(cpu_pc, ctx.npc); + gen_helper_debug(cpu_env); + goto done_generating; + } + + /* Conditionally skip the next instruction, if indicated. */ + if (ctx.skip_cond !=3D TCG_COND_NEVER) { + skip_label =3D gen_new_label(); + if (ctx.skip_var0 =3D=3D cpu_skip) { + /* + * Copy cpu_skip so that we may zero it before the branch. + * This ensures that cpu_skip is non-zero after the label + * if and only if the skipped insn itself sets a skip. + */ + ctx.free_skip_var0 =3D true; + ctx.skip_var0 =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx.skip_var0, cpu_skip); + tcg_gen_movi_tl(cpu_skip, 0); + } + if (ctx.skip_var1 =3D=3D NULL) { + tcg_gen_brcondi_tl(ctx.skip_cond, ctx.skip_var0, 0, skip_l= abel); + } else { + tcg_gen_brcond_tl(ctx.skip_cond, ctx.skip_var0, + ctx.skip_var1, skip_label); + ctx.skip_var1 =3D NULL; + } + if (ctx.free_skip_var0) { + tcg_temp_free(ctx.skip_var0); + ctx.free_skip_var0 =3D false; + } + ctx.skip_cond =3D TCG_COND_NEVER; + ctx.skip_var0 =3D NULL; + } + + translate(&ctx); + + if (skip_label) { + canonicalize_skip(&ctx); + gen_set_label(skip_label); + if (ctx.bstate =3D=3D DISAS_NORETURN) { + ctx.bstate =3D DISAS_CHAIN; + } + } + } while (ctx.bstate =3D=3D DISAS_NEXT + && num_insns < max_insns + && (ctx.npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 + && !tcg_op_buf_full()); + + if (tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + bool nonconst_skip =3D canonicalize_skip(&ctx); + + switch (ctx.bstate) { + case DISAS_NORETURN: + assert(!nonconst_skip); + break; + case DISAS_NEXT: + case DISAS_TOO_MANY: + case DISAS_CHAIN: + if (!nonconst_skip) { + /* Note gen_goto_tb checks singlestep. */ + gen_goto_tb(&ctx, 1, ctx.npc); + break; + } + tcg_gen_movi_tl(cpu_pc, ctx.npc); + /* fall through */ + case DISAS_LOOKUP: + if (!ctx.singlestep) { + tcg_gen_lookup_and_goto_ptr(); + break; + } + /* fall through */ + case DISAS_EXIT: + if (ctx.singlestep) { + gen_helper_debug(cpu_env); + } else { + tcg_gen_exit_tb(NULL, 0); + } + break; + default: + g_assert_not_reached(); + } + +done_generating: + gen_tb_end(tb, num_insns); + + tb->size =3D (ctx.npc - pc_start) * 2; + tb->icount =3D num_insns; +} + +void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb, + target_ulong *data) +{ + env->pc_w =3D data[0]; +} --=20 2.17.2 (Apple Git-113)