From nobody Tue Feb 10 05:41:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575572260; cv=none; d=zohomail.com; s=zohoarc; b=D1vG2fSLa0k7l2F5tQ4iSKFKtWF9AYaXVkl/pKu4iYOwq3tSJDvxyoFjIeiraxNe2fOOqFG914fHJGHlg+iYG6gonMAnO2Hee57CqCeeHufSgsuh/1zmamtyj1l9hbgEzbMuCxKhZSUwKX8ku0whZK92ZJuN9gRdsTmVArd+YyQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575572260; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gf9xKfPE3hTjjLC7PupLlgf4OrbJDpE2y5L5riXmncY=; b=Y1u64EdV6EFzuMxhJI6JdpREl+DjCACCjsWtf8D4AjhRykFp71r9wv8LdoMmI6FL8UGf9dBaxm+srYZ5P4qyY4OqIJcYvibeBuS4HMusMNTxIyI5twZLmFRiMHY402Zlb6nNNiIroFQ0sUkb72WNKV8rf90yLCWWUBuGEQ+WIfc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575572260626719.4345051350653; Thu, 5 Dec 2019 10:57:40 -0800 (PST) Received: from localhost ([::1]:59794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icwJn-00062x-7q for importer@patchew.org; Thu, 05 Dec 2019 13:57:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43735) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icw8J-0006Dl-OY for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icw8H-0001ra-SB for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:47 -0500 Received: from 10.mo3.mail-out.ovh.net ([87.98.165.232]:53360) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icw8H-0001l1-HU for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:45 -0500 Received: from player158.ha.ovh.net (unknown [10.108.57.178]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id DEAB3231786 for ; Thu, 5 Dec 2019 19:45:43 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 2FB54CDB158E; Thu, 5 Dec 2019 18:45:38 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 5/5] ppc/pnv: add a LPC Controller model for POWER10 Date: Thu, 5 Dec 2019 19:44:54 +0100 Message-Id: <20191205184454.10722-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191205184454.10722-1-clg@kaod.org> References: <20191205184454.10722-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5789095850069494758 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekuddguddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjqdffgfeufgfipdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrudehkedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.165.232 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Same a POWER9, only the MMIO window changes. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 4 ++++ include/hw/ppc/pnv_lpc.h | 6 +++++- hw/ppc/pnv.c | 25 ++++++++++++++++++++++--- hw/ppc/pnv_lpc.c | 30 ++++++++++++++++++++++-------- 4 files changed, 53 insertions(+), 12 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 47b7370b27d8..56d1161515dd 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -115,6 +115,7 @@ typedef struct Pnv10Chip { =20 /*< public >*/ Pnv9Psi psi; + PnvLpcController lpc; } Pnv10Chip; =20 typedef struct PnvChipClass { @@ -329,6 +330,9 @@ IPMIBmc *pnv_bmc_create(void); #define PNV10_XSCOM_SIZE 0x0000000400000000ull #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc000000= 00ull) =20 +#define PNV10_LPCM_SIZE 0x0000000100000000ull +#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00060300000000= 00ull) + #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x00060302020000= 00ull) =20 diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index f659410716e1..c1ec85d5e2c5 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -31,6 +31,9 @@ #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9" #define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC) =20 +#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10" +#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LP= C) + typedef struct PnvLpcController { DeviceState parent; =20 @@ -97,6 +100,7 @@ typedef struct PnvLpcClass { struct PnvChip; =20 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); -int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset); +int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset, + uint64_t lpcm_addr, uint64_t lpcm_size); =20 #endif /* PPC_PNV_LPC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 09263ab747d8..67d0ad55b870 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -314,7 +314,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, = void *fdt) pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } =20 - pnv_dt_lpc(chip, fdt, 0); + pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); } =20 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) @@ -332,6 +332,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip,= void *fdt) if (chip->ram_size) { pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } + + pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } =20 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -601,8 +603,8 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip= , Error **errp) =20 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) { - error_setg(errp, "No ISA bus!"); - return NULL; + Pnv10Chip *chip10 =3D PNV10_CHIP(chip); + return pnv_lpc_isa_create(&chip10->lpc, false, errp); } =20 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) @@ -1315,6 +1317,8 @@ static void pnv_chip_power10_instance_init(Object *ob= j) =20 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), TYPE_PNV10_PSI, &error_abort, NULL); + object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), + TYPE_PNV10_LPC, &error_abort, NULL); } =20 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) @@ -1349,6 +1353,21 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) } pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, &PNV_PSI(&chip10->psi)->xscom_regs); + + /* LPC */ + object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "= psi", + &error_abort); + object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), + &chip10->lpc.xscom_regs); + + chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", + (uint64_t) PNV10_LPCM_BASE(chi= p)); } =20 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index dd5374c83899..18256d9ba399 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -122,26 +122,26 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, v= oid *fdt, int xscom_offset) } =20 /* POWER9 only */ -int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset) +int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_ad= dr, + uint64_t lpcm_size) { const char compat[] =3D "ibm,power9-lpcm-opb\0simple-bus"; const char lpc_compat[] =3D "ibm,power9-lpc\0ibm,lpc"; char *name; int offset, lpcm_offset; - uint64_t lpcm_addr =3D PNV9_LPCM_BASE(chip); uint32_t opb_ranges[8] =3D { 0, cpu_to_be32(lpcm_addr >> 32), cpu_to_be32((uint32_t)lpcm_addr), - cpu_to_be32(PNV9_LPCM_SIZE / 2), - cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_size / 2), + cpu_to_be32(lpcm_size / 2), cpu_to_be32(lpcm_addr >> 32), - cpu_to_be32(PNV9_LPCM_SIZE / 2), - cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_size / 2), + cpu_to_be32(lpcm_size / 2), }; uint32_t opb_reg[4] =3D { cpu_to_be32(lpcm_addr >> 32), cpu_to_be32((uint32_t)lpcm_addr), - cpu_to_be32(PNV9_LPCM_SIZE >> 32), - cpu_to_be32((uint32_t)PNV9_LPCM_SIZE), + cpu_to_be32(lpcm_size >> 32), + cpu_to_be32((uint32_t)lpcm_size), }; uint32_t lpc_ranges[12] =3D { 0, 0, cpu_to_be32(LPC_MEM_OPB_ADDR), @@ -691,6 +691,19 @@ static const TypeInfo pnv_lpc_power9_info =3D { .class_init =3D pnv_lpc_power9_class_init, }; =20 +static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "PowerNV LPC Controller POWER10"; +} + +static const TypeInfo pnv_lpc_power10_info =3D { + .name =3D TYPE_PNV10_LPC, + .parent =3D TYPE_PNV9_LPC, + .class_init =3D pnv_lpc_power10_class_init, +}; + static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); @@ -764,6 +777,7 @@ static void pnv_lpc_register_types(void) type_register_static(&pnv_lpc_info); type_register_static(&pnv_lpc_power8_info); type_register_static(&pnv_lpc_power9_info); + type_register_static(&pnv_lpc_power10_info); } =20 type_init(pnv_lpc_register_types) --=20 2.21.0