From nobody Tue May 7 05:33:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575571752; cv=none; d=zohomail.com; s=zohoarc; b=MD+wxaBsIPIU7aWaGmYZzQtcsyYREIH7awL9RGABhXNgbLM5b6xRAQ1rfvptTF7tjTfVt83PnS4awaE7gXTf8cVOv1tYPV8dE/v48Wdy3zJM2sk10xO2qpNYzRcrGZ63SZKpXG4zmSlN8xucH6TjvmKXLCq/vmrpKpA355Wrlrc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575571752; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M7ksKnzSPaVBEE2aE9lnl8Ui90/i9NX4B2+40KNfE3Y=; b=OYAq1DjLgj6tETIezCx9MI3sfzzyTco4k2fmbXuMjWwdf1jfjLSRQCs0eirMBM9fyfK3nKrK2qWfWHUbWjO/xKAiIg3bfyUJt4dZg5s+QGFmzfB11SXaIfWo9YJSc6wHUvyLFR52DEwAAzteJcVfMUoRrdl8xbwS0jxnpodYnuc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575571752111939.3578041785753; Thu, 5 Dec 2019 10:49:12 -0800 (PST) Received: from localhost ([::1]:59692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icwBa-0007nu-DI for importer@patchew.org; Thu, 05 Dec 2019 13:49:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42616) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icw85-0005uf-EG for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icw7z-0000mk-CO for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:31 -0500 Received: from 10.mo6.mail-out.ovh.net ([87.98.157.236]:43482) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icw7x-0000ek-3p for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:27 -0500 Received: from player158.ha.ovh.net (unknown [10.108.35.232]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id C24D01F012B for ; Thu, 5 Dec 2019 19:45:20 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 1509ECDB14DD; Thu, 5 Dec 2019 18:45:15 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 1/5] target/ppc: Add POWER10 DD1.0 model information Date: Thu, 5 Dec 2019 19:44:50 +0100 Message-Id: <20191205184454.10722-2-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191205184454.10722-1-clg@kaod.org> References: <20191205184454.10722-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5782621924080782310 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekuddguddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjqdffgfeufgfipdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuffhomhgrihhnpedutddrnhgrmhgvpddtiedrnhgrmhgvpddttddrnhgrmhgvpddtjedrnhgrmhgvpddthedrnhgrmhgvnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrudehkedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.157.236 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This includes in QEMU a new CPU model for the POWER10 processor with the same capabilities of a POWER9 process. The model will be extended when support is completed. Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu-models.h | 3 + target/ppc/cpu.h | 1 + target/ppc/compat.c | 21 +++- target/ppc/cpu-models.c | 3 + target/ppc/translate_init.inc.c | 215 ++++++++++++++++++++++++++++++++ 5 files changed, 237 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 4fdb73034dd0..ce750b2d55d2 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -373,6 +373,8 @@ enum { CPU_POWERPC_POWER9_BASE =3D 0x004E0000, CPU_POWERPC_POWER9_DD1 =3D 0x004E0100, CPU_POWERPC_POWER9_DD20 =3D 0x004E1200, + CPU_POWERPC_POWER10_BASE =3D 0x00800000, + CPU_POWERPC_POWER10_DD1 =3D 0x00800100, CPU_POWERPC_970_v22 =3D 0x00390202, CPU_POWERPC_970FX_v10 =3D 0x00391100, CPU_POWERPC_970FX_v20 =3D 0x003C0200, @@ -409,6 +411,7 @@ enum { CPU_POWERPC_LOGICAL_2_06_PLUS =3D 0x0F100003, CPU_POWERPC_LOGICAL_2_07 =3D 0x0F000004, CPU_POWERPC_LOGICAL_3_00 =3D 0x0F000005, + CPU_POWERPC_LOGICAL_3_10 =3D 0x0F000006, }; =20 /* System version register (used on MPC 8xxx) = */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f9528fc29d98..0c5eb67245ef 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2368,6 +2368,7 @@ enum { PCR_COMPAT_2_06 =3D PPC_BIT(61), PCR_COMPAT_2_07 =3D PPC_BIT(60), PCR_COMPAT_3_00 =3D PPC_BIT(59), + PCR_COMPAT_3_10 =3D PPC_BIT(58), PCR_VEC_DIS =3D PPC_BIT(0), /* Vec. disable (bit NA since POWE= R8) */ PCR_VSX_DIS =3D PPC_BIT(1), /* VSX disable (bit NA since POWER= 8) */ PCR_TM_DIS =3D PPC_BIT(2), /* Trans. memory disable (POWER8) = */ diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 7de4bf312285..f48df2594459 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -51,36 +51,38 @@ static const CompatInfo compat_table[] =3D { { /* POWER6, ISA2.05 */ .name =3D "power6", .pvr =3D CPU_POWERPC_LOGICAL_2_05, - .pcr =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | - PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS, + .pcr =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DI= S, .pcr_level =3D PCR_COMPAT_2_05, .max_vthreads =3D 2, }, { /* POWER7, ISA2.06 */ .name =3D "power7", .pvr =3D CPU_POWERPC_LOGICAL_2_06, - .pcr =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR= _TM_DIS, + .pcr =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_TM_DIS, .pcr_level =3D PCR_COMPAT_2_06, .max_vthreads =3D 4, }, { .name =3D "power7+", .pvr =3D CPU_POWERPC_LOGICAL_2_06_PLUS, - .pcr =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR= _TM_DIS, + .pcr =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_TM_DIS, .pcr_level =3D PCR_COMPAT_2_06, .max_vthreads =3D 4, }, { /* POWER8, ISA2.07 */ .name =3D "power8", .pvr =3D CPU_POWERPC_LOGICAL_2_07, - .pcr =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07, + .pcr =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07, .pcr_level =3D PCR_COMPAT_2_07, .max_vthreads =3D 8, }, { /* POWER9, ISA3.00 */ .name =3D "power9", .pvr =3D CPU_POWERPC_LOGICAL_3_00, - .pcr =3D PCR_COMPAT_3_00, + .pcr =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00, .pcr_level =3D PCR_COMPAT_3_00, /* * POWER9 hardware only supports 4 threads / core, but this @@ -91,6 +93,13 @@ static const CompatInfo compat_table[] =3D { */ .max_vthreads =3D 8, }, + { /* POWER10, ISA3.10 */ + .name =3D "power10", + .pvr =3D CPU_POWERPC_LOGICAL_3_10, + .pcr =3D PCR_COMPAT_3_10, + .pcr_level =3D PCR_COMPAT_3_10, + .max_vthreads =3D 8, + }, }; =20 static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 086548e9b965..4ad16863c0ce 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -774,6 +774,8 @@ "POWER9 v1.0") POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER= 9, "POWER9 v2.0") + POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER= 10, + "POWER10 v1.0") #endif /* defined (TARGET_PPC64) */ =20 /*************************************************************************= **/ @@ -950,6 +952,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { { "power8", "power8_v2.0" }, { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.0" }, + { "power10", "power10_v1.0" }, #endif =20 /* Generic PowerPCs */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 64a838095c7a..7364d36b07a8 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -3354,6 +3354,11 @@ static void init_excp_POWER9(CPUPPCState *env) #endif } =20 +static void init_excp_POWER10(CPUPPCState *env) +{ + init_excp_POWER9(env); +} + #endif =20 /*************************************************************************= ****/ @@ -8996,6 +9001,216 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; } =20 +#ifdef CONFIG_SOFTMMU +/* + * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-enco= dings + * Encoded as array of int_32s in the form: + * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy + * x -> AP encoding + * y -> radix mode supported page size (encoded as a shift) + */ +static struct ppc_radix_page_info POWER10_radix_page_info =3D { + .count =3D 4, + .entries =3D { + 0x0000000c, /* 4K - enc: 0x0 */ + 0xa0000010, /* 64K - enc: 0x5 */ + 0x20000015, /* 2M - enc: 0x1 */ + 0x4000001e /* 1G - enc: 0x2 */ + } +}; +#endif /* CONFIG_SOFTMMU */ + +static void init_proc_POWER10(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_book3s_207_dbg(env); + + /* POWER8 Specific Registers */ + gen_spr_book3s_ids(env); + gen_spr_amr(env); + gen_spr_iamr(env); + gen_spr_book3s_purr(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power6_common(env); + gen_spr_power6_dbg(env); + gen_spr_power8_tce_address_control(env); + gen_spr_power8_ids(env); + gen_spr_power8_ebb(env); + gen_spr_power8_fscr(env); + gen_spr_power8_pmu_sup(env); + gen_spr_power8_pmu_user(env); + gen_spr_power8_tm(env); + gen_spr_power8_pspb(env); + gen_spr_vtb(env); + gen_spr_power8_ic(env); + gen_spr_power8_book4(env); + gen_spr_power8_rpr(env); + gen_spr_power9_mmu(env); + + /* POWER9 Specific registers */ + spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_TIDR, 0); + + /* FIXME: Filter fields properly based on privilege level */ + spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_PSSCR, 0); + + /* env variables */ + env->dcache_line_size =3D 128; + env->icache_line_size =3D 128; + + /* Allocate hardware IRQ controller */ + init_excp_POWER10(env); + ppcPOWER9_irq_init(env_archcpu(env)); +} + +static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) =3D=3D CPU_POWERPC_POWER10_B= ASE) { + return true; + } + return false; +} + +static bool cpu_has_work_POWER10(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + if (cs->halted) { + uint64_t psscr =3D env->spr[SPR_PSSCR]; + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + /* If EC is clear, just return true on any pending interrupt */ + if (!(psscr & PSSCR_EC)) { + return true; + } + /* External Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_EEE)) { + bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (heic =3D=3D 0 || !msr_hv || msr_pr) { + return true; + } + } + /* Decrementer Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_DEE)) { + return true; + } + /* Machine Check or Hypervisor Maintenance Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + return true; + } + /* Privileged Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_PDEE)) { + return true; + } + /* Hypervisor Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_HDEE)) { + return true; + } + /* Hypervisor virtualization exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && + (env->spr[SPR_LPCR] & LPCR_HVEE)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + +POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + dc->fw_name =3D "PowerPC,POWER10"; + dc->desc =3D "POWER10"; + dc->props =3D powerpc_servercpu_properties; + pcc->pvr_match =3D ppc_pvr_match_power10; + pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | + PCR_COMPAT_3_00; + pcc->pcr_supported =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_= 2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc =3D init_proc_POWER10; + pcc->check_pow =3D check_pow_nocheck; + cc->has_work =3D cpu_has_work_POWER10; + pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; + pcc->msr_mask =3D (1ull << MSR_SF) | + (1ull << MSR_SHV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model =3D POWERPC_MMU_3_00; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; + /* segment page size remain the same */ + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; + pcc->radix_page_info =3D &POWER10_radix_page_info; + pcc->lrg_decr_bits =3D 56; +#endif + pcc->excp_model =3D POWERPC_EXCP_POWER9; + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach =3D bfd_mach_ppc64; + pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; + pcc->l1_dcache_size =3D 0x8000; + pcc->l1_icache_size =3D 0x8000; + pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { --=20 2.21.0 From nobody Tue May 7 05:33:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575572102; cv=none; d=zohomail.com; s=zohoarc; b=dddzs795MIugOUBPHBIcAjXCgToDkwG44rlWv3BnqKjXFbD7uD75gkYq7FT5SgX30VqhAJNipWogeNVg83f/bYEFViOhX3WOCCndk//Y3xWED3pELjpKaaXdG2wvyepI4dS4CVfOcG9dDWm1CQnVufdNfIAteur9mCNC5JZHKUg= ARC-Message-Signature: i=1; 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Thu, 05 Dec 2019 13:55:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42800) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icw88-0005y8-CL for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icw85-0000y3-C5 for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:35 -0500 Received: from 2.mo69.mail-out.ovh.net ([178.33.251.80]:37523) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icw81-0000le-BI for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:31 -0500 Received: from player158.ha.ovh.net (unknown [10.108.57.50]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id C2758727B4 for ; Thu, 5 Dec 2019 19:45:26 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 9E084CDB1508; Thu, 5 Dec 2019 18:45:20 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 2/5] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine Date: Thu, 5 Dec 2019 19:44:51 +0100 Message-Id: <20191205184454.10722-3-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191205184454.10722-1-clg@kaod.org> References: <20191205184454.10722-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5784310774419393510 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekuddguddukecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjqdffgfeufgfipdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrudehkedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.251.80 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is an empty shell with the XSCOM bus and cores. The chip controllers will come later. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 33 ++++++++ include/hw/ppc/pnv_xscom.h | 19 +++++ hw/ppc/pnv.c | 158 +++++++++++++++++++++++++++++++++++-- hw/ppc/pnv_core.c | 10 +++ hw/ppc/pnv_xscom.c | 23 ++++-- 5 files changed, 232 insertions(+), 11 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 3a7bc3c57e0d..bfa61edfbabd 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -43,6 +43,7 @@ typedef enum PnvChipType { PNV_CHIP_POWER8, /* AKA Venice */ PNV_CHIP_POWER8NVL, /* AKA Naples */ PNV_CHIP_POWER9, /* AKA Nimbus */ + PNV_CHIP_POWER10, /* AKA TBD */ } PnvChipType; =20 typedef struct PnvChip { @@ -105,6 +106,14 @@ typedef struct Pnv9Chip { #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) =20 +#define TYPE_PNV10_CHIP "pnv10-chip" +#define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) + +typedef struct Pnv10Chip { + /*< private >*/ + PnvChip parent_obj; +} Pnv10Chip; + typedef struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; @@ -144,6 +153,10 @@ typedef struct PnvChipClass { #define PNV_CHIP_POWER9(obj) \ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) =20 +#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") +#define PNV_CHIP_POWER10(obj) \ + OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) + /* * This generates a HW chip id depending on an index, as found on a * two socket system with dual chip modules : @@ -203,6 +216,16 @@ PnvChip *pnv_get_chip(uint32_t chip_id); #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL =20 +static inline bool pnv_chip_is_power10(const PnvChip *chip) +{ + return PNV_CHIP_GET_CLASS(chip)->chip_type =3D=3D PNV_CHIP_POWER10; +} + +static inline bool pnv_is_power10(PnvMachineState *pnv) +{ + return pnv_chip_is_power10(pnv->chips[0]); +} + /* * BMC helpers */ @@ -293,4 +316,14 @@ IPMIBmc *pnv_bmc_create(void); #define PNV9_HOMER_SIZE 0x0000000000300000ull #define PNV9_HOMER_BASE(chip) \ (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZ= E) + +/* + * POWER10 MMIO base addresses - 16TB stride per chip + */ +#define PNV10_CHIP_BASE(chip, base) \ + ((base) + ((uint64_t) (chip)->chip_id << 44)) + +#define PNV10_XSCOM_SIZE 0x0000000400000000ull +#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc000000= 00ull) + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 67641ed27800..790eb3d8f3b0 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -70,6 +70,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 =20 +/* + * Layout of the XSCOM PCB addresses (POWER 9) + */ #define PNV9_XSCOM_EC_BASE(core) \ ((uint64_t)(((core) & 0x1F) + 0x20) << 24) #define PNV9_XSCOM_EC_SIZE 0x100000 @@ -87,6 +90,22 @@ typedef struct PnvXScomInterfaceClass { #define PNV9_XSCOM_XIVE_BASE 0x5013000 #define PNV9_XSCOM_XIVE_SIZE 0x300 =20 +/* + * Layout of the XSCOM PCB addresses (POWER 10) + */ +#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) +#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24) +#define PNV10_XSCOM_EC(proc) \ + ((0x2 << 16) | ((1 << (3 - (proc))) << 12)) + +#define PNV10_XSCOM_EQ_BASE(core) \ + ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) +#define PNV10_XSCOM_EQ_SIZE 0x100000 + +#define PNV10_XSCOM_EC_BASE(core) \ + ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) +#define PNV10_XSCOM_EC_SIZE 0x100000 + extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fa656858b24a..d99cd72840be 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -317,6 +317,23 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip,= void *fdt) pnv_dt_lpc(chip, fdt, 0); } =20 +static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) +{ + int i; + + pnv_dt_xscom(chip, fdt, 0); + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D chip->cores[i]; + + pnv_dt_core(chip, pnv_core, fdt); + } + + if (chip->ram_size) { + pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); + } +} + static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) { uint32_t io_base =3D d->ioport_id; @@ -467,6 +484,7 @@ static void *pnv_dt_create(MachineState *machine) { const char plat_compat8[] =3D "qemu,powernv8\0qemu,powernv\0ibm,powern= v"; const char plat_compat9[] =3D "qemu,powernv9\0ibm,powernv"; + const char plat_compat10[] =3D "qemu,powernv10\0ibm,powernv"; PnvMachineState *pnv =3D PNV_MACHINE(machine); void *fdt; char *buf; @@ -484,7 +502,10 @@ static void *pnv_dt_create(MachineState *machine) _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); _FDT((fdt_setprop_string(fdt, 0, "model", "IBM PowerNV (emulated by qemu)"))); - if (pnv_is_power9(pnv)) { + if (pnv_is_power10(pnv)) { + _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10, + sizeof(plat_compat10)))); + } else if (pnv_is_power9(pnv)) { _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, sizeof(plat_compat9)))); } else { @@ -528,8 +549,8 @@ static void *pnv_dt_create(MachineState *machine) pnv_dt_bmc_sensors(pnv->bmc, fdt); } =20 - /* Create an extra node for power management on Power9 */ - if (pnv_is_power9(pnv)) { + /* Create an extra node for power management on Power9 and Power10 */ + if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) { pnv_dt_power_mgt(fdt); } =20 @@ -578,6 +599,12 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chi= p, Error **errp) return pnv_lpc_isa_create(&chip9->lpc, false, errp); } =20 +static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) +{ + error_setg(errp, "No ISA bus!"); + return NULL; +} + static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) { return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); @@ -618,6 +645,13 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc= , uint32_t irq) object_property_set_bool(obj, true, "realized", &error_fatal); } =20 +static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) +{ + /* + * No interrupt controller yet + */; +} + static void pnv_init(MachineState *machine) { PnvMachineState *pnv =3D PNV_MACHINE(machine); @@ -822,6 +856,11 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, ui= nt32_t core_id) return (chip->chip_id << 8) | (core_id << 2); } =20 +static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) +{ + return (chip->chip_id << 8) | (core_id << 2); +} + static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { @@ -859,6 +898,27 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip= , PowerPCCPU *cpu) pnv_cpu->intc =3D NULL; } =20 +static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) +{ + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + /* Will be defined when the interrupt controller is */ + pnv_cpu->intc =3D NULL; +} + +static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) +{ + ; +} + +static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) +{ + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + pnv_cpu->intc =3D NULL; +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -886,6 +946,9 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip,= PowerPCCPU *cpu) */ #define POWER9_CORE_MASK (0xffffffffffffffull) =20 + +#define POWER10_CORE_MASK (0xffffffffffffffull) + static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 =3D PNV8_CHIP(obj); @@ -1246,6 +1309,56 @@ static void pnv_chip_power9_class_init(ObjectClass *= klass, void *data) &k->parent_realize); } =20 +static void pnv_chip_power10_instance_init(Object *obj) +{ + /* + * No controllers yet + */ + ; +} + +static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); + PnvChip *chip =3D PNV_CHIP(dev); + Error *local_err =3D NULL; + + /* XSCOM bridge is first */ + pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); + + pcc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } +} + +static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvChipClass *k =3D PNV_CHIP_CLASS(klass); + + k->chip_type =3D PNV_CHIP_POWER10; + k->chip_cfam_id =3D 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ + k->cores_mask =3D POWER10_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p10; + k->intc_create =3D pnv_chip_power10_intc_create; + k->intc_reset =3D pnv_chip_power10_intc_reset; + k->intc_destroy =3D pnv_chip_power10_intc_destroy; + k->isa_create =3D pnv_chip_power10_isa_create; + k->dt_populate =3D pnv_chip_power10_dt_populate; + k->pic_print_info =3D pnv_chip_power10_pic_print_info; + dc->desc =3D "PowerNV Chip POWER10"; + + device_class_set_parent_realize(dc, pnv_chip_power10_realize, + &k->parent_realize); +} + static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); @@ -1327,10 +1440,12 @@ static void pnv_chip_core_realize(PnvChip *chip, Er= ror **errp) &error_fatal); =20 /* Each core has an XSCOM MMIO region */ - if (!pnv_chip_is_power9(chip)) { - xscom_core_base =3D PNV_XSCOM_EX_BASE(core_hwid); - } else { + if (pnv_chip_is_power10(chip)) { + xscom_core_base =3D PNV10_XSCOM_EC_BASE(core_hwid); + } else if (pnv_chip_is_power9(chip)) { xscom_core_base =3D PNV9_XSCOM_EC_BASE(core_hwid); + } else { + xscom_core_base =3D PNV_XSCOM_EX_BASE(core_hwid); } =20 pnv_xscom_add_subregion(chip, xscom_core_base, @@ -1558,6 +1673,14 @@ static void pnv_machine_power9_class_init(ObjectClas= s *oc, void *data) mc->alias =3D "powernv"; } =20 +static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER10"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power10_v1.0"); +} + static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1595,7 +1718,19 @@ static void pnv_machine_class_init(ObjectClass *oc, = void *data) .parent =3D TYPE_PNV9_CHIP, \ } =20 +#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV10_CHIP, \ + } + static const TypeInfo types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("powernv10"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv_machine_power10_class_init, + }, { .name =3D MACHINE_TYPE_NAME("powernv9"), .parent =3D TYPE_PNV_MACHINE, @@ -1635,6 +1770,17 @@ static const TypeInfo types[] =3D { .abstract =3D true, }, =20 + /* + * P10 chip and variants + */ + { + .name =3D TYPE_PNV10_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power10_instance_init, + .instance_size =3D sizeof(Pnv10Chip), + }, + DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_i= nit), + /* * P9 chip and variants */ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 5ab75bde6cc5..2651044278ed 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -247,6 +247,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); + /* TODO: check PNV_XSCOM_EX_SIZE for p10 */ pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, pc, name, PNV_XSCOM_EX_SIZE); =20 @@ -308,6 +309,14 @@ static void pnv_core_power9_class_init(ObjectClass *oc= , void *data) pcc->xscom_ops =3D &pnv_core_power9_xscom_ops; } =20 +static void pnv_core_power10_class_init(ObjectClass *oc, void *data) +{ + PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); + + /* TODO: Use the P9 XSCOMs for now on P10 */ + pcc->xscom_ops =3D &pnv_core_power9_xscom_ops; +} + static void pnv_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -337,6 +346,7 @@ static const TypeInfo pnv_core_infos[] =3D { DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), + DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"), }; =20 DEFINE_TYPES(pnv_core_infos) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index f01d788a6545..b3d3b6e3507d 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -69,10 +69,16 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t = addr) { addr &=3D (PNV_XSCOM_SIZE - 1); =20 - if (pnv_chip_is_power9(chip)) { - return addr >> 3; - } else { + switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { + case PNV_CHIP_POWER8E: + case PNV_CHIP_POWER8: + case PNV_CHIP_POWER8NVL: return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); + case PNV_CHIP_POWER9: + case PNV_CHIP_POWER10: + return addr >> 3; + default: + g_assert_not_reached(); } } =20 @@ -307,6 +313,7 @@ static int xscom_dt_child(Object *child, void *opaque) =20 static const char compat_p8[] =3D "ibm,power8-xscom\0ibm,xscom"; static const char compat_p9[] =3D "ibm,power9-xscom\0ibm,xscom"; +static const char compat_p10[] =3D "ibm,power10-xscom\0ibm,xscom"; =20 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) { @@ -315,7 +322,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_of= fset) ForeachPopulateArgs args; char *name; =20 - if (pnv_chip_is_power9(chip)) { + if (pnv_chip_is_power10(chip)) { + reg[0] =3D cpu_to_be64(PNV10_XSCOM_BASE(chip)); + reg[1] =3D cpu_to_be64(PNV10_XSCOM_SIZE); + } else if (pnv_chip_is_power9(chip)) { reg[0] =3D cpu_to_be64(PNV9_XSCOM_BASE(chip)); reg[1] =3D cpu_to_be64(PNV9_XSCOM_SIZE); } else { @@ -332,7 +342,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_of= fset) _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); =20 - if (pnv_chip_is_power9(chip)) { + if (pnv_chip_is_power10(chip)) { + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, + sizeof(compat_p10)))); + } else if (pnv_chip_is_power9(chip)) { _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, sizeof(compat_p9)))); } else { --=20 2.21.0 From nobody Tue May 7 05:33:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 5 Dec 2019 18:45:26 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 3/5] ppc/psi: cleanup definitions Date: Thu, 5 Dec 2019 19:44:52 +0100 Message-Id: <20191205184454.10722-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191205184454.10722-1-clg@kaod.org> References: <20191205184454.10722-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5785999623497157606 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekuddguddukecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjqdffgfeufgfipdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrudehkedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.57.129 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_psi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index a360515a86f8..f15aaa5c9cc0 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -609,9 +609,12 @@ static const TypeInfo pnv_psi_power8_info =3D { #define PSIHB9_IRQ_METHOD PPC_BIT(0) #define PSIHB9_IRQ_RESET PPC_BIT(1) #define PSIHB9_ESB_CI_BASE 0x60 -#define PSIHB9_ESB_CI_VALID 1 +#define PSIHB9_ESB_CI_64K PPC_BIT(1) +#define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47) +#define PSIHB9_ESB_CI_VALID PPC_BIT(63) #define PSIHB9_ESB_NOTIF_ADDR 0x68 -#define PSIHB9_ESB_NOTIF_VALID 1 +#define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60) +#define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63) #define PSIHB9_IVT_OFFSET 0x70 #define PSIHB9_IVT_OFF_SHIFT 32 =20 --=20 2.21.0 From nobody Tue May 7 05:33:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 05 Dec 2019 13:45:40 -0500 Received: from player158.ha.ovh.net (unknown [10.109.143.72]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 50735116856 for ; Thu, 5 Dec 2019 19:45:38 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 241BECDB1560; Thu, 5 Dec 2019 18:45:32 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 4/5] ppc/pnv: add a PSI bridge model for POWER10 Date: Thu, 5 Dec 2019 19:44:53 +0100 Message-Id: <20191205184454.10722-5-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191205184454.10722-1-clg@kaod.org> References: <20191205184454.10722-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5787688474466290662 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekuddguddukecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjqdffgfeufgfipdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrudehkedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.39.154 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The POWER10 PSIHB controller is very similar to the one on POWER9. We should probably introduce a common PnvPsiXive object. The ESB page size should be changed to 64k when P10 support is ready. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 9 +++++++++ include/hw/ppc/pnv_psi.h | 2 ++ include/hw/ppc/pnv_xscom.h | 3 +++ hw/ppc/pnv.c | 27 ++++++++++++++++++++------- hw/ppc/pnv_psi.c | 25 ++++++++++++++++++++++++- 5 files changed, 58 insertions(+), 8 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index bfa61edfbabd..47b7370b27d8 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -112,6 +112,9 @@ typedef struct Pnv9Chip { typedef struct Pnv10Chip { /*< private >*/ PnvChip parent_obj; + + /*< public >*/ + Pnv9Psi psi; } Pnv10Chip; =20 typedef struct PnvChipClass { @@ -326,4 +329,10 @@ IPMIBmc *pnv_bmc_create(void); #define PNV10_XSCOM_SIZE 0x0000000400000000ull #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc000000= 00ull) =20 +#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull +#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x00060302020000= 00ull) + +#define PNV10_PSIHB_SIZE 0x0000000000100000ull +#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x00060302030000= 00ull) + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index e82df9709fb8..a044aab304ae 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -69,6 +69,8 @@ typedef struct Pnv9Psi { XiveSource source; } Pnv9Psi; =20 +#define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10" + #define PNV_PSI_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI) #define PNV_PSI_GET_CLASS(obj) \ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 790eb3d8f3b0..a40d2a2a2a98 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -106,6 +106,9 @@ typedef struct PnvXScomInterfaceClass { ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) #define PNV10_XSCOM_EC_SIZE 0x100000 =20 +#define PNV10_XSCOM_PSIHB_BASE 0x3011D00 +#define PNV10_XSCOM_PSIHB_SIZE 0x100 + extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d99cd72840be..09263ab747d8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -647,9 +647,9 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc,= uint32_t irq) =20 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) { - /* - * No interrupt controller yet - */; + Pnv10Chip *chip10 =3D PNV10_CHIP(chip); + + pnv_psi_pic_print_info(&chip10->psi, mon); } =20 static void pnv_init(MachineState *machine) @@ -1311,16 +1311,17 @@ static void pnv_chip_power9_class_init(ObjectClass = *klass, void *data) =20 static void pnv_chip_power10_instance_init(Object *obj) { - /* - * No controllers yet - */ - ; + Pnv10Chip *chip10 =3D PNV10_CHIP(obj); + + object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), + TYPE_PNV10_PSI, &error_abort, NULL); } =20 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); PnvChip *chip =3D PNV_CHIP(dev); + Pnv10Chip *chip10 =3D PNV10_CHIP(dev); Error *local_err =3D NULL; =20 /* XSCOM bridge is first */ @@ -1336,6 +1337,18 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) error_propagate(errp, local_err); return; } + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), + "bar", &error_fatal); + object_property_set_bool(OBJECT(&chip10->psi), true, "realized", + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, + &PNV_PSI(&chip10->psi)->xscom_regs); } =20 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index f15aaa5c9cc0..32e4cbdb09bb 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -539,6 +539,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Er= ror **errp) =20 static const char compat_p8[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; static const char compat_p9[] =3D "ibm,power9-psihb-x\0ibm,psihb-x"; +static const char compat_p10[] =3D "ibm,power10-psihb-x\0ibm,psihb-x"; =20 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { @@ -558,7 +559,10 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, vo= id *fdt, int xscom_offset) _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); - if (ppc->chip_type =3D=3D PNV_CHIP_POWER9) { + if (ppc->chip_type =3D=3D PNV_CHIP_POWER10) { + _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, + sizeof(compat_p10))); + } else if (ppc->chip_type =3D=3D PNV_CHIP_POWER9) { _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, sizeof(compat_p9))); } else { @@ -910,6 +914,24 @@ static const TypeInfo pnv_psi_power9_info =3D { }, }; =20 +static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvPsiClass *ppc =3D PNV_PSI_CLASS(klass); + + dc->desc =3D "PowerNV PSI Controller POWER10"; + + ppc->chip_type =3D PNV_CHIP_POWER10; + ppc->xscom_pcba =3D PNV10_XSCOM_PSIHB_BASE; + ppc->xscom_size =3D PNV10_XSCOM_PSIHB_SIZE; +} + +static const TypeInfo pnv_psi_power10_info =3D { + .name =3D TYPE_PNV10_PSI, + .parent =3D TYPE_PNV9_PSI, + .class_init =3D pnv_psi_power10_class_init, +}; + static void pnv_psi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -939,6 +961,7 @@ static void pnv_psi_register_types(void) type_register_static(&pnv_psi_info); type_register_static(&pnv_psi_power8_info); type_register_static(&pnv_psi_power9_info); + type_register_static(&pnv_psi_power10_info); } =20 type_init(pnv_psi_register_types); --=20 2.21.0 From nobody Tue May 7 05:33:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575572260; cv=none; d=zohomail.com; s=zohoarc; b=D1vG2fSLa0k7l2F5tQ4iSKFKtWF9AYaXVkl/pKu4iYOwq3tSJDvxyoFjIeiraxNe2fOOqFG914fHJGHlg+iYG6gonMAnO2Hee57CqCeeHufSgsuh/1zmamtyj1l9hbgEzbMuCxKhZSUwKX8ku0whZK92ZJuN9gRdsTmVArd+YyQ= ARC-Message-Signature: i=1; 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Thu, 05 Dec 2019 13:57:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43735) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icw8J-0006Dl-OY for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icw8H-0001ra-SB for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:47 -0500 Received: from 10.mo3.mail-out.ovh.net ([87.98.165.232]:53360) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1icw8H-0001l1-HU for qemu-devel@nongnu.org; Thu, 05 Dec 2019 13:45:45 -0500 Received: from player158.ha.ovh.net (unknown [10.108.57.178]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id DEAB3231786 for ; Thu, 5 Dec 2019 19:45:43 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 2FB54CDB158E; Thu, 5 Dec 2019 18:45:38 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 5/5] ppc/pnv: add a LPC Controller model for POWER10 Date: Thu, 5 Dec 2019 19:44:54 +0100 Message-Id: <20191205184454.10722-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191205184454.10722-1-clg@kaod.org> References: <20191205184454.10722-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5789095850069494758 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekuddguddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjqdffgfeufgfipdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecukfhppedtrddtrddtrddtpdeltddrjeeirdehtddrvddvfeenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrudehkedrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.165.232 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Same a POWER9, only the MMIO window changes. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 4 ++++ include/hw/ppc/pnv_lpc.h | 6 +++++- hw/ppc/pnv.c | 25 ++++++++++++++++++++++--- hw/ppc/pnv_lpc.c | 30 ++++++++++++++++++++++-------- 4 files changed, 53 insertions(+), 12 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 47b7370b27d8..56d1161515dd 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -115,6 +115,7 @@ typedef struct Pnv10Chip { =20 /*< public >*/ Pnv9Psi psi; + PnvLpcController lpc; } Pnv10Chip; =20 typedef struct PnvChipClass { @@ -329,6 +330,9 @@ IPMIBmc *pnv_bmc_create(void); #define PNV10_XSCOM_SIZE 0x0000000400000000ull #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc000000= 00ull) =20 +#define PNV10_LPCM_SIZE 0x0000000100000000ull +#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00060300000000= 00ull) + #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x00060302020000= 00ull) =20 diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index f659410716e1..c1ec85d5e2c5 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -31,6 +31,9 @@ #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9" #define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC) =20 +#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10" +#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LP= C) + typedef struct PnvLpcController { DeviceState parent; =20 @@ -97,6 +100,7 @@ typedef struct PnvLpcClass { struct PnvChip; =20 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); -int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset); +int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset, + uint64_t lpcm_addr, uint64_t lpcm_size); =20 #endif /* PPC_PNV_LPC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 09263ab747d8..67d0ad55b870 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -314,7 +314,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, = void *fdt) pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } =20 - pnv_dt_lpc(chip, fdt, 0); + pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); } =20 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) @@ -332,6 +332,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip,= void *fdt) if (chip->ram_size) { pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } + + pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } =20 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -601,8 +603,8 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip= , Error **errp) =20 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) { - error_setg(errp, "No ISA bus!"); - return NULL; + Pnv10Chip *chip10 =3D PNV10_CHIP(chip); + return pnv_lpc_isa_create(&chip10->lpc, false, errp); } =20 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) @@ -1315,6 +1317,8 @@ static void pnv_chip_power10_instance_init(Object *ob= j) =20 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), TYPE_PNV10_PSI, &error_abort, NULL); + object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), + TYPE_PNV10_LPC, &error_abort, NULL); } =20 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) @@ -1349,6 +1353,21 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) } pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, &PNV_PSI(&chip10->psi)->xscom_regs); + + /* LPC */ + object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "= psi", + &error_abort); + object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), + &chip10->lpc.xscom_regs); + + chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", + (uint64_t) PNV10_LPCM_BASE(chi= p)); } =20 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index dd5374c83899..18256d9ba399 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -122,26 +122,26 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, v= oid *fdt, int xscom_offset) } =20 /* POWER9 only */ -int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset) +int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_ad= dr, + uint64_t lpcm_size) { const char compat[] =3D "ibm,power9-lpcm-opb\0simple-bus"; const char lpc_compat[] =3D "ibm,power9-lpc\0ibm,lpc"; char *name; int offset, lpcm_offset; - uint64_t lpcm_addr =3D PNV9_LPCM_BASE(chip); uint32_t opb_ranges[8] =3D { 0, cpu_to_be32(lpcm_addr >> 32), cpu_to_be32((uint32_t)lpcm_addr), - cpu_to_be32(PNV9_LPCM_SIZE / 2), - cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_size / 2), + cpu_to_be32(lpcm_size / 2), cpu_to_be32(lpcm_addr >> 32), - cpu_to_be32(PNV9_LPCM_SIZE / 2), - cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_size / 2), + cpu_to_be32(lpcm_size / 2), }; uint32_t opb_reg[4] =3D { cpu_to_be32(lpcm_addr >> 32), cpu_to_be32((uint32_t)lpcm_addr), - cpu_to_be32(PNV9_LPCM_SIZE >> 32), - cpu_to_be32((uint32_t)PNV9_LPCM_SIZE), + cpu_to_be32(lpcm_size >> 32), + cpu_to_be32((uint32_t)lpcm_size), }; uint32_t lpc_ranges[12] =3D { 0, 0, cpu_to_be32(LPC_MEM_OPB_ADDR), @@ -691,6 +691,19 @@ static const TypeInfo pnv_lpc_power9_info =3D { .class_init =3D pnv_lpc_power9_class_init, }; =20 +static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "PowerNV LPC Controller POWER10"; +} + +static const TypeInfo pnv_lpc_power10_info =3D { + .name =3D TYPE_PNV10_LPC, + .parent =3D TYPE_PNV9_LPC, + .class_init =3D pnv_lpc_power10_class_init, +}; + static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); @@ -764,6 +777,7 @@ static void pnv_lpc_register_types(void) type_register_static(&pnv_lpc_info); type_register_static(&pnv_lpc_power8_info); type_register_static(&pnv_lpc_power9_info); + type_register_static(&pnv_lpc_power10_info); } =20 type_init(pnv_lpc_register_types) --=20 2.21.0