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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GpVUc819EtKJmXmcFCtrJ6j6UAZ0zHMd3RprAICGD1Q=; b=BXOWQtpMs2xHzrkqMezlvx/Rx3H/5spS7nryedTFylz+s3IAZXQZrzLW5SPwAyoGbr rCmrLe8aCGEw8YbxfhE245cEuuqL8VG0oSUXW8ZJ10ntF6I4VaBOzWxi51q4nRpzGJa2 HIO4xew7OX+onjwGnQkhlD9N8ExoaLR/bJ6O6z0pixDwzLMP3i79vH+DyrlhiOfT1cIn MvBMP0GZkiem2Dsg1GiGRHb/8yWsFxtl2Ey2Ldl3pETgfZuvBBGYxmIBt+e717Akz680 F6OhH2+T2KNSvS6kpL5YXieVggjlKNutqvxZcqgO1woTZWAQgAFdF3z0N4Ly24dvRiWe cE8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GpVUc819EtKJmXmcFCtrJ6j6UAZ0zHMd3RprAICGD1Q=; b=eKbqVsPnkdukHhkJRSanY9mCpqJf80dZJtniZQLEHrqUo/sOGcp+VsqCsiK6KRle9I eJsbHtQOaTRKZr+Xr4O0RKvgfjvHbZyu17NYG+8Bo42ddz2dFlsHZcuppka/cRgYTsJt NZvoFgEQ7+NApsgylkGohDl3ufk4UqfhxWwafZj99+KERmH+WNg5Sc7tOnhSNM4a9nCn Oe6yXo24Ald3YwTGn9XJ4cTaBooFZV1xtq/5+mKy/pGgHiHn0pWmALvi/V57mxGxkM/T wwXObk302rPkeX+O81wqS9VQ2F04cYK38KvceN2haLXysYh4dL3FpPwswLBmoo64KO8F V4Mw== X-Gm-Message-State: APjAAAWwwEIVKtdSde/bDcdeUxf1MU0NyBi3ZOzpIhgIG9M8/MXJgJ8U 9X8gNWDfPBf9VJQrP1ltAF03ubvWXQI= X-Google-Smtp-Source: APXvYqwO+fX9D8kFXDXW+MLJYBVpr1S8AEqabpKa9FJimxt8juYiBVMYryGN0Ew3on1ZAa6TDqn/gw== X-Received: by 2002:a62:e914:: with SMTP id j20mr266652pfh.245.1575413616536; Tue, 03 Dec 2019 14:53:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/11] cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN Date: Tue, 3 Dec 2019 14:53:23 -0800 Message-Id: <20191203225333.17055-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In target/arm we will shortly have "too many" mmu_idx. The current minimum barrier is caused by the way in which tlb_flush_page_by_mmuidx is coded. We can remove this limitation by allocating memory for consumption by the worker. Let us assume that this is the unlikely case, as will be the case for the majority of targets which have so far satisfied the BUILD_BUG_ON, and only allocate memory when necessary. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/cputlb.c | 167 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 132 insertions(+), 35 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 98221948d6..0c2adb93ea 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -447,28 +447,29 @@ static void tlb_flush_page_locked(CPUArchState *env, = int midx, } } =20 -/* As we are going to hijack the bottom bits of the page address for a - * mmuidx bit mask we need to fail to build if we can't do that +/** + * tlb_flush_page_by_mmuidx_async_0: + * @cpu: cpu on which to flush + * @addr: page of virtual address to flush + * @idxmap: set of mmu_idx to flush + * + * Helper for tlb_flush_page_by_mmuidx and friends, flush one page + * at @addr from the tlbs indicated by @idxmap from @cpu. */ -QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN); - -static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu, - run_on_cpu_data data) +static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu, + target_ulong addr, + uint16_t idxmap) { CPUArchState *env =3D cpu->env_ptr; - target_ulong addr_and_mmuidx =3D (target_ulong) data.target_ptr; - target_ulong addr =3D addr_and_mmuidx & TARGET_PAGE_MASK; - unsigned long mmu_idx_bitmap =3D addr_and_mmuidx & ALL_MMUIDX_BITS; int mmu_idx; =20 assert_cpu_is_self(cpu); =20 - tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n", - addr, mmu_idx_bitmap); + tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%x\n", addr, idxmap); =20 qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - if (test_bit(mmu_idx, &mmu_idx_bitmap)) { + if ((idxmap >> mmu_idx) & 1) { tlb_flush_page_locked(env, mmu_idx, addr); } } @@ -477,22 +478,75 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tb_flush_jmp_cache(cpu, addr); } =20 +/** + * tlb_flush_page_by_mmuidx_async_1: + * @cpu: cpu on which to flush + * @data: encoded addr + idxmap + * + * Helper for tlb_flush_page_by_mmuidx and friends, called through + * async_run_on_cpu. The idxmap parameter is encoded in the page + * offset of the target_ptr field. This limits the set of mmu_idx + * that can be passed via this method. + */ +static void tlb_flush_page_by_mmuidx_async_1(CPUState *cpu, + run_on_cpu_data data) +{ + target_ulong addr_and_idxmap =3D (target_ulong) data.target_ptr; + target_ulong addr =3D addr_and_idxmap & TARGET_PAGE_MASK; + uint16_t idxmap =3D addr_and_idxmap & ~TARGET_PAGE_MASK; + + tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); +} + +typedef struct { + target_ulong addr; + uint16_t idxmap; +} TLBFlushPageByMMUIdxData; + +/** + * tlb_flush_page_by_mmuidx_async_2: + * @cpu: cpu on which to flush + * @data: allocated addr + idxmap + * + * Helper for tlb_flush_page_by_mmuidx and friends, called through + * async_run_on_cpu. The addr+idxmap parameters are stored in a + * TLBFlushPageByMMUIdxData structure that has been allocated + * specifically for this helper. Free the structure when done. + */ +static void tlb_flush_page_by_mmuidx_async_2(CPUState *cpu, + run_on_cpu_data data) +{ + TLBFlushPageByMMUIdxData *d =3D data.host_ptr; + + tlb_flush_page_by_mmuidx_async_0(cpu, d->addr, d->idxmap); + g_free(d); +} + void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t i= dxmap) { - target_ulong addr_and_mmu_idx; - tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%" PRIx16 "\n", addr, idxmap); =20 /* This should already be page aligned */ - addr_and_mmu_idx =3D addr & TARGET_PAGE_MASK; - addr_and_mmu_idx |=3D idxmap; + addr &=3D TARGET_PAGE_MASK; =20 - if (!qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work, - RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); + if (qemu_cpu_is_self(cpu)) { + tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); + } else if (idxmap < TARGET_PAGE_SIZE) { + /* + * Most targets have only a few mmu_idx. In the case where + * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid + * allocating memory for this operation. + */ + async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_1, + RUN_ON_CPU_TARGET_PTR(addr | idxmap)); } else { - tlb_flush_page_by_mmuidx_async_work( - cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); + TLBFlushPageByMMUIdxData *d =3D g_new(TLBFlushPageByMMUIdxData, 1); + + /* Otherwise allocate a structure, freed by the worker. */ + d->addr =3D addr; + d->idxmap =3D idxmap; + async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_2, + RUN_ON_CPU_HOST_PTR(d)); } } =20 @@ -504,17 +558,36 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, uint16_t idxmap) { - const run_on_cpu_func fn =3D tlb_flush_page_by_mmuidx_async_work; - target_ulong addr_and_mmu_idx; - tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); =20 /* This should already be page aligned */ - addr_and_mmu_idx =3D addr & TARGET_PAGE_MASK; - addr_and_mmu_idx |=3D idxmap; + addr &=3D TARGET_PAGE_MASK; =20 - flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); - fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); + /* + * Allocate memory to hold addr+idxmap only when needed. + * See tlb_flush_page_by_mmuidx for details. + */ + if (idxmap < TARGET_PAGE_SIZE) { + flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1, + RUN_ON_CPU_TARGET_PTR(addr | idxmap)); + } else { + CPUState *dst_cpu; + + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu !=3D src_cpu) { + TLBFlushPageByMMUIdxData *d + =3D g_new(TLBFlushPageByMMUIdxData, 1); + + d->addr =3D addr; + d->idxmap =3D idxmap; + async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2, + RUN_ON_CPU_HOST_PTR(d)); + } + } + } + + tlb_flush_page_by_mmuidx_async_0(src_cpu, addr, idxmap); } =20 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) @@ -526,17 +599,41 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUStat= e *src_cpu, target_ulong addr, uint16_t idxmap) { - const run_on_cpu_func fn =3D tlb_flush_page_by_mmuidx_async_work; - target_ulong addr_and_mmu_idx; - tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); =20 /* This should already be page aligned */ - addr_and_mmu_idx =3D addr & TARGET_PAGE_MASK; - addr_and_mmu_idx |=3D idxmap; + addr &=3D TARGET_PAGE_MASK; =20 - flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); - async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_= idx)); + /* + * Allocate memory to hold addr+idxmap only when needed. + * See tlb_flush_page_by_mmuidx for details. + */ + if (idxmap < TARGET_PAGE_SIZE) { + flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1, + RUN_ON_CPU_TARGET_PTR(addr | idxmap)); + async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_1, + RUN_ON_CPU_TARGET_PTR(addr | idxmap)); + } else { + CPUState *dst_cpu; + TLBFlushPageByMMUIdxData *d; + + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu !=3D src_cpu) { + d =3D g_new(TLBFlushPageByMMUIdxData, 1); + d->addr =3D addr; + d->idxmap =3D idxmap; + async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2, + RUN_ON_CPU_HOST_PTR(d)); + } + } + + d =3D g_new(TLBFlushPageByMMUIdxData, 1); + d->addr =3D addr; + d->idxmap =3D idxmap; + async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_2, + RUN_ON_CPU_HOST_PTR(d)); + } } =20 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575414542; cv=none; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vu6ogLPsJVc9JMwH067ih3gg/dp3iZ1trwEWoF/7t8M=; b=yWhlzSTj6kVcbNTGlCIMl6monUDG4Ac9Td0llETvm0RevFBHmhK2x+Dp86EvPHIgE4 IK4PmufTmN//ZgZzK4DkVJ8kH57ixQCHGR0zQ3l0+fAOV8g4Glq+pHSBnXQejIBtH1Js 8B1d3shdJ+Xp3hmkC09ujmMZHrKXRj8ztL4S1RdZ4LmLOS/SLjEjw5+L+qaV2PoI23wX 8elJCddzCrPJr5LMyE/iVQATVjRq3XJiBApczBlKpcenKZQQ674h7hT7EmLDovvWJMVo OBx4EpMCxhyjgDY4qvh9Hlsw2bbx5x9/rT2y737oMmxSPpqoP2MJq6cFdjDdIO0riT/z rCfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vu6ogLPsJVc9JMwH067ih3gg/dp3iZ1trwEWoF/7t8M=; b=QgpL78PfheZayRVx6kTOByQNbgK1AlNBpsBL3Fsp35fLb4z9eBz0d1WaP0Wkz8GvuJ Ew43QyHq9D0A6V2jKhWtOMkoyAv9NKZMdFFO7MZo15YlO+DChcOYkjmlBrRQ/uMmFXW2 b7OpEXLQaozsxbpe/6vyY73G8Q0XCcCJs6DQ+bWla/RJECAt84kQy1gOIHLfH4XozP8R ymYwi2vvMq7lPWRDucwZUvUPqI/CyFe9x575tH2HYhr+zHeLaV22Retw/nqgzfGlTEvG faQO6DTEyuYKUAl/Rw/7Ziho6+MyYGftygpALl56zRFybMwAt9ZcaCFymQ1KPPUz+44p 1Xnw== X-Gm-Message-State: APjAAAX/Zw8hOFixD0HMPfebtTveBQiVZRednmevYujEjlYJOV/0bt5K DyNgLhH3xDq5btLg8EGz654augUUiN8= X-Google-Smtp-Source: APXvYqy89O23x/eC+YnGuksZRxhqnAZKKc8dl/r2bd4Tm09wkZ5QW3CLobuxgUexODgR40WZXzS0sA== X-Received: by 2002:a62:4e4e:: with SMTP id c75mr308764pfb.144.1575413617804; Tue, 03 Dec 2019 14:53:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1 Date: Tue, 3 Dec 2019 14:53:24 -0800 Message-Id: <20191203225333.17055-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use a common predicate for querying stage1-ness. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 11 +++++++++++ target/arm/helper.c | 8 +++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 49dac2a677..850f204f14 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1034,6 +1034,17 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMSta= te *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif =20 +static inline bool arm_mmu_idx_is_stage1(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + return true; + default: + return false; + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index f3785d5ad6..fdb86ea427 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3212,8 +3212,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, bool take_exc =3D false; =20 if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) - && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 - || mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { + && arm_mmu_idx_is_stage1(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -9159,8 +9158,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } } =20 - if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1(mmu_idx)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -9469,7 +9467,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && + if (arm_mmu_idx_is_stage1(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575415291; cv=none; d=zohomail.com; s=zohoarc; b=BXwHRvUI2iv+aXc4CN9TF32+2xP5U/80GxEdeTsxjRZxpMwhasJSAIhp1Yf6yWflh89oX1QJg+O3LOh+5svsYYbSSqSOJC66geizAewADCe+dwZ1SHnwJ3dAgK08UxNsLxXVLkrwu1j9fAW8I2fm+ZTiLk/UTYNl7huMajg0uSs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575415291; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=SPzn+VTOyMQJa+XMTau4HeWDSYCIOZdHOCWei3+VPg4=; b=YOnG1gPfG7iqpRx5zDBiN7HxL2a0DaSL8tAtVMgS4dJcRsAcN/CYYe94foAL0L/gUHGX+D137THxRCJL/vF0F4oghrdl6pt4SNOrMmPBEtUvl16kJExilvXXeIysEYGAMqGPUWVzgI8b/6pk/gSDUm1EI773nD9Ult/yhX7F4J4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575415291642883.6856040665456; Tue, 3 Dec 2019 15:21:31 -0800 (PST) Received: from localhost ([::1]:60322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHU2-000108-6I for importer@patchew.org; Tue, 03 Dec 2019 18:21:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58301) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH39-0002aP-Ep for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH37-0006Op-88 for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:43 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:46207) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH36-0006Le-Tw for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:41 -0500 Received: by mail-pf1-x441.google.com with SMTP id y14so2106022pfm.13 for ; Tue, 03 Dec 2019 14:53:40 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SPzn+VTOyMQJa+XMTau4HeWDSYCIOZdHOCWei3+VPg4=; b=cl6tTLRQFOQdhgq5Q6NZ7uYAEDC3Mbt/eAS5tnOu+JBpV73JXyR6IrLc5/98zHlBnd C5RYxlYZP9EvW1sy2Ho1dXZLkBcOi64xAR/MzG1bNVnM/JinbQ+J7vdEKdlulpJQJGj7 iNpAfVwAt4izyCwT9wrL94IKDLht5NXovFy72zFYCxp6oV81xW8oTBW5R3URm1ItX4cf kofZrx3ElQRDVfTKdCvnaN0z3lJNX57ot4Qn0ZK6e68oQ3v5Ak2wymgR07N8AlgV19Ct FANhVgJa1V7NsDdG8AuYn9Uv635+uZpsC026gLCT4fU+Pz3ZyuGJmc0yZXI12O1NAr4I p33Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SPzn+VTOyMQJa+XMTau4HeWDSYCIOZdHOCWei3+VPg4=; b=b+KumRBGm6ayyJBhpN+XMlHYGdXthe0aa5keRBzfEAKBEUa1UwgDuI3QFVlbYOEHvE J+WM9sSYZAEvHALBgmbMh+5BrU0eHnS+qBfSrfarg9CNbFr7inXIcg13/l0Pf/OrT1Yi h0KbmNI8/8NPllJanm+mqgcd5dijx3oTlPp5I3FYezEiQ2s5x6AGXHimVGQ8H4swm83x F6IOabETZwHL3zm5VCPIjdvjpNbRXtmzjo9O0w5bZQg9+8E+epXFQafUFwNW+S6ZOXeO BtcVlfF7nDuPOVDD8ZtheeIp1vpD6/e0X1Iraa9IBA4N/L0MOVPKqQzH8s1SLg975lvI 3oNw== X-Gm-Message-State: APjAAAUM3BN3Pdb0c6BL58UTfFcdx+wnPunphF8H1t4zWvAC/TSgc9la hFP94DnUKgXbn0YsdU1KfxBzCySHVUs= X-Google-Smtp-Source: APXvYqzPEg/8bhlt+aGndQlelRWyEr0YLkkCoWHHnSA65GjO8sO87eLoTosxyqLwCjrUamS9nuiO4g== X-Received: by 2002:aa7:9d9c:: with SMTP id f28mr328728pfq.20.1575413619122; Tue, 03 Dec 2019 14:53:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/11] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Date: Tue, 3 Dec 2019 14:53:25 -0800 Message-Id: <20191203225333.17055-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To implement PAN, we will want to swap, for short periods of time, to a different privileged mmu_idx. In addition, we cannot do this with flushing alone, because the AT* instructions have both PAN and PAN-less versions. Add the ARMMMUIdx*_PAN constants where necessary next to the corresponding ARMMMUIdx* constant. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 35 +++++++++++++-------- target/arm/internals.h | 9 ++++++ target/arm/helper.c | 63 +++++++++++++++++++++++++++++++------- target/arm/translate-a64.c | 2 ++ target/arm/translate.c | 2 ++ 6 files changed, 88 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 18ac562346..d593b60b28 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 9 +#define NB_MMU_MODES 12 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22935e4433..22c5706835 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2715,20 +2715,22 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * 5. we want to be able to use the TLB for accesses done as part of a * stage1 page table walk, rather than having to walk the stage2 page * table over and over. + * 6. we need separate EL1/EL2 mmu_idx for handling the Priviledged Access + * Never (PAN) bit within PSTATE. * * This gives us the following list of cases: * * NS EL0 (aka NS PL0) EL1&0 stage 1+2 - * NS EL1 (aka NS PL1) EL1&0 stage 1+2 + * NS EL1 (aka NS PL1) EL1&0 stage 1+2 (+PAN) * NS EL0 EL2&0 - * NS EL2 EL2&0 + * NS EL2 EL2&0 (+PAN) * NS EL2 (aka NS PL2) * S EL0 (aka S PL0) - * S EL1 (not used if EL3 is 32 bit) + * S EL1 (not used if EL3 is 32 bit) (+PAN) * S EL3 (aka S PL1) * NS EL0&1 stage 2 * - * for a total of 9 different mmu_idx. + * for a total of 12 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2783,19 +2785,22 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_EL20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_EL20_0 =3D 1 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_EL10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_1_PAN =3D 3 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_E2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_EL20_2 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_EL20_2 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_EL20_2_PAN =3D 6 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_SE0 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE1 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE0 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1_PAN =3D 9 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 10 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_Stage2 =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 11 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2803,6 +2808,7 @@ typedef enum ARMMMUIdx { */ ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -2828,10 +2834,13 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(EL10_0), TO_CORE_BIT(EL20_0), TO_CORE_BIT(EL10_1), + TO_CORE_BIT(EL10_1_PAN), TO_CORE_BIT(E2), TO_CORE_BIT(EL20_2), + TO_CORE_BIT(EL20_2_PAN), TO_CORE_BIT(SE0), TO_CORE_BIT(SE1), + TO_CORE_BIT(SE1_PAN), TO_CORE_BIT(SE3), TO_CORE_BIT(Stage2), =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 850f204f14..2408953031 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -843,12 +843,16 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_= idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: case ARMMMUIdx_EL20_0: case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: + case ARMMMUIdx_SE1_PAN: return true; default: return false; @@ -861,10 +865,13 @@ static inline bool regime_is_secure(CPUARMState *env,= ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: case ARMMMUIdx_EL20_0: case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -874,6 +881,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) return false; case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: + case ARMMMUIdx_SE1_PAN: case ARMMMUIdx_SE3: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: @@ -1039,6 +1047,7 @@ static inline bool arm_mmu_idx_is_stage1(ARMMMUIdx mm= u_idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index fdb86ea427..4e3fe00316 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -671,6 +671,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_1_PAN | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2); } @@ -682,6 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_1_PAN | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2); } @@ -2660,6 +2662,7 @@ static int gt_phys_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_EL20_0: case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2671,6 +2674,7 @@ static int gt_virt_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_EL20_0: case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3288,7 +3292,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUId= x_EL10_1) { + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || + mmu_idx =3D=3D ARMMMUIdx_EL10_1 || + mmu_idx =3D=3D ARMMMUIdx_EL10_1_PAN) { format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |=3D arm_current_el(env) =3D=3D 2; @@ -3746,7 +3752,9 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env,= const ARMCPRegInfo *ri, if ((arm_hcr_el2_eff(env) & HCR_E2H) && extract64(raw_read(env, ri) ^ value, 48, 16)) { tlb_flush_by_mmuidx(env_cpu(env), - ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0); + ARMMMUIdxBit_EL20_2 | + ARMMMUIdxBit_EL20_2_PAN | + ARMMMUIdxBit_EL20_0); } raw_write(env, ri, value); } @@ -3764,6 +3772,7 @@ static void vttbr_write(CPUARMState *env, const ARMCP= RegInfo *ri, if (raw_read(env, ri) !=3D value) { tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_1_PAN | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2); raw_write(env, ri, value); @@ -4124,12 +4133,18 @@ static int vae1_tlbmask(CPUARMState *env) { /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; + return ARMMMUIdxBit_SE1 | + ARMMMUIdxBit_SE1_PAN | + ARMMMUIdxBit_SE0; } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; + return ARMMMUIdxBit_EL20_2 | + ARMMMUIdxBit_EL20_2_PAN | + ARMMMUIdxBit_EL20_0; } else { - return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; + return ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_1_PAN | + ARMMMUIdxBit_EL10_0; } } =20 @@ -4165,14 +4180,23 @@ static int vmalle1_tlbmask(CPUARMState *env) * Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; + return ARMMMUIdxBit_SE1 | + ARMMMUIdxBit_SE1_PAN | + ARMMMUIdxBit_SE0; } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; + return ARMMMUIdxBit_EL20_2 | + ARMMMUIdxBit_EL20_2_PAN | + ARMMMUIdxBit_EL20_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; + return ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_1_PAN | + ARMMMUIdxBit_EL10_0 | + ARMMMUIdxBit_Stage2; } else { - return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; + return ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_1_PAN | + ARMMMUIdxBit_EL10_0; } } =20 @@ -4188,7 +4212,9 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static int vae2_tlbmask(CPUARMState *env) { if (arm_hcr_el2_eff(env) & HCR_E2H) { - return ARMMMUIdxBit_EL20_0 | ARMMMUIdxBit_EL20_2; + return ARMMMUIdxBit_EL20_0 | + ARMMMUIdxBit_EL20_2 | + ARMMMUIdxBit_EL20_2_PAN; } else { return ARMMMUIdxBit_E2; } @@ -9080,6 +9106,7 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx= mmu_idx) switch (mmu_idx) { case ARMMMUIdx_EL20_0: case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -9088,10 +9115,13 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUI= dx mmu_idx) case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_SE1: + case ARMMMUIdx_SE1_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -9207,6 +9237,8 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu= _idx) return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_EL10_1: return ARMMMUIdx_Stage1_E1; + case ARMMMUIdx_EL10_1_PAN: + return ARMMMUIdx_Stage1_E1_PAN; default: return mmu_idx; } @@ -9253,6 +9285,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) return false; case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: g_assert_not_reached(); } } @@ -11145,7 +11178,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || + mmu_idx =3D=3D ARMMMUIdx_EL10_1 || + mmu_idx =3D=3D ARMMMUIdx_EL10_1_PAN) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11672,10 +11707,13 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_SE0: return 0; case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: case ARMMMUIdx_SE1: + case ARMMMUIdx_SE1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: return 2; case ARMMMUIdx_SE3: return 3; @@ -11886,11 +11924,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, /* TODO: ARMv8.2-UAO */ switch (mmu_idx) { case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: case ARMMMUIdx_SE1: + case ARMMMUIdx_SE1_PAN: /* TODO: ARMv8.3-NV */ flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); break; case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: /* TODO: ARMv8.4-SecEL2 */ /* * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20_0 is diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fe492bea90..b5c7bc2d76 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -124,9 +124,11 @@ static int get_a64_user_mem_index(DisasContext *s) */ switch (useridx) { case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: useridx =3D ARMMMUIdx_EL10_0; break; case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: useridx =3D ARMMMUIdx_EL20_0; break; case ARMMMUIdx_SE1: diff --git a/target/arm/translate.c b/target/arm/translate.c index b7f726e733..47a374b53d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -155,10 +155,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cInc5a19jU6WxGPEpK5KzVQbF4VsjSynVXIzjEULPhE=; b=xS7z3I3aUvdGgcrTGD4qP+BY8TO1wrSKD/eSM1S3Kt34LxYnokHUQaT/dO4ycglfdE cjZfPTqgnEZY7YWCIbYeC88KESjVbg8JAYMvifnOgkZOptcBZIubkKQF6sZ1nUlP1Dih CHFNYSwOx5X5aI7I5xEP9tdTZjr7QADRaqDlTUXn3N8p8IGSBxCzZstGC1uxhZ1Kedxd qoWxBZ0uFbwuJ+ni0kyWTCV22bgfdpBuMGAZjutRO+gHzHfi/DuiGDXGbKUQIyAmnnUS D6YQlc2K32zTQNc/qMIBBXOZwYaoYL7v0wLFceXneT5+HCdsWYcDL09CAhySZYftAADz 026w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cInc5a19jU6WxGPEpK5KzVQbF4VsjSynVXIzjEULPhE=; b=R7mgLxV3qjJLrIV263iJ3xXTZ+ARNpqehZ/MteGu8TOz8JaKO/FpbCn+7ngBNBrp+D fg2pPZ870jqE9IHhzBGRr5zYx8ADhAmnXUoOBBrIMlmxnUO4ddkH4jTTLiUuW3YRNxwu iC9eQb97l3VPqA1Af+vG2xLjDWMK6XbGuxX7X2oEp8v0C4JaF6bvd97VeDeAQ0A1P8oC U7lO/G1yApiEJULaWBxwGzxB+0+7MLciWqx+jFlW6Q9v+VDNhoPGYNrCi6TCtIfMEzR6 unQLWbJGmyCzeBxpyz0RZU99Ct5tmxPDwjMHqqLljBHVwzm9TcT13KtREU073bu9CtYB yOkA== X-Gm-Message-State: APjAAAX1D8wkP8lG3l/SsGkdYREQfcE9ZAEMlTst1m9jHcDigD2HBgYK zZTUnQL8+EU7PxzALjhLy61hDxZq934= X-Google-Smtp-Source: APXvYqztNttbmbt/BiahwMrxyBDKq86VegofgBGvLajYVB8hUwSEvdsPiBw31jgePM7ueLOxAAhyQw== X-Received: by 2002:aa7:870c:: with SMTP id b12mr320615pfo.82.1575413620282; Tue, 03 Dec 2019 14:53:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/11] target/arm: Reduce CPSR_RESERVED Date: Tue, 3 Dec 2019 14:53:26 -0800 Message-Id: <20191203225333.17055-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since v8.0, the CPSR_RESERVED bits have been allocated. We are not yet implementing ARMv8.4-DIT; retain CPSR_RESERVED, since that overlaps with our current hack for AA32 single step. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22c5706835..49dc436e5e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1149,12 +1149,16 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in +/* + * Note that the RESERVED bits include bit 21, which is PSTATE_SS in * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, * where it is live state but not accessible to the AArch32 code. + * + * TODO: With ARMv8.4-DIT, bit 21 is DIT in AArch32 (bit 24 for AArch64). + * We will need to move AArch32 SS somewhere else at that point. */ -#define CPSR_RESERVED (0x7U << 21) +#define CPSR_RESERVED (1U << 21) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575414348; cv=none; d=zohomail.com; s=zohoarc; b=eUyeDueiWO9H8rM79DWVreKnp64dHWjoThVzTgDqUwLZlsnWPOZra9zVvb+Y+tz1xIsQdhyzMWNE4ocfftoBlOjayuxs3DAwHSPUhtefqA3H06B0HN4a4CcA/C8CHVI90yu9UyHZkVcWmrjPx/EEKlahebh7nkCqYeo5BX544Bg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575414348; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=by8LmgJPpfyV7BVjX7xy3BTMjxptfd86p6Ff5RwnARA=; b=hFp2wyd1fUXPAfiB/WY/61Ocu1hpzWGwHKPf9P9yAy93L1NyRiMSmM+rWwW50saAs20rU/EA27agLB+7b1nqlygp5zNHqWLeqCXbGr7KQ/QehJI62llrlihL/ytWe22mK5T8jsNgJDQL2ZpwY1aauRxG/yHc+pG4qxtvD94UzTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575414348328925.952886313526; Tue, 3 Dec 2019 15:05:48 -0800 (PST) Received: from localhost ([::1]:60152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHEo-0008WQ-4g for importer@patchew.org; Tue, 03 Dec 2019 18:05:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3H-0002bl-CM for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH39-0006Vx-C2 for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:44 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:41189) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH38-0006Ry-RX for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:42 -0500 Received: by mail-pl1-x643.google.com with SMTP id bd4so2278388plb.8 for ; Tue, 03 Dec 2019 14:53:42 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=by8LmgJPpfyV7BVjX7xy3BTMjxptfd86p6Ff5RwnARA=; b=GMuGC4V7qbLrXldRswf9I4Cz9sQCnBllz+QBDFO5rKgczlx8XsGS42O+Nx3PgjwkWw RHaiip+5E3aVI5FNn4qBPdttJZVjudkgWu6WOTcrPNe7Rk+bosKLCCkrCuZHQYYVKsM3 3Y1vj9WMNikaYWrI3RLkngPPRh9CqlHtZVDHBGLB4dmN+ms67w7vWLktOsMIAWGonAWr bgDre4oCrFRf8UJUuDeVETlKInZmN3OQEM9LA3ksrnpoiNkixJgjmPVvqvpGCKXO/y+d lDj56iymXp7zOgt5nmSx2H6+PGgpxexY2oRm2T60+Tz6ZRBm/Wgkiy+pwmghblx8dBc5 Y+7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=by8LmgJPpfyV7BVjX7xy3BTMjxptfd86p6Ff5RwnARA=; b=BFDd7MLIGcLa00WjxrXFGRmb30cYzN45mctuXH0wFAOwl4j6puZxDpByJUWlFU0ZK4 g6gWHsYE+NZ3YFaluJWhE+hgsS+J5LeNVmUFzCnFbPwDESqLWbCNvISnQcRV0KqzGAvn /4qeGNVijhnM4etamcv07gwoQPh8BBVGT5oPkH4cDz5dGNgbrpYigO/kWm4Gk1PzysB0 2iGgY3sIoFFVOIqAr94w7PmNS+VrB121uLz4XIz3RxPhdtdtNFGhsPUxONUA3wiYhPM4 zHvuCV/HkaVFPHTn1H28YOhmg3ZA2FkdCaBKb4mLAtDNSs0L59WXtrx6suXM5YvOQoHD lKRQ== X-Gm-Message-State: APjAAAUqAfu+Q5sEngAuRfG42PN26LFdli8Gb1RxLSsHr/I5wWZ1qOxL VW+tLb5kq8pU8Yd1KeF6fkGGyA2a4nw= X-Google-Smtp-Source: APXvYqyUfz/m6dxpoYyLwAvkMX0j6Jn4wqJsm8WtdrWaHFFS1yhKyNNELcmV2KwF10DRUsmcVGM+4Q== X-Received: by 2002:a17:90a:a44:: with SMTP id o62mr8242690pjo.80.1575413621392; Tue, 03 Dec 2019 14:53:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1 Date: Tue, 3 Dec 2019 14:53:27 -0800 Message-Id: <20191203225333.17055-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 49dc436e5e..170dd5b124 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1694,6 +1694,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) =20 +FIELD(ID_MMFR3, CMAINTVA, 0, 4) +FIELD(ID_MMFR3, CMAINTSW, 4, 4) +FIELD(ID_MMFR3, BPMAINT, 8, 4) +FIELD(ID_MMFR3, MAINTBCST, 12, 4) +FIELD(ID_MMFR3, PAN, 16, 4) +FIELD(ID_MMFR3, COHWALK, 20, 4) +FIELD(ID_MMFR3, CMEMSZ, 24, 4) +FIELD(ID_MMFR3, SUPERSEC, 28, 4) + FIELD(ID_MMFR4, SPECSEI, 0, 4) FIELD(ID_MMFR4, AC2, 4, 4) FIELD(ID_MMFR4, XNX, 8, 4) @@ -3401,6 +3410,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const= ARMISARegisters *id) return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) !=3D 0; +} + +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; +} + /* * 64-bit feature tests via id registers. */ @@ -3550,6 +3569,16 @@ static inline bool isar_feature_aa64_lor(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; } =20 +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; +} + +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575415481; cv=none; d=zohomail.com; s=zohoarc; b=Du7sdw7tBklVeJYQuYNQkZ9Go1N0IgT4/CF27u9XXXu+kwpBXpTjrVuq3tFP49KX3wa1HqNMNkivM7QkItjA4dCOZcgY9a5fsxxhvxKOLyC9FBcnHIrnvs5tPYyRl4s20JNCYvMFPdNdDRU1nKiNMHAHs+sV26lGRrelCpB5YXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575415481; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=9AspWquiqmrjmokhsjjXAIAYddZO8ijvxyMTH0rKsT4=; b=WpwjXUuKzg9S8nECspTn6Urd4Sfb6088+qo4MB+odei7wdh1VQ8XrRzp2V0UUUXiY5KngPTZsLcsATidK7Jkkd5BrwPxGt93h3Iqvle77zUZVzsASwPJUXbaU8HARvDTLUsnEVC//TPhWrEtkrNuGvJBCvictxhaMGPZeX5GZ2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157541548113473.88010020739193; Tue, 3 Dec 2019 15:24:41 -0800 (PST) Received: from localhost ([::1]:60360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHX5-0002H6-Ss for importer@patchew.org; Tue, 03 Dec 2019 18:24:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58424) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3R-0002fA-I6 for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH3H-0006dN-Bc for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:56 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:46369) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH3A-0006Wb-FO for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:53:44 -0500 Received: by mail-pl1-x641.google.com with SMTP id k20so2268231pll.13 for ; Tue, 03 Dec 2019 14:53:43 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9AspWquiqmrjmokhsjjXAIAYddZO8ijvxyMTH0rKsT4=; b=TRh6x+GxhqCDb8UUvIybqVpfm0N1XLS/bBqzZZvb+XYzetMcaNvXmq9AhE5q7QVkrf Hy76zd/nVEaeq3IDtdmwSFKXd49YAezuKD97ShCEiN/e6C9nDVQIWspWwMfUT3KJD1Xn dS3GKRk2wEgRK+FYP+Dw1aoJnbwM+znVoOnPDzg8eyq6P9Pmcp2LggGXUjE2uJXeQDf4 AHs58DWiTxnEJwu/uhGLeTGVju6gburY7S/zINoPhaI+ONw72XD/LL5ppK+qH2jVqC83 NCI65qjq63kEq+9NhQnSq6tNvGO84jHLG+Bn2OTv/mIXSXhsfjjgkx7g27LaikN2e6pj LlfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9AspWquiqmrjmokhsjjXAIAYddZO8ijvxyMTH0rKsT4=; b=MBl8HhKs69a47bZkc7tb+vXlRIHQnsyA5zKIS2DmmuWSeiAB7aYo52rTegW1m8DSbA ZJgNOQDO0072WIEZvHS0TTnzMkhCDBeBuQJclyaZh5Df+ahCB9lwbViXLUjvKdWJD52P Jvziww6msHlEjGfYsS4KPKGp1aJjcyEY0Ot0zeJjdPw1MQ5iwfaxBgmy+pJAxGlLU9LL tRoBkJ+o71IEyPHiqrsavXSM4X9/5GYD82bIRO1saEHtJ4elGQNk3QlaRYdEE+Q2MEP+ psLCbsoD97FwEggUwTUNClDyjecw+s0HCItDRSH4N6RY6ga7UldhCDmdAjqomFFsg/I6 RxeA== X-Gm-Message-State: APjAAAVRt17rPHXjBFzYi79YUOrzN31fa1KzPqgMH44cqpihrqwYmJqd Y1iXw5+VaQYc+05acvJYXSaX6K2YimU= X-Google-Smtp-Source: APXvYqxSM55ZsmKw6xGoNdwrlm50u45BNK5tlpteDRGvldW+jBNBz5K2LHi+P+L2XAkotvfxAvx8NQ== X-Received: by 2002:a17:902:a502:: with SMTP id s2mr325104plq.327.1575413622675; Tue, 03 Dec 2019 14:53:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/11] target/arm: Update MSR access for PAN Date: Tue, 3 Dec 2019 14:53:28 -0800 Message-Id: <20191203225333.17055-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For aarch64, there's a dedicated msr (imm, reg) insn. For aarch32, this is done via msr to cpsr; and writes from el0 are ignored. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 22 ++++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 4 ++++ 4 files changed, 42 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 170dd5b124..f0e61bf34f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1159,6 +1159,7 @@ void pmu_init(ARMCPU *cpu); * We will need to move AArch32 SS somewhere else at that point. */ #define CPSR_RESERVED (1U << 21) +#define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -1225,6 +1226,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_PAN (1U << 22) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4e3fe00316..512be5c644 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4112,6 +4112,17 @@ static void aa64_daif_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->daif =3D value & PSTATE_DAIF; } =20 +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_PAN; +} + +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7405,6 +7416,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, lor_reginfo); } =20 + if (cpu_isar_feature(aa64_pan, cpu)) { + static const ARMCPRegInfo pan_reginfo[] =3D { + { .name =3D "PAN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D = 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, + .readfn =3D aa64_pan_read, .writefn =3D aa64_pan_write, }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pan_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { static const ARMCPRegInfo vhe_reginfo[] =3D { { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b5c7bc2d76..7f5a68106b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1601,6 +1601,20 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x04: /* PAN */ + if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + t1 =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; diff --git a/target/arm/translate.c b/target/arm/translate.c index 47a374b53d..98e6072dd4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2785,6 +2785,10 @@ static int gen_set_psr(DisasContext *s, uint32_t mas= k, int spsr, TCGv_i32 t0) tcg_gen_or_i32(tmp, tmp, t0); store_cpu_field(tmp, spsr); } else { + /* Data writes to CPSR.PAN using an MSR insn at EL0 are ignored. = */ + if (IS_USER(s)) { + mask &=3D ~CPSR_PAN; + } gen_set_cpsr(t0, mask); } tcg_temp_free_i32(t0); --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kdW9rejh1ibQajGq3OYdmfZLH8GvxDCl1d2Jfe7OmXM=; b=McUPS8EwimSh1/Fh5SI1znSlwb1sJgYucLyst9pmIYvO6GVt4QTxxDxTnWJrxE+29L 98yJC/dLhgpW/aptS8ckulAeN6Wih1CJlNE6k8MeEnzNg7eChm/TEZmDXB49SuJvD/Oh g9iJT0ucE6FV8r4M4T18L87o0eBtvfi+793rJHjTmnSo4j6hiJ7tnecN7Vj6nIJbBQRE jd+6rKVZh9nDqrI4uD8xdaJ9VO2GKNS4u99aPnbXYVfDjQ2mIWo35XwgBv4+9K+7IDdN JjQeH0lRbJ4dRVQJLAr4ABM8nhJagfOLTLOJovrdDZzCTFymRKv0nSNqxgYyeQIJmryd WLMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kdW9rejh1ibQajGq3OYdmfZLH8GvxDCl1d2Jfe7OmXM=; b=n8BMcA1gG2ux7cBzxIszAmkiBs47J2C1RIW/IlL53MPT2lSyCWqdHbR/lj0jusJjgT tJBR2/rkVNhw+rK5CmLWMqRH5Q2DWgV6dNte/jWUpycXjZ/6w5kM8kYvstkRhEFp8Hxy T8tnwNy7/o/pEokx1V7c7JFPf6mgidHjxeuk5las0mHzLfpZstKqB2DDH0M2ZiuAdYKC VACrpbrJarKVEDnNf/rjgttjoCmhb04gn5R12tSHljQs/n2MSFjqdsxordxJQr70K+qr vXbI2+VjG0E2zG5PlwtJGDxrntlvv2RN/k37HRFMsrrf/KVCQ5nQuCRk+GIFIDcScqZH Y+AQ== X-Gm-Message-State: APjAAAU4rL066rC0QYowc35x+wGuBnjHynQdYLWE+kJbvD4lZNJf6oZZ 9w8MfCiTkJDoCDlEhKlSj8wQauGrdzo= X-Google-Smtp-Source: APXvYqx9sIgEx+ddkvSLwkpJ/hZ5lkrhMPYg9JQzZ/4mPA+S5eM5SDjDE3oYipGWTwe1jIk+vnG1nA== X-Received: by 2002:a17:902:6bcc:: with SMTP id m12mr347091plt.272.1575413624119; Tue, 03 Dec 2019 14:53:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/11] target/arm: Update arm_mmu_idx_el for PAN Date: Tue, 3 Dec 2019 14:53:29 -0800 Message-Id: <20191203225333.17055-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Examine the PAN bit for EL1, EL2, and Secure EL1 to determine if it applies. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 512be5c644..6c65dd799e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11770,13 +11770,22 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return ARMMMUIdx_EL10_0; case 1: if (arm_is_secure_below_el3(env)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_SE1_PAN; + } return ARMMMUIdx_SE1; } + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_EL10_1_PAN; + } return ARMMMUIdx_EL10_1; case 2: /* TODO: ARMv8.4-SecEL2 */ /* Note that TGE does not apply at EL2. */ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_EL20_2_PAN; + } return ARMMMUIdx_EL20_2; } return ARMMMUIdx_E2; --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575414533; cv=none; d=zohomail.com; s=zohoarc; b=kjzVAhBtt+pZ6jMMZVyfJsBjrI9+aBxkVJAlto7R7nJGsPM3zrfWvU1A5mWr5p3w+Im8UQQHzA3kIsQ+nFcXYe70KXJ0Y4O/YRsyuVRuFTw3JFMwFh77dHJipgGvJyPUXOnZIXK+AJTMXdma6GLtjYEMYm4ECFEI2YPwRyj9EfY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575414533; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=zIHslnUoGfikMY/tOISXoUEjJ6B+SC/aIId9fLfQVxs=; b=fsw7Fv9EYVMTQlM4drsr2AJfgMUX9yNJupnNdMqWM+p/2yOFxBcgXgoYH+ygyivstc96k9GNxZvh7PMVWdx32JYWP0Rh42bxhi84wrFAh58Coi6GcU4/VnGtbNRdGCdziAYmCIKsARjZpUxNdx2F3fYCrrGEctAVLOtjVT2DVH4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157541453344875.40551689415906; Tue, 3 Dec 2019 15:08:53 -0800 (PST) Received: from localhost ([::1]:60192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHHo-0001of-4Q for importer@patchew.org; Tue, 03 Dec 2019 18:08:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58613) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3e-0002wm-Ru for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH3Z-0006ue-5R for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:11 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:36581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH3V-0006Zp-Tg for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:07 -0500 Received: by mail-pj1-x102c.google.com with SMTP id n96so2120386pjc.3 for ; Tue, 03 Dec 2019 14:53:46 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zIHslnUoGfikMY/tOISXoUEjJ6B+SC/aIId9fLfQVxs=; b=CnJtkF8ZTefan5dRJ/FlnlnsN9Bl085KXHD9S5KUxhOY3kcVUZUr+mjfmIqvdDG8Fx Yrcg5wVcSTYVV60HTxBczy6HtmryhUMJXN+YEHiaHQMnVkgil2Zx/v40INj2ASwyttsg aFj8KH/r/LPwZAJ4O+IwkMvsDJE29RYsPAZU1yVtkvEcIReLQkRa9UngxFjp7Bb31gQC vz8d+U9mUdDLc3HXrJTTlS7fG/XKHpyZDZgZQQe5K1s2YyW6LYOxv2EczLRXivGgFGQ+ Gr7EhiJNwZHpN8KKWLvv7DG6K0CNjzeJmGkaiOs0NT5/h68HS4Rj2xklSJgz+Xt3h8kK 76Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zIHslnUoGfikMY/tOISXoUEjJ6B+SC/aIId9fLfQVxs=; b=JoRTPdOYhSoyzzfje8G99xoWbtztc5j5QzuzMkYz1xVwKJgd43xGZZcVHs3tSguQae pw2F+oBeaETxM9cvt3Ui8CHUztD98cBoRQdNiJSeWY+ukDCkfQakIbz3ranbReKGSvhO U8O8k4dSgRr9J9OfMB+aQHNAwkx7RD0b3bJWh1QU9Xbz4PpkxMT25Obk9fWmi9+x+aX6 mQMDrb3JoBvAsFnqIOrRiVthMKpvi4KBbMd7QIoFdEW3hjcscKdhyhmLMdWvwkUGSOga 4c/o6TlUEZzuiYcKPGo+NPxnQBustWQajR5Kmz3CjacrXC6HIPsZKagFo0ihahr5UlZD asZg== X-Gm-Message-State: APjAAAUwHiRsvc0HDDVIOVgkWDJo9UhCleDYZJK0UnLXrKTWVNboAysK 8i++yj5Azfh3YEKbplGerXwsiGceWM0= X-Google-Smtp-Source: APXvYqxEdNOANe2spkGfjIoKhF3O9uFG0a+GWUvvoCQ38xCbbmjgBiCXOGjoOFSOAeLgyYBa9krcIA== X-Received: by 2002:a17:902:9a8d:: with SMTP id w13mr355806plp.330.1575413625366; Tue, 03 Dec 2019 14:53:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/11] target/arm: Enforce PAN semantics in get_S1prot Date: Tue, 3 Dec 2019 14:53:30 -0800 Message-Id: <20191203225333.17055-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::102c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If we have a PAN-enforcing mmu_idx, set prot =3D=3D 0 if user_rw !=3D 0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 13 +++++++++++++ target/arm/helper.c | 3 +++ 2 files changed, 16 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2408953031..ab3b436379 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -893,6 +893,19 @@ static inline bool regime_is_secure(CPUARMState *env, = ARMMMUIdx mmu_idx) } } =20 +static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_EL10_1_PAN: + case ARMMMUIdx_EL20_2_PAN: + case ARMMMUIdx_SE1_PAN: + return true; + default: + return false; + } +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 6c65dd799e..a1dbafb9b2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9444,6 +9444,9 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, if (is_user) { prot_rw =3D user_rw; } else { + if (user_rw && regime_is_pan(env, mmu_idx)) { + return 0; + } prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); } =20 --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575415689; cv=none; d=zohomail.com; s=zohoarc; b=M/6SvFg50dk4iXC8Kcp9QtP78G7AZdh5IatmyA8LO0ZnoGJUT/WrULJVTM6Cw6xFs7MKmWH7nVtNdSlZbw9qMfqWOJGeNHjVBn8K4uG6xRZ9MLt8X/Hv2GY9UUivBGiSmpvLVseGKEd5jyF7OjcYYrsPA0ZxUZjXeKV1JGdrQ5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575415689; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=CW2EPJtOmxl4BSZSTFMUahqoZD/6rAAwVofwfa2CqPY=; b=AH5n84Eu+o1gU1TAbtFU4AkiMoqz8bFJghDyU/xsJNJLcEOBUfemMAIZaSayvd9UxpxrAg7EDvVtvN24NGwmaQBRQNTkEcojGCSfGVbn2azPSs4F8GO9CZD2lo/YQ4rHXPhTCeIzm9Y/+JkVNp+VUvP9RcHpRM+nbpHvahci+6w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575415689112670.8612147415214; Tue, 3 Dec 2019 15:28:09 -0800 (PST) Received: from localhost ([::1]:60394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHaR-0005j8-3j for importer@patchew.org; Tue, 03 Dec 2019 18:28:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58631) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3e-0002wp-VL for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH3Z-0006uv-63 for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:11 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:37696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH3V-0006aj-9R for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:05 -0500 Received: by mail-pf1-x443.google.com with SMTP id s18so2577878pfm.4 for ; Tue, 03 Dec 2019 14:53:48 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CW2EPJtOmxl4BSZSTFMUahqoZD/6rAAwVofwfa2CqPY=; b=i9iXMUtl7S9kXYrXaO6jMQ2JlSFVx5US+lcZQijuDMQdlT8b5nJs7vbrHyxknWNPEH z16qZxgXtKzm9Tcz1TsgM1oFotzJKz6TEhVuQVxcc3RevIjgTxTaxo0HLl9PlCMNeU6g EKyVRdvqj+9Iepd94LK/Gyjc2UgQaQ08uzoSbR7Nf41pFK0mArn7XFWY+8fDBejAZhtN zLY2kqOgSY586MnxPYED5WuVfoJN2illYRT/DDfIxOeKNCLnCySkEj0Teu92k26/PhIX j/fOE3a6b/+IdHHkQjUSFBo40KZwsyFhbz1BxazZVcuDABIW3hZjq3kLUZAuJCIJFcsi qY+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CW2EPJtOmxl4BSZSTFMUahqoZD/6rAAwVofwfa2CqPY=; b=cMd6PYM4jlkTTvw7Uoj7PCj7xg79R5yE0vIt4vhV67R9O0KBthz4sAmzIvI7Y40qQY ip/wv//erMx9TFK9roCwT8CDSXiOzVhgMhCPhEMiulcncCV4SJomOqKiwVVPJ8OKD7q7 eYdqg3SfN1CgKpnE8YQZ+j5DxC+vpGIY6oQCRI0u1aigY9GNH0COt3RoCPn/DIePk8sk kLU0kUW59HjHi7M1hYOCwPBqHPo0q8SI5O+IPCiFS1knNPnLmGYVv3y7dvdGixkQJTeC FIP0QTtr2z4Wdv2S2E/aTxnMpEAW60l2c74NUtEHvSBGJprOlkg2mHRnj+omGCbUgyhw aRQQ== X-Gm-Message-State: APjAAAWk1BzeOit7ADIlP++1zUpmYfF1wZ4kR3TpA0JhglR7WSRwByJR VCqVfRTeHM2VaXyO/s7EQF7mfta3/zY= X-Google-Smtp-Source: APXvYqzD/XHQ0w/WY8XON6ZVogOAj9QhVcPIzKDnKqtYgyawuVtpwL/w/sNjpmfKHnea3KoHZTdm2Q== X-Received: by 2002:a63:5962:: with SMTP id j34mr37304pgm.421.1575413626664; Tue, 03 Dec 2019 14:53:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/11] target/arm: Set PAN bit as required on exception entry Date: Tue, 3 Dec 2019 14:53:31 -0800 Message-Id: <20191203225333.17055-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The PAN bit is preserved, or set as per SCTLR_ELx.SPAN, plus several other conditions listed in the ARM ARM. Signed-off-by: Richard Henderson --- target/arm/helper.c | 42 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a1dbafb9b2..043e44d73d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8634,8 +8634,12 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) { + int new_el; + /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); + new_el =3D arm_current_el(env); + /* * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. @@ -8648,7 +8652,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; /* Set new mode endianness */ env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { env->uncached_cpsr |=3D CPSR_E; } /* J and IL must always be cleared for exception entry */ @@ -8659,6 +8663,14 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; env->elr_el[2] =3D env->regs[15]; } else { + /* CPSR.PAN is preserved unless target is EL1 and SCTLR.SPAN =3D= =3D 0. */ + if (cpu_isar_feature(aa64_pan, env_archcpu(env))) { + env->uncached_cpsr |=3D + (new_el =3D=3D 1 && + (env->cp15.sctlr_el[1] & SCTLR_SPAN) =3D=3D 0 + ? CPSR_PAN + : env->spsr & CPSR_PAN); + } /* * this is a lie, as there was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 @@ -8921,6 +8933,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int new_el =3D env->exception.target_el; target_ulong addr =3D env->cp15.vbar_el[new_el]; unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); + unsigned int old_mode; unsigned int cur_el =3D arm_current_el(env); =20 /* @@ -9006,20 +9019,43 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) } =20 if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D pstate_rea= d(env); + old_mode =3D pstate_read(env); aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] =3D env->pc; } else { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D cpsr_read(= env); + old_mode =3D cpsr_read(env); env->elr_el[new_el] =3D env->regs[15]; =20 aarch64_sync_32_to_64(env); =20 env->condexec_bits =3D 0; } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... = */ + new_mode |=3D old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + !=3D (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { + new_mode |=3D PSTATE_PAN; + } + break; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575415861; cv=none; d=zohomail.com; s=zohoarc; b=BM0r2Dw8lkzcZ+GUkBTLPBOvOAaxfYZ/iS5xeFigI2otwsRFK1kIbfdqalmzIy16mupmn/MbLJv8cX6B4kWLSgMz3JMhY87L/GcV7GMFbJVl6ELcIgLZ1jYHHNvRWbO4AX0WN0BN/Bc4c59jDkgmicpILlC6OpEvxIla10sKsOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575415861; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=yh3Zl0Yfgd5t5mYjFXJ95PB0dxs1Lxcsdr6CBQV1gYs=; b=bZEypN+gQ2wRUfAHMsXM53RnEDBjSkaE4ntNKacMFC2uq3URY+r2D3mr/VFZ80wa02bHmcIdcslQsdxn75//iz2o+mSh98afqX7urFz85CaOeT2y/7oRlQqWTylL2J0fI2as57GxbzPb7JDbjOUAl0FA81t54wW+gmljPKBxEwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575415861148535.6489388455875; Tue, 3 Dec 2019 15:31:01 -0800 (PST) Received: from localhost ([::1]:60416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHdD-0007UX-PQ for importer@patchew.org; Tue, 03 Dec 2019 18:30:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58628) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3e-0002wo-U1 for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH3Z-0006vN-AG for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:11 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:35018) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH3V-0006bt-UA for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:07 -0500 Received: by mail-pj1-x1041.google.com with SMTP id w23so1032520pjd.2 for ; Tue, 03 Dec 2019 14:53:49 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yh3Zl0Yfgd5t5mYjFXJ95PB0dxs1Lxcsdr6CBQV1gYs=; b=MO5NaQ+fWAcCRw8VDgNrpdsX+WE2S6qwB+PHclgbzfqvmArsAARrtN2c3SHs25Vkmv Cro5Zf6oeiRfhtmRbH6sFrgJGbmu1uSiQ3uVLtMAdVNqVM8aFciYg9CJK0p0vwPMtU07 CGPsy8tp7a3O4pSeIGPk98/FPFdn75Bi/nXOZcizAcP8Gbsv2Ood4iIf/YsmVjM7Z2qa 0tPgcakSmNCO/kbPqE9QfzFc6d8ya7sGR7QB2u29z7gxOktq/atKaG/rM1UYY87aQkhQ Oy5CfGzCUPFeOoWho3HAx3V8JKLDM2vE4Tax0vNiLfbZEOOApSh6u68LfirTR7U5Nvos MYAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yh3Zl0Yfgd5t5mYjFXJ95PB0dxs1Lxcsdr6CBQV1gYs=; b=k61auEUPGg2RJV6KGzMvcQYoUB/v5Ut6efjVgEQiQ0VgGNzI8YuT8Et2lugyPTUPDo qtnum2skrkmjCErB7BJygjxvunKJMV3NxGdSJHfyMNtGTfDl9pt7kmN0ICehQsOcSOA+ DaUSct20ZeLCDIVe106yrNvlTheIAfrEO0Rl1hzApemyLAl4j/zW+l+F2sluWvnLJtbF VQCvYJ65NUIFdV5oC3UkgEEf17ykb1fhs5ODw5/9zJgZzxzqqoY1/qpvqafMNTiMYPXJ C5kxSqmwtfJoxTWulDmxcmEyo1P1mwFH7rao+JO3AdWWyk2mwWfjVceafK7tKCNlyTQx HJxw== X-Gm-Message-State: APjAAAXbsmu/w6M7p3VZ+3rh2ueFhFcSLyb83XI+H8umK6Z0r/xZ440i po8diXefmwp2x5zmCLDGrDibOIiZNWE= X-Google-Smtp-Source: APXvYqwe5gK7CBpQMgu7t8Ovhe+hpyTDwLjOF6zmhJMiNp3XvrZmoLZUniCmcUor65vqN42DuxFghQ== X-Received: by 2002:a17:902:d201:: with SMTP id t1mr367250ply.322.1575413628230; Tue, 03 Dec 2019 14:53:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/11] target/arm: Implement ATS1E1 system registers Date: Tue, 3 Dec 2019 14:53:32 -0800 Message-Id: <20191203225333.17055-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 043e44d73d..f1eab4fb28 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3360,16 +3360,20 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) =20 switch (ri->opc2 & 6) { case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; break; case 2: - mmu_idx =3D ARMMMUIdx_Stage1_E1; - break; + g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + /* fall through */ case 1: - mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx =3D secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_= E1_PAN; + } else { + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + } break; default: g_assert_not_reached(); @@ -3438,8 +3442,12 @@ static void ats_write64(CPUARMState *env, const ARMC= PRegInfo *ri, switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx =3D secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_= E1_PAN; + } else { + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + } break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_E2; @@ -7426,6 +7434,36 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_arm_cp_regs(cpu, pan_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + static const ARMCPRegInfo ats1e1_reginfo[] =3D { + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D = 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_E= XC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D = 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_E= XC, + .writefn =3D ats_write64 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + static const ARMCPRegInfo ats1cp_reginfo[] =3D { + { .name =3D "ATS1CPRP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_E= XC, + .writefn =3D ats_write }, + { .name =3D "ATS1CPWP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_E= XC, + .writefn =3D ats_write }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { static const ARMCPRegInfo vhe_reginfo[] =3D { --=20 2.17.1 From nobody Mon May 20 01:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575415011; cv=none; d=zohomail.com; s=zohoarc; b=BgGu1D4wcFZADDhSKhqqkZ/iJbnqGcmXwKQHEHwvwoFM6L/et5Oj9tcZtwSyd9EA2RxdJNezll5ihvHKaojfybE/fZ5LGVfmrnrh5trHORLLFmTv0O/s+BxOyUS0ZPdvwLJPWTKutVyz1eY1uPvY/lN14wzO/o38D4wG6Shn2do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575415011; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=KQ4nnssDdUX84cYwpBX+qRuZqhWJTbkOPZT8YrFeOhs=; b=R1dr/xKhMTzwyOoayY1xtW8ZkTWozsBSFgm7PXsUOXFAYc1wuaFDpNIbqle9a6cUuXR/4Xc7ZErqA+qjkf10b+X0TLqTcwcQLNdkU99mXJtiYkS0sVQ/xfCYsouxRbI5ZwTk2hKTVN+8aYabK23K6PncH/t9YM5cVCTuz5f3Q7A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575415011252239.34484207446542; Tue, 3 Dec 2019 15:16:51 -0800 (PST) Received: from localhost ([::1]:60276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHPV-00074c-Lx for importer@patchew.org; Tue, 03 Dec 2019 18:16:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58621) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3e-0002wn-TS for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH3Z-0006um-7C for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:11 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:39585) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH3X-0006cn-6X for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:09 -0500 Received: by mail-pf1-x441.google.com with SMTP id x28so2571052pfo.6 for ; Tue, 03 Dec 2019 14:53:51 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KQ4nnssDdUX84cYwpBX+qRuZqhWJTbkOPZT8YrFeOhs=; b=eQqCE+shHPKIcO9Tsszm6MGoIgkVazn2NdvmjidCvDhFFv8TMKl5srUULllLUwbs9D ZsE7wD18a6tMOt+SZPxGrNyHDWqcuT0KLg26eGWYd+FL5+RnVV396rmD1txesA4Gqq8U PWsyacEjJD05oj+VqZFbx8uygjCS0/TSrTz35T9NBuWExQiYemzKe185UokdsqoILDxi bgjltdW8Qw73KKdVTL6MkHDQVF/83NykJy5TwjPeP+6DbuVMexjORfGFyoEORY2qR5ge MyWmzZdscFwnIqvmNHokbdwvLxU6c1n7HnVe3glHaGWLypsFKmHNZVq/HehUU8KxvW14 30xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KQ4nnssDdUX84cYwpBX+qRuZqhWJTbkOPZT8YrFeOhs=; b=XcnIpQgD6U5br/29QuPCsdDH1RJsDZ4+wWezWRBkkKZPpC1K28fL24Yyizxg/2mWef NBJ+RvxTKYxDX4h6P8BZtHiv2tQneCLrjFfcgo2k+FY3ffZpo09aw7dALOCrurNUTXVE Kc0ATDORaJr64f08mkmXgYrthFX0QUe7w0IQrXZxbB7HhqfegLEJpLSKSmBws6uNHUui U0NTOmIO5xkmiKslQD3EQA9RcStjKCe3+ZRgQhOZLynjDMcLmMGdEx3Dvf0q4CQGHUNm FjFr+yq7vikWCKemcLv2b2NKeZLeLCffrF3oe4vWpv0zLwHRfY1dDy/lwiYKNOIGaesy GfSw== X-Gm-Message-State: APjAAAUQQ9GHFJtyHEbhyX5JOfLw39WwbVTMBp5tKXC3rSFUME7grors HEj2UJYM97vyM+EJDo7/8X2CbRCzWyY= X-Google-Smtp-Source: APXvYqw2S+J4qUvWrWi2iqNjRCGoF8tWPoQg8HZ/UNWBWkEU6DRENLmBJs+BlsOPWIHlE3RKWQZtDA== X-Received: by 2002:a62:fb0e:: with SMTP id x14mr308844pfm.194.1575413629919; Tue, 03 Dec 2019 14:53:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/11] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Date: Tue, 3 Dec 2019 14:53:33 -0800 Message-Id: <20191203225333.17055-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes enablement of ARMv8.1-PAN. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f3360dbb98..3b0c466137 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2640,6 +2640,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 + t =3D cpu->id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 =3D t; + t =3D cpu->id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ cpu->id_mmfr4 =3D t; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 009411813f..9399253b4c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -671,6 +671,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ @@ -691,6 +692,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 + u =3D cpu->id_mmfr3; + u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 =3D u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, --=20 2.17.1