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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IK4eA+8GzL3ARTInAUnzO/6P31CtExBfABqpoPMVkjQ=; b=TzyXE10eIeEtfc3xnTUutUXgUMLdl6filN8zICwyjjGmsrnEB7NcIFHRsw0D03VFda g0+VEd9xAjTfLyBOfdd2YW4hANY3ZRy2/JGU2BXvnRTcFtgWh/0EsuWys+ohQ7oWSGIY aOaotBT9FnrV7EufLpOzVA9qkTdtMJPAPNTDlahpFfS7hRtUkU2eAIgWvATh82RYlgr4 kNuVq1cEFidepgVHMpoJSCtj8emNIqBtnBftdr01IhDoLBBFRp1HkkOBr47d2WWMP79w GRi+3FZ/guPzvkON9N/XAzaw7kir/FfIV6GuvZGb5GRZo3kJfZ/gPNz2aKi0D5PW/3T5 P4LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IK4eA+8GzL3ARTInAUnzO/6P31CtExBfABqpoPMVkjQ=; b=XRmBi7fnsl/CBEF5JxiRl73btpEzhKzWmWnIbw2LGm1tLGZVQy4z8lIyOQ+4akRXys FDDm4icgcr6GKn586KCxHHscbdTJ9A1l4bNeEw296q1T800oeVUoquyLNcWfs5sKEHrm X4GK5/BxNX1eVmKQbL98VCOv9Y/dsVDoJdXjgiCv9l85dUI+YhgHiKQSZkPMOoKgL7n1 39EmHaxpLU/ZLDIJTnDBq5Fk3o3qWedpRpTpoF5AfP1JPr9RA/GW+KxnD4vEfyJWiJqY /BgF1U7ykqBZZYKtudwPGnhED7FsdZi7IpOwJlAAL323gTKCiR4JhnI6jreMd1wWCT/1 k8ew== X-Gm-Message-State: APjAAAVkhr2paIV1qHJTgfX9ofcZU/1NdJiXvKEoF3DkwzHm9wW5Pv6K 0iHKHK1/7vh6T5+mlQHck5tbeFrQwKo= X-Google-Smtp-Source: APXvYqwGk9wconeG8Ip5Bn9Zczuemo8ldM4s9lLUjVCrnU7knLZ/lbQjyKVRA6T/XSYnuUUYo8ghzQ== X-Received: by 2002:a05:6a00:3:: with SMTP id h3mr2255810pfk.78.1575340188542; Mon, 02 Dec 2019 18:29:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/40] target/arm: Simplify tlb_force_broadcast alternatives Date: Mon, 2 Dec 2019 18:29:04 -0800 Message-Id: <20191203022937.1474-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 +++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b0130d814..6c09cda4ea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiall_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimva_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiasid_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimvaa_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3915,11 +3913,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1is_write(env, NULL, value); - return; + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); } - - tlb_flush_by_mmuidx(cs, mask); } =20 static int vmalle1_tlbmask(CPUARMState *env) @@ -4041,11 +4038,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vae1is_write(env, NULL, value); - return; + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.17.1