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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bqFmG5Z1vaxgrnnahQPUtAEMOtLoaTFE8WYhisDg6pA=; b=mITxmaZC7eclvocYyjWfbqDgOESFlDcSqs07Xn72GZulYpILeHcMKJK9qExMo1nb0t Ws3LZ+i7fdamiuHCPRgHfAWZmoYVgGYOAI5/m3IWNEHsJWr9+UJALPoH2wXrlfKCVlsp WnieNIVJ3oefOuG/AjQw2EN6DUVZbyQENzx79k7btiGIWJDAtDN9TOTNer5o9tx74u8n NBbZ6QhBn/LfKhNjBLOI8+MDAPyzWPLxDuOXKZjee0oW+KQNtiBEPbRUX00Ttw3q5q6d a9LoglXoGgpnOudbjjgil0bzoXkKR0HrMlFfrMmX9+MftC/TyQUNg6llZ4dx/xM4Vfjf R2tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bqFmG5Z1vaxgrnnahQPUtAEMOtLoaTFE8WYhisDg6pA=; b=pwQLkZjfRwwzm2YDdoACN35dkJZL2/Y6gSu+FM1qtzasZgB3dzq9T7aKxT+6WRbbdF zYMN1aqKAaeTvR8osk7E/1pLH+2WcqUxq4ZaK3cxX7Xilh0tGTjZWahW3stVWw1RNl7d laJ0k4QhdEe+z6HyTTYDAB7vmJZrtmzR+4tVmA/ovwhsPpGWpySyM4Npgj1g3Mv31Dvj I5oqGe3/5Vbuh5okbzZMUyitgWHQVsoFFtYGqC302yezRxf7lCYdNzqxR4vahLUzTHYk WY89b/nRefG+CRW06totgqnPV1GRSsvusl9mr+hXFrppnrmFoNDpnqwQn+YT55twRE7a IYrQ== X-Gm-Message-State: APjAAAWSpCyTI+wWJG2tJUCzRhkigkwX8bKUr4wQ+ZfxXFk5BoHqwCgo WFfjWGU2eBHJH7SJzNEV4+uVa/6rOg8= X-Google-Smtp-Source: APXvYqyjYrTMidUh438qrX5fwv9SAgp+L4vbPniO4kTyjPld0K64wY0iFS+81WP03eCnW3p9MzWQNA== X-Received: by 2002:aa7:968b:: with SMTP id f11mr2326350pfk.209.1575340180449; Mon, 02 Dec 2019 18:29:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/40] target/arm: Define isar_feature_aa64_vh Date: Mon, 2 Dec 2019 18:28:58 -0800 Message-Id: <20191203022937.1474-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4ba..994cad2014 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3632,6 +3632,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; } =20 +static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; +} + static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340408; cv=none; d=zohomail.com; s=zohoarc; b=duv6TvYRaBB6ecd2c7RNNaRsOuONq8st0Q8uLXRWv2sy5O0vHnTEVP7Oj75SwWv/Dyd1bAnjN/D5RFO87mHF7XQ8Z/DTCIEIItlVNH5R/nmCT0Kh6S7NGcvdWQCgk6mQh8NOiR/NyOhS6u63ct/1QQA+6M9gP13C9HBs0A0a5+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340408; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6+PxY8SIDMEG7zwbqXLvGydymJLf+U0upJ2ABich2l0=; b=PBB9B6Lm2j4pLMHXh5TAZr2FPScR0FjG7bhO461PRPC9xn0PTRKUR6Og0byvmBlF3N0PIYqOK3yFMRj1lcDXPa2CWzZRfFbQAF+81XxVUQ8GOLf78BCYp3sT3NFG47pcCaRWZQ/oqjJMnrSpXXdhE8D2i0+W6DRiv3Uk2antIOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575340408989832.4281719567268; Mon, 2 Dec 2019 18:33:28 -0800 (PST) Received: from localhost ([::1]:47134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby0F-00056a-2Y for importer@patchew.org; Mon, 02 Dec 2019 21:33:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59047) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwe-0002y2-Ge for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwd-0007wm-Bj for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:44 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:33599) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwd-0007vP-5m for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:43 -0500 Received: by mail-pl1-x643.google.com with SMTP id ay6so1015793plb.0 for ; Mon, 02 Dec 2019 18:29:43 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6+PxY8SIDMEG7zwbqXLvGydymJLf+U0upJ2ABich2l0=; b=al9UUL+mkN/6t8YLEzPqgmKq3KP+bXg/GqpsiXjwJmVI+m/fqSe72I8bDU4VWRzNCZ Eul2lGK362EcZWctjX90DzRcqJuNG737U57oIIN9U5diQYdD9dQRTclXicOSOQSrwkFE IfTxWobn6+Vi8QL9+6bpzH/28SACDKLtEQTOg7AOk3XY3VOpn0mkl5ldz1mukWyK8oV+ aS1N101hwbXfl/Z3Ff228RkUmlRculRB6r/C03EyfzqWLp8WIM/bulJrcr3gowplq1F2 r212Xqnydt3DPhjS/+mCh5khYI4qYc3dHZTPASCsKOvJrBlrV+M66stql0t2hs8VqSBM e9Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6+PxY8SIDMEG7zwbqXLvGydymJLf+U0upJ2ABich2l0=; b=GBGSDYMMy4x9LWZAnXA6O83iF0a4T9wETy3ujC+RFvEndhhGNR1igv2U6aesDOZWfR q5O+4opndlVCDD4EOq/T3YVf7wpQ/UgvLV/kTql/5ZvoCG7I9wukD/JYRtqqj035aV7v 6AMoG2wdMSXspdSEuaxK0G4P6M/QaI7BUifY2wbQwrs38vy13kI60DOhSv3njyJt7TJu tlXefHAmrnl5s8PUpeYtpNWyPP6rsVkt0yYl7FHeEkkIrcueAm3bBECswBRIZRkey/EE XLXCAQyJoOCFlOTjvVTl27MWC+xHSrf0O1y4jAknhzd3W0FhiwTyivsRlyssTjwStC02 pjHw== X-Gm-Message-State: APjAAAWXn5XuUr8Y3BFnIpoK4DpKODFojTcLq+rM4T7m8lreYZrw7Wse J9SJsH6kRvcaxZLn1iqBsQV2EUbg2FE= X-Google-Smtp-Source: APXvYqx8qG34kGzIm0bTrpS2oFEQexXgcxKp00bCl0HDU7PLKTMGa0GBTsI7BGjoVXQj+AIdQZsuEg== X-Received: by 2002:a17:90a:c592:: with SMTP id l18mr2810677pjt.69.1575340181879; Mon, 02 Dec 2019 18:29:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/40] target/arm: Enable HCR_E2H for VHE Date: Mon, 2 Dec 2019 18:28:59 -0800 Message-Id: <20191203022937.1474-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 ------- target/arm/helper.c | 6 +++++- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 994cad2014..9729e62d2c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1387,13 +1387,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) =20 -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b..d81daadf45 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4672,7 +4672,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t valid_mask =3D HCR_MASK; + /* Begin with bits defined in base ARMv8.0. */ + uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -4686,6 +4687,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |=3D HCR_E2H; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340411; cv=none; d=zohomail.com; s=zohoarc; b=k8d5a3XNeXIZokEenlFrbpigtkK+ffD6WcS4/KQEJoI1H9TOR5TnJmxa9pk5rIPyRIWnzyD4YlxwiRuM554H3C6KjjXTAu4c0BIwlvdpZXpgo7oGYpQrWcqiQ4gtRivz8jKXiwpTNQuhpJwq6DJBz/fGQaRxRb+ffm9RHBT/cI8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340411; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+TWIlcZZrmEqGDmi7NHEaLblsjTyqMT3Bn6OGEgJfYE=; b=fmLmBXEFFYh+pJ61F67lxfRPU+6Bqisgt+AmKWW083Sukban3qLINfVPuOqoU5xVr1FVeUUsEjaRcLxKQnLtXl8Lo/+lexjv0d2kWKJ5m9oyZhryltPGrOuEYNORy7Tt86doJioVswGJhFjkjJHLSJw8NtLI5rEyP3+T8GnDDl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575340411018749.7100980614553; Mon, 2 Dec 2019 18:33:31 -0800 (PST) Received: from localhost ([::1]:47142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby0H-0005Ds-MZ for importer@patchew.org; Mon, 02 Dec 2019 21:33:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59248) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwf-0002zN-SG for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwe-0007yg-JJ for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:45 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:35150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwe-0007xM-Cx for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:44 -0500 Received: by mail-pf1-x441.google.com with SMTP id b19so991642pfo.2 for ; Mon, 02 Dec 2019 18:29:44 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+TWIlcZZrmEqGDmi7NHEaLblsjTyqMT3Bn6OGEgJfYE=; b=C7X7emm81rhXLpsyakilwuRbZmwY9k57/rLnqpPuLP2oDBHZC8kT1JZCo/QE/wgMya xmD1wwwYDIx9FomLmomyd93WLmzr9+kd4/AufCyVFxpl2ZbhULH3HtINeXSB2s0DAEdR 4Jvk84gsOsR9Y1QtadUN61vbAWhKI/S9O8tgcdjw+QxranMRoLpRLbuGLngHJLEQst4d yNZWjV5pgOWMsGZyo4dFrEIfMf5U0Mo7hMvomd0YMOYK1ONsW9INsO4+wIVixdQVo/B9 fRIVL4wYcWLVC5aX47qXeKiIahCGFTNilTJkNTpunc+Ym4ktvimSY9d7Pzbdfej+2lrs GTXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+TWIlcZZrmEqGDmi7NHEaLblsjTyqMT3Bn6OGEgJfYE=; b=L/3d7QPHTcJLrwkQfBdIxl+SR5ZeJxr93XL/XezPhpLMZ5IZ/9k8tAW1QZek4XZOK/ g2mqX+6COqZPB3wK98AwPmYiQklvj5ff2iVOuZg4oHz25ABk3GWwBC1ekrlynDxA9jsd 4ZwMbbCz8C65qcWiATwFejPhPuc6XLTynnVY4qn/OqdENXg7ao1kkUlNrUWdfxCfOY1U txOGKuH04uW3vfacRZoJBFZN5KQdlxn5zsBWcQXyZVEyHvKodXv5CnG4Ie2zmZwjRDEv ZFEDtSK11DG0CiYBcm985m79YWvRTmd67IE5h+NomhXxXIFPiyBud5oRdSi2KtY1dJaE ow6w== X-Gm-Message-State: APjAAAWy4LkF4DO782N5Zt610CcOHvGem/5XIbEWFg+gvs3BkZewaim0 N9I1U5/i9ku8xJIG5vMtJ7s3JhUiiiw= X-Google-Smtp-Source: APXvYqyXcpakRRlr9/Bmf40W1VRjxTgj7G076ZgihLbithgZaUvpMhgrWLfOLJ5DrAp6WgKcxUQ/mA== X-Received: by 2002:a63:184c:: with SMTP id 12mr2829694pgy.418.1575340183028; Mon, 02 Dec 2019 18:29:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/40] target/arm: Add CONTEXTIDR_EL2 Date: Mon, 2 Dec 2019 18:29:00 -0800 Message-Id: <20191203022937.1474-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Not all of the breakpoint types are supported, but those that only examine contextidr are extended to support the new register. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 50 +++++++++++++++++++++++++++++---------- target/arm/helper.c | 11 +++++++++ 2 files changed, 49 insertions(+), 12 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index dde80273ff..2e3e90c6a5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -20,6 +20,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); int bt; uint32_t contextidr; + uint64_t hcr_el2; =20 /* * Links to unimplemented or non-context aware breakpoints are @@ -40,24 +41,44 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) } =20 bt =3D extract64(bcr, 20, 4); - - /* - * We match the whole register even if this is AArch32 using the - * short descriptor format (in which case it holds both PROCID and ASI= D), - * since we don't implement the optional v7 context ID masking. - */ - contextidr =3D extract64(env->cp15.contextidr_el[1], 0, 32); + hcr_el2 =3D arm_hcr_el2_eff(env); =20 switch (bt) { case 3: /* linked context ID match */ - if (arm_current_el(env) > 1) { - /* Context matches never fire in EL2 or (AArch64) EL3 */ + switch (arm_current_el(env)) { + default: + /* Context matches never fire in AArch64 EL3 */ return false; + case 2: + if (!(hcr_el2 & HCR_E2H)) { + /* Context matches never fire in EL2 without E2H enabled. = */ + return false; + } + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 1: + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 0: + if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)= ) { + contextidr =3D env->cp15.contextidr_el[2]; + } else { + contextidr =3D env->cp15.contextidr_el[1]; + } + break; } - return (contextidr =3D=3D extract64(env->cp15.dbgbvr[lbn], 0, 32)); - case 5: /* linked address mismatch (reserved in AArch64) */ + break; + + case 7: /* linked contextidr_el1 match */ + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 13: /* linked contextidr_el2 match */ + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 9: /* linked VMID match (reserved if no EL2) */ case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 15: /* linked full context ID match */ default: /* * Links to Unlinked context breakpoints must generate no @@ -66,7 +87,12 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) return false; } =20 - return false; + /* + * We match the whole register even if this is AArch32 using the + * short descriptor format (in which case it holds both PROCID and ASI= D), + * since we don't implement the optional v7 context ID masking. + */ + return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; } =20 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) diff --git a/target/arm/helper.c b/target/arm/helper.c index d81daadf45..b4d774632d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6953,6 +6953,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, lor_reginfo); } =20 + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + static const ARMCPRegInfo vhe_reginfo[] =3D { + { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D= 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]= ) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vhe_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340562; cv=none; d=zohomail.com; s=zohoarc; b=dKS63jzJ49hfRLot+X0M9Wp7lBUQZ7XFT79al+8hjdxOrB383YFoKf6w+RcXWfvVr1tYGED6gEh5J/lKCxL1CLnR7LwvjwsPL1RfZXC2sKHB+iIXblsmMqgrV1gZV1lXUWfZxuvDK3FoYx0NkKe362Xuc9WM3kIFG8rme3SkTYE= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g10Bq1OMZeg/ZBhQAkp+7YToyhofBnM8pkI8wVPAgyc=; b=evxaY1QU7cax/t6xE2PUpr+13+A251LZLRN3oAz75ntZuNfYGfS/eO5AUq4KF2KY5g DzLsiFAwfOz5m2V1uTm/ybHgR+ndnQfa4DoMyD9DM6SGWhMSu9cKENC0GKty7mnQYAYt VHklVwlgODSrS2nVTxxNv3SmHaHeXk9c7HZHltFrGT6dBXTEOjS20Um7ZOw+0xH/Fb59 c724Twcse0A+Vd9PUBEM7TPGp0I+9ygwppyZCoezMUoYc7NWWqdSs4AX99b0ZwXrKSLF 8AF0FxNvUbX+IYCI7FY8A5GqulKzcCB7493i+l9n+1Lhngxv4Ve+P+yPpmjNUzba6YEA za5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g10Bq1OMZeg/ZBhQAkp+7YToyhofBnM8pkI8wVPAgyc=; b=FDy0DpOaKWxMDszjMWEqi7u3/bc0dHij2QTlJ9UFeCgEW9tpCvofpiyyMip8XZepGv 5v5XPrVB7Qb6kg3VVvWkemyB7578fPpYEaxGUEsBfP14tR5CXQ4gxHCmYW2bClwiyMOd pkSMIcqWP6mTlYImptl5IkiSwmMPkefuLSe2Xut+iYbRDs7u/3vA9C/R6GX42l7lRVZm EY2YBJVBbSDXDNn03rrPNSfzaYtDVS1HCKRJoQyE87h9kkyQ01AQAXxzyHwzqfsNaP+G NFRPDaDlWxTeqSrQ4+zHa5mRHOjKu+nKAgu1GO7rt1Xth6v5gPfEc6UtiT/fo6Zl8llk bFhw== X-Gm-Message-State: APjAAAUH6ex20yjRUlCpq+gvCe3f2kUNnnlyPjHlnCJT2SuLnctjly7S YIg3VnJRiofKBdRkYm/4vIt4FaCu4C0= X-Google-Smtp-Source: APXvYqzaVXWRlWCV6+3NUyB1ghGeoSQ0gz7MuhW59xKJzwyyHwSoFcU3vNQvrMHCdqb8HswZKsXsdA== X-Received: by 2002:a17:902:ac8b:: with SMTP id h11mr2668987plr.87.1575340184343; Mon, 02 Dec 2019 18:29:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/40] target/arm: Add TTBR1_EL2 Date: Mon, 2 Dec 2019 18:29:01 -0800 Message-Id: <20191203022937.1474-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) At the same time, add writefn to TTBR0_EL2 and TCR_EL2. A later patch will update any ASID therein. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b4d774632d..06ec4641f3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3484,6 +3484,12 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4893,10 +4899,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -4930,7 +4934,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6959,6 +6963,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D= 1, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]= ) }, + { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vhe_reginfo); --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340761; cv=none; d=zohomail.com; s=zohoarc; b=PipqKD6tFZ/V/SDM/kFAuJCni5BRSoBAaqx+b7FuOgNV0opDr5sdua1cjvch/53ZcMM33FOdtD1tp1KbAN1n4V8tZozmBBTVaMn8Ph8Q7HE+5vBQ/G3ruzVi0T8941/PlKs0TY6AfNsrij0FH6/1gaiq6BFpJytZi+qPEYPGCAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340761; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B4OK5efhSNwYjg2uPjOpVrsLC64wOt5gZm1Hay36cdk=; b=clOw8n7wldm1zRwqprAH0AohlYp0Z82dbX+3fEU1Q3IGgXz6GVClQNHF1CSaIj68/6 8BA/KuvYj4WnZzWSuMJVU7z9v+GbDzq3mbiYpV5jbfHQNHdhH8BzQS2E2F2akJqPcigw eVTRar3ZaWAL40y3xcRMpxhWXE4+hiPyYRF6d+vHWBklyPydLP98o63d4/T/yi4LltRC jNOJmeMD3PV/EGT+ez6X+hsb9Uk2MeDVM9y+qS2exz7tfAzqPafomdtQMzb1uKGN/h4x tbfFDYORuqjfxax7+kw30tE3SKNtBPo5xTtb5m1E4j9DL+ZSNlkvusRLqI0nf5C8UZoj HJgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B4OK5efhSNwYjg2uPjOpVrsLC64wOt5gZm1Hay36cdk=; b=DIRSpbWiNoSuCEXtVCeh2Wvlx/qME/wIp0Eo2Q83WRmiXDCDdKNNa4sT2IQzJyPyIx +UxXSYDk8kJ76MNVpXJPWOxF7ZP6biL/N47Q7S+Cjz7ma7S2vuGWEXbLcxpeLQN/EQ8H +wGqVxE3M5NrhPNP9lncnwdZBA9mPLCwi3UzmHYyOC20xFqFtGmtTVCU157aKDxl42r9 RmP6DvbHVKlZ51yQJooERHnNkmYzpo22+iEemq0UFNVsG3MWewFaTXhahlU3OjL9A8rx VA9476OSIwE5oL6EO6DlKB3WEAXwktCzLJxMtz0nsJoDlPu5WfFEBL76tsqHqZimfDnz eDLw== X-Gm-Message-State: APjAAAXpOQcldsdJXZe+VjQkM44aOfBVpD9b3IrS9y2rolYsbzuc1Xnh IZ8pbS5GHjMOWJ69w9nkC+xeBibhBxI= X-Google-Smtp-Source: APXvYqyf6mLa6Rmqb19Fu9HGxekCaIwUYBcXwtxvw04TJyHn3shdulXF2ldjDVwS0Bli15Zt6Wa/rg== X-Received: by 2002:a63:5346:: with SMTP id t6mr2545902pgl.302.1575340185457; Mon, 02 Dec 2019 18:29:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/40] target/arm: Update CNTVCT_EL0 for VHE Date: Mon, 2 Dec 2019 18:29:02 -0800 Message-Id: <20191203022937.1474-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The virtual offset may be 0 depending on EL, E2H and TGE. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 06ec4641f3..731507a82f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2475,9 +2475,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, const = ARMCPRegInfo *ri) return gt_get_countervalue(env); } =20 +static uint64_t gt_virt_cnt_offset(CPUARMState *env) +{ + uint64_t hcr; + + switch (arm_current_el(env)) { + case 2: + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + return 0; + } + break; + case 0: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return 0; + } + break; + } + + return env->cp15.cntvoff_el2; +} + static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - env->cp15.cntvoff_el2; + return gt_get_countervalue(env) - gt_virt_cnt_offset(env); } =20 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2492,7 +2514,13 @@ static void gt_cval_write(CPUARMState *env, const AR= MCPRegInfo *ri, static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } =20 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - (gt_get_countervalue(env) - offset)); @@ -2502,7 +2530,13 @@ static void gt_tval_write(CPUARMState *env, const AR= MCPRegInfo *ri, int timeridx, uint64_t value) { - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } =20 trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340565; cv=none; d=zohomail.com; s=zohoarc; b=kKA6535JyUOzvTUzLCRYQt0/YXApoMUZj+tU2IRgjFOYqeihC6bV3aZrAKA5ZjU81WgOfxWM14PeyMzaGglTIrixExzEYJw1g96v3N+l3lvMVHI6QNzeMdu/qEe+7zwTtTQJGTmuNc2lsjR5ZDIBRtsMmAK6WmubfDs/CS2qfkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340565; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6jNPELaVUbQXue+a0WdtAOAMA9kKsluaXGIO7/1Q4Qk=; b=gO0p8T+8jveP0BJbHxai3qSPLscJwOu4rcdlIFieG+4efddebfkDHLYoe33O/NCPA88LWVy9ih7vGdfMsdKwe8XWLpEBXTTlc8kmyZMNke2u+PHIOwGg6dPAhCWfgaRtxJcRiB8wWam/tgPjOf7/4pRbiVFd4x2V0e0e442hNdg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575340565016628.0516713575777; Mon, 2 Dec 2019 18:36:05 -0800 (PST) Received: from localhost ([::1]:47200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby2j-0000Tk-W7 for importer@patchew.org; Mon, 02 Dec 2019 21:36:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59788) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwm-00035r-FG for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwi-000856-Qs for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:50 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35717) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwi-00083t-Gg for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:48 -0500 Received: by mail-pg1-x543.google.com with SMTP id l24so879045pgk.2 for ; Mon, 02 Dec 2019 18:29:48 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6jNPELaVUbQXue+a0WdtAOAMA9kKsluaXGIO7/1Q4Qk=; b=wJOKn0uhBqva2BpBGzl8QZxs/EzZxRkutBziLmka2Rr9f96dGYK1GdlyPvIy+6PtUa CwDlfT2PbYGSsmAMn1u/vayb+2Fe/EteCKvvpdYZv4mEJa7DEGevGpDVWL1GPAQinXhM ykCwWwIUMJ2N9LJh7AKvWGIrSzlV0hm7tJ3C22v+5CIV+16ciM0K/+8oUoKUIoKsBulc esweJOqPC0UAQDoxbWt8Bs9OnWFCgOZnfNKjpelCUFQIZrk+wgAGpkENdogrjfJT57dt b+MdWiY6MV9vepZpQp/10qBgm31YKSbewUcnej7okQwVK/c7zobzvzCvKOUVRoAP1r2h X3bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6jNPELaVUbQXue+a0WdtAOAMA9kKsluaXGIO7/1Q4Qk=; b=AjWW/q/ANk8MIGxZmrslCOTxr5OZOyx+EEFP2kcI0kejTiIdhUtNWkQraVmlH20JDY H6x+5p+8+LpF238DhiN8WEBBlmdC2QiM5dUHQ6wPdAnJyMXfsv6/pagYmLvTy1xWPg/Y 7R1Q8fmagDyZezlHiZ4CiaJDyS9eVQuGFTfm/K5k9Eu99Lm/XhfCFfj2mxJAoAOvYt0s EszpRL66jG/LGSLzfAZhT5Q9oY+IHdlRQFiSKNAZ5HrzwFZG2SN/yu6m55h3nq1P01Yu 43tkHpjhyYGcioXXaCHQS0qt5bAnExh4bEOeIqrJJEn7VREIY1L5ugKEpijbn4GpRg2V rTcQ== X-Gm-Message-State: APjAAAXTeCpa7vaAji1Bm9B/bgkBVljmw/tVwtHoMtVKGg0xLDKxsoac vNFG/0myH+ajsL/dIoOeQvv7InKODBI= X-Google-Smtp-Source: APXvYqyRCm+tVl5pcKOCf9qdZF2aEH0eKYaUYgTvBRncJRiUWjABILKkQMAgp0rkbQXDYeDSaSQo/Q== X-Received: by 2002:a63:364d:: with SMTP id d74mr2819262pga.408.1575340187119; Mon, 02 Dec 2019 18:29:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Date: Mon, 2 Dec 2019 18:29:03 -0800 Message-Id: <20191203022937.1474-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) No functional change, but unify code sequences. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 118 ++++++++++++++------------------------------ 1 file changed, 37 insertions(+), 81 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 731507a82f..0b0130d814 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3890,70 +3890,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMSta= te *env, * Page D4-1736 (DDI0487A.b) */ =20 +static int vae1_tlbmask(CPUARMState *env) +{ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + } +} + static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); + int mask =3D vae1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); return; } =20 + tlb_flush_by_mmuidx(cs, mask); +} + +static int vmalle1_tlbmask(CPUARMState *env) +{ + /* + * Note that the 'ALL' scope must invalidate both stage 1 and + * stage 2 translations, whereas most other scopes only invalidate + * stage 1 translations. + */ if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; } } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vmalle1_tlbmask(env); =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } - } + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3977,28 +3968,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); + int mask =3D vmalle1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else if (has_el2) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4048,20 +4021,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - bool sec =3D arm_is_secure_below_el3(env); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - if (sec) { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4072,8 +4036,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { @@ -4081,15 +4045,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, return; } =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340624; cv=none; d=zohomail.com; s=zohoarc; b=McZavZqubK8aqD7f6TE7EOVuXCHt0T4rO8/0HgvviZXyaoWIB8TExS5peBe9r0/1f4INEGge1J3D207dwA7qVlpSvsffKKN4frRt4ROhzgmbMYWFmtgEAhLJGnDH74LRsNfkkDUIbxptn6Mui56pmshfYWniL9Ja9nvgdRrF6xs= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IK4eA+8GzL3ARTInAUnzO/6P31CtExBfABqpoPMVkjQ=; b=TzyXE10eIeEtfc3xnTUutUXgUMLdl6filN8zICwyjjGmsrnEB7NcIFHRsw0D03VFda g0+VEd9xAjTfLyBOfdd2YW4hANY3ZRy2/JGU2BXvnRTcFtgWh/0EsuWys+ohQ7oWSGIY aOaotBT9FnrV7EufLpOzVA9qkTdtMJPAPNTDlahpFfS7hRtUkU2eAIgWvATh82RYlgr4 kNuVq1cEFidepgVHMpoJSCtj8emNIqBtnBftdr01IhDoLBBFRp1HkkOBr47d2WWMP79w GRi+3FZ/guPzvkON9N/XAzaw7kir/FfIV6GuvZGb5GRZo3kJfZ/gPNz2aKi0D5PW/3T5 P4LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IK4eA+8GzL3ARTInAUnzO/6P31CtExBfABqpoPMVkjQ=; b=XRmBi7fnsl/CBEF5JxiRl73btpEzhKzWmWnIbw2LGm1tLGZVQy4z8lIyOQ+4akRXys FDDm4icgcr6GKn586KCxHHscbdTJ9A1l4bNeEw296q1T800oeVUoquyLNcWfs5sKEHrm X4GK5/BxNX1eVmKQbL98VCOv9Y/dsVDoJdXjgiCv9l85dUI+YhgHiKQSZkPMOoKgL7n1 39EmHaxpLU/ZLDIJTnDBq5Fk3o3qWedpRpTpoF5AfP1JPr9RA/GW+KxnD4vEfyJWiJqY /BgF1U7ykqBZZYKtudwPGnhED7FsdZi7IpOwJlAAL323gTKCiR4JhnI6jreMd1wWCT/1 k8ew== X-Gm-Message-State: APjAAAVkhr2paIV1qHJTgfX9ofcZU/1NdJiXvKEoF3DkwzHm9wW5Pv6K 0iHKHK1/7vh6T5+mlQHck5tbeFrQwKo= X-Google-Smtp-Source: APXvYqwGk9wconeG8Ip5Bn9Zczuemo8ldM4s9lLUjVCrnU7knLZ/lbQjyKVRA6T/XSYnuUUYo8ghzQ== X-Received: by 2002:a05:6a00:3:: with SMTP id h3mr2255810pfk.78.1575340188542; Mon, 02 Dec 2019 18:29:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/40] target/arm: Simplify tlb_force_broadcast alternatives Date: Mon, 2 Dec 2019 18:29:04 -0800 Message-Id: <20191203022937.1474-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 +++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b0130d814..6c09cda4ea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiall_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimva_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiasid_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimvaa_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3915,11 +3913,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1is_write(env, NULL, value); - return; + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); } - - tlb_flush_by_mmuidx(cs, mask); } =20 static int vmalle1_tlbmask(CPUARMState *env) @@ -4041,11 +4038,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vae1is_write(env, NULL, value); - return; + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4fmp+B7ZQONDNO2I4Fh6/DwMwJ80JOOXXH0hQuh4p3Y=; b=h7WCX4/WtKG58R2fDgzuV9CB44gpaAzfTgPkyShc5UhOatA+rCGEQbDUi4hcxwJqmC 0eqfu+ZK5ODq1ej4TOwtYaiUslkTdbB+pjq2Mh/qlblDPzD56SxV0WH5b7DDHb4wqNRT ZjCegX4zHb3NZasyU1ZeN19mk6eYq4NN+AUzWeumL1PPpa/PosNiw58lgr2i3CooX0vn PxTOsrkQVdIie1FVqMaujPe61i8RQB66TFmh8tdN+C8lNhHmpk9Eb8GZQHGoRPbf4Ebi cffI6ninrKX3ZO+cpWt/5dN+oQC+xPkgBoVcxmeuIq7Ef2sr8vtPlmMWxkpJFBA8BNw2 Zgkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4fmp+B7ZQONDNO2I4Fh6/DwMwJ80JOOXXH0hQuh4p3Y=; b=RwBxwrlvJwG92jKCb8V7zjEmFLTr+lzWPuHaEYM9Csu0PQVns97/WbGV6N/Q0BPbAZ 08ahqb1UDdGq9uI36XfQ6uyVPvHZZD3K9wxaBFSoDJaShccr0gZo9oytTwweS/yp/CQv wFvVuYEL/t2JHd2LoGjYTjtc2wQlrsrMF/SLyFvOyYSH7x8swmsWWXXe5eATI9VEyRHh QiNrpF/CcuJzdCmWxS9pqxtLNe5yPRA/jhBfMbY5VwnIr/+zA2Zcg8sewwMrYdNrfZbx +8zQWuAE9hD17KUx2O/zMU2kxUcZoqUUeBYa9T/ZEYTKE3SNsf7zxrrmpAaDNAbqroIX eo8A== X-Gm-Message-State: APjAAAUGYjxh3dWWOZQ1BM30+To5RdIoNw0JcKh84YGHKWjUp5D5SUrk LSNRcJh27XURTOOTJ1BLarA9CpvAY7s= X-Google-Smtp-Source: APXvYqywtAnLjuS7bvEe8rYRlnGtFIbwNhYTeOrvmeD48Yz3E4CQNncl6pRTGiXqGTAb+Z6ZN2f89g== X-Received: by 2002:a62:1687:: with SMTP id 129mr2386952pfw.44.1575340189548; Mon, 02 Dec 2019 18:29:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/40] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Date: Mon, 2 Dec 2019 18:29:05 -0800 Message-Id: <20191203022937.1474-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the EL1&0 regime. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/helper.c | 40 +++++++++++++++++++------------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 5 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9729e62d2c..802cddd2df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2864,8 +2864,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, #define ARM_MMU_IDX_COREIDX_MASK 0x7 =20 typedef enum ARMMMUIdx { - ARMMMUIdx_S12NSE0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_S12NSE1 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, @@ -2890,8 +2890,8 @@ typedef enum ARMMMUIdx { * for use when calling tlb_flush_by_mmuidx() and friends. */ typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_S12NSE0 =3D 1 << 0, - ARMMMUIdxBit_S12NSE1 =3D 1 << 1, + ARMMMUIdxBit_EL10_0 =3D 1 << 0, + ARMMMUIdxBit_EL10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, ARMMMUIdxBit_S1SE0 =3D 1 << 4, diff --git a/target/arm/internals.h b/target/arm/internals.h index f5313dd3d4..54142dd789 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: diff --git a/target/arm/helper.c b/target/arm/helper.c index 6c09cda4ea..d2b90763ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -670,8 +670,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS); } =20 @@ -681,8 +681,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS); } =20 @@ -3068,7 +3068,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUI= dx_S12NSE1) { + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUId= x_EL10_1) { format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |=3D arm_current_el(env) =3D=3D 2; @@ -3167,11 +3167,11 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) break; case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ - mmu_idx =3D ARMMMUIdx_S12NSE1; + mmu_idx =3D ARMMMUIdx_EL10_1; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ - mmu_idx =3D ARMMMUIdx_S12NSE0; + mmu_idx =3D ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3229,10 +3229,10 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3531,8 +3531,8 @@ static void vttbr_write(CPUARMState *env, const ARMCP= RegInfo *ri, /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ if (raw_read(env, ri) !=3D value) { tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS); raw_write(env, ri, value); } @@ -3893,7 +3893,7 @@ static int vae1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } } =20 @@ -3929,9 +3929,9 @@ static int vmalle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2= NS; } else { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } } =20 @@ -8671,8 +8671,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) */ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { + mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0); } return mmu_idx; } @@ -8715,8 +8715,8 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) return true; default: return false; - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: g_assert_not_reached(); } } @@ -10620,7 +10620,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11148,7 +11148,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { - return ARMMMUIdx_S12NSE0 + el; + return ARMMMUIdx_EL10_0 + el; } } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4bebbe629..2703ebf32a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) ARMMMUIdx useridx; =20 switch (s->mmu_idx) { - case ARMMMUIdx_S12NSE1: - useridx =3D ARMMMUIdx_S12NSE0; + case ARMMMUIdx_EL10_1: + useridx =3D ARMMMUIdx_EL10_0; break; case ARMMMUIdx_S1SE1: useridx =3D ARMMMUIdx_S1SE0; diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d5d4bd888..e3deea50e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) */ switch (s->mmu_idx) { case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0); + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: + return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340567; cv=none; d=zohomail.com; s=zohoarc; b=fS9Di/DVU6E8WM0HKON/bwyIZRlHuyuUPE2oxZq9QoPzefNmXq12mYMhOHJla0PTDGqVjaBfnPt2yop8Oe/0d6W3ZhZGrtcMLd1aF8SLbG3u5bCYa8ThupO4uim2+bBiBlZ4rh/la6AjNRfGHxGfs2xn9RYZNLghTBS/Ve2iGLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340567; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9298xhTmvXNu+8P+Gy8ST3y6QgYH5tl8FVXemGU4CpA=; b=HUHbYcT1r4iSKymyVAA9XTwe5bZXwiNbkSxFcrrBcuxLX8TxEJ2xx0N2ZEa6Tt8F4q jwmYON+E1mqUXAeMsfYh8DkWU+otW+xXUfxMF7eyDfmOmmNV6Kh0NW2SU7b41AHNQSD5 5V5/SnQ+QaqYruaelYLd+4q0Z7kdmtrjAw+cgveWgtghlLp5FhBhtYyypHXIuPvYIdIM YT9XJQEQKz+Q6hjLEb5vHVHUvA+tJHu5gDoCHY7Uv/6fK7SMgl561AHfMkM4BxmylSiO 3tsZyNlry5ODDHyTWcrMhiCBWw33/GJ0fQ5qcQVQOBcV8FTf/sOsJKgp2JoXK30JdpG8 u0KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9298xhTmvXNu+8P+Gy8ST3y6QgYH5tl8FVXemGU4CpA=; b=DYflJ4mhxGAoEoXhBWtB5PPjduZSE9A7h2akIipxtVU/wmmUo549NSu92uy04ocHqE 94hVgpa/a491Wak2h+Mp7NcfY5ObN1SC3NlweDLIu1B8u1YTuOLOCumfPNyKlmBHHz3X uIL6EOgVWBn2ISWScH8u+8bOjSAcobuwhhkrL4gl2/gxER2GSN4JFoSUv7dSvbHHFE3j MY3WMu2evTNugdOu6pK8gGAZkvWZZgDiEJ+ZdMDPPcGu3Mxe5VqPc4jsGhDw7BXqg/WP z9gzccxqmo+RFzEWELu3VhsGwYSkCRh8oByoHYcN0NCfnigs5OrHK4MId2cTGVmRkALR Wtjw== X-Gm-Message-State: APjAAAVqqvcctfoM7JHM+QpWl1Ef1UX28a1KAW1YG8pfxtydlaYSyVjl 6vf6FAyMa/3+xNNlcOpvVsvfUqDuc7A= X-Google-Smtp-Source: APXvYqwbzbOm2CMiV/2h1p/4NsoV8rYM7xqSiHDSdJmU/Rh3Wi0q8VzVnkejLFUXSntXGW/B2VFrLw== X-Received: by 2002:a63:5851:: with SMTP id i17mr2754191pgm.181.1575340190925; Mon, 02 Dec 2019 18:29:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/40] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Date: Mon, 2 Dec 2019 18:29:06 -0800 Message-Id: <20191203022937.1474-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The EL1&0 regime is the only one that uses 2-stage translation. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 +-- target/arm/internals.h | 2 +- target/arm/helper.c | 57 ++++++++++++++++++++------------------ target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 5 files changed, 35 insertions(+), 32 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 802cddd2df..fdb868f2e9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2870,7 +2870,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_S2NS =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, @@ -2896,7 +2896,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1E3 =3D 1 << 3, ARMMMUIdxBit_S1SE0 =3D 1 << 4, ARMMMUIdxBit_S1SE1 =3D 1 << 5, - ARMMMUIdxBit_S2NS =3D 1 << 6, + ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, ARMMMUIdxBit_MUserNegPri =3D 1 << 2, diff --git a/target/arm/internals.h b/target/arm/internals.h index 54142dd789..ca8be78bbf 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -813,7 +813,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: diff --git a/target/arm/helper.c b/target/arm/helper.c index d2b90763ca..97677f8482 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -672,7 +672,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -683,7 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -704,7 +704,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 pageaddr =3D sextract64(value << 12, 0, 40); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); } =20 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -720,7 +720,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const = ARMCPRegInfo *ri, pageaddr =3D sextract64(value << 12, 0, 40); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3528,12 +3528,15 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ + /* + * A change in VMID to the stage2 page table (Stage2) invalidates + * the combined stage 1&2 tlbs (EL10_1 and EL10_0). + */ if (raw_read(env, ri) !=3D value) { tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); raw_write(env, ri, value); } } @@ -3929,7 +3932,7 @@ static int vmalle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2= NS; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -4083,7 +4086,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, =20 pageaddr =3D sextract64(value << 12, 0, 48); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); } =20 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, @@ -4099,7 +4102,7 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *en= v, const ARMCPRegInfo *ri, pageaddr =3D sextract64(value << 12, 0, 48); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, @@ -8560,7 +8563,7 @@ void arm_cpu_do_interrupt(CPUState *cs) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: case ARMMMUIdx_S1E2: return 2; case ARMMMUIdx_S1E3: @@ -8614,7 +8617,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } } =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* HCR.DC means HCR.VM behaves as 1 */ return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } @@ -8645,7 +8648,7 @@ static inline bool regime_translation_big_endian(CPUA= RMState *env, static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return env->cp15.vttbr_el2; } if (ttbrn =3D=3D 0) { @@ -8660,7 +8663,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env, = ARMMMUIdx mmu_idx, /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return &env->cp15.vtcr_el2; } return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; @@ -8847,7 +8850,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, bool have_wxn; int wxn =3D 0; =20 - assert(mmu_idx !=3D ARMMMUIdx_S2NS); + assert(mmu_idx !=3D ARMMMUIdx_Stage2); =20 user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); if (is_user) { @@ -8939,7 +8942,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, ARMMMUFaultInfo *fi) { if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && - !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; int s2prot; @@ -8956,7 +8959,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, pcacheattrs =3D &cacheattrs; } =20 - ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, + ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa, &txattrs, &s2prot, &s2size, fi, pcacheatt= rs); if (ret) { assert(fi->type !=3D ARMFault_None); @@ -9428,7 +9431,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR_EL2 */ tbi =3D tbid =3D hpd =3D false; } else { @@ -9489,7 +9492,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState= *env, uint32_t va, int select, tsz; bool epd, hpd; =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR */ bool sext =3D extract32(tcr, 4, 1); bool sign =3D extract32(tcr, 3, 1); @@ -9591,7 +9594,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, level =3D 1; /* There is no TTBR1 for EL2 */ ttbr1_valid =3D (el !=3D 2); - addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_S2NS ? 40 : 32); + addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); inputsize =3D addrsize - param.tsz; } =20 @@ -9642,7 +9645,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, goto do_fault; } =20 - if (mmu_idx !=3D ARMMMUIdx_S2NS) { + if (mmu_idx !=3D ARMMMUIdx_Stage2) { /* The starting level depends on the virtual address size (which c= an * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to @@ -9742,7 +9745,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, attrs =3D extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* Stage 2 table descriptors do not include any attribute fiel= ds */ break; } @@ -9773,7 +9776,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, ap =3D extract32(attrs, 4, 2); xn =3D extract32(attrs, 12, 1); =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { ns =3D true; *prot =3D get_S2prot(env, ap, xn); } else { @@ -9800,7 +9803,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, } =20 if (cacheattrs !=3D NULL) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0, 4= )); } else { @@ -9821,7 +9824,7 @@ do_fault: fi->type =3D fault_type; fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_S2NS); + fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2); return true; } =20 @@ -10635,13 +10638,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong= address, prot, page_size, fi, cacheattrs); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { *phys_ptr =3D ipa; return ret; } =20 /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2= NS, + ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_St= age2, phys_ptr, attrs, &s2_prot, page_size, fi, cacheattrs !=3D NULL ? &cacheattrs2 := NULL); @@ -10683,7 +10686,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, /* Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. */ - if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_S2NS + if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 && !arm_feature(env, ARM_FEATURE_V8)) { if (regime_el(env, mmu_idx) =3D=3D 3) { address +=3D env->cp15.fcseidr_s; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2703ebf32a..3a39315a6c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -119,7 +119,7 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_S1SE1: useridx =3D ARMMMUIdx_S1SE0; break; - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: g_assert_not_reached(); default: useridx =3D s->mmu_idx; diff --git a/target/arm/translate.c b/target/arm/translate.c index e3deea50e0..1716bbb615 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -172,7 +172,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPrivNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: default: g_assert_not_reached(); } --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340844; cv=none; d=zohomail.com; s=zohoarc; b=PHQBqmrdor9GIdTiWHZ9IpGkCODGOT0iHTp7MeFtUumhnV/pAFYQqBSeGXlXWUMInXaZ/aILJXDKJOXK5ygAPza0gCPc93E5QeV3PYpQvtOzBDlpIUyDJrRGBWa8DWWkemkMXglvqerPj7ZnvKky1fEHp4/STBrj84R98+pLhNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340844; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=tLWF7lZ5KzCCuuF9ZSK7qlYg+vYwOMe91hFIJnibsig=; b=iJTZEeVUsC4qUIiU2N8xcxyvDkamzges5YLzbKnmcFcLN3LzluwZlTP+NT8oXyH26wbC4h/x/O3DmMhXWs2IsPrvWX25IPiL7LkPXlIp9Cq0/MxaFhqb6kTiDNC4Ts8qkpxPT2LLZf559pbngcGyji1978q0VtfRlBboeIaNyoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157534084472182.99378030731043; Mon, 2 Dec 2019 18:40:44 -0800 (PST) Received: from localhost ([::1]:47264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby7H-0005io-D7 for importer@patchew.org; Mon, 02 Dec 2019 21:40:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60025) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwt-0003Bu-1j for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwq-00089r-Tq for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:58 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:40803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwo-00087P-RD for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:55 -0500 Received: by mail-pg1-x543.google.com with SMTP id k25so866647pgt.7 for ; Mon, 02 Dec 2019 18:29:53 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tLWF7lZ5KzCCuuF9ZSK7qlYg+vYwOMe91hFIJnibsig=; b=cv1FX3uMvtISefHU/db2SHYp5V2kJNZD/M/5R6xfRx1rUKiL7VKZJWfAR4OqABkEE2 T9WkT5hn+iVjcqyiONq3BrZmJ9IiRqBLsDMnE2WT925386RB7b9y39opJS9i7lDnoa5o yJpJ3lqloKLfxAgc5BvUWgn1Bf2Bvmh13FfLyde+PHhbhjS9K3AoEFPfKtCyu24ndLyS OxCrdeg3bNKb+Yf4rGwV34tQnYxNxwj8EbZWSpfhFrWjzWTTp1RNq8bRz/U7ITlqokD1 Bp/DsxPvqMSRmhOJwK09Q6Ksd3uCpJHBGJ157XbwisV8e1f88xwfO5zt/WoKvjwxbzmQ pv+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tLWF7lZ5KzCCuuF9ZSK7qlYg+vYwOMe91hFIJnibsig=; b=JriqLp6+Z4eLlkNlUf61xofLZt2bF/V8qJ91PtbKnD4XdPIltcbJhAI1TVu+PkR2kR bQkbFgsVZT4g9G0yWrFg2ihewlX+0vKZe/C7wsmcDZNxZBzRwm15dea1rHpsTdWxtjLV SnSQAMnDlxtvVBOJ+3B51YcbrilHaYruQA75xtBOC/gI48xXzN8WJQ4H3IFzvs5dC8mh YBfsfAdtaXk+n2usKgNon+yYqKU0LdNEE60amiXSvB+3cLbGcU6mNCCTK1e7AZCaQ6NS SxasYi8SEBxgSKlgvfUkpKSodJHnz+J7/RJFh+wlFycaJBqgaKMDyvyMIVdD+2jJLJck T1AQ== X-Gm-Message-State: APjAAAVESpbWywANusHvbU/JFVQS+YOzeY1OwB8ENM5LY011Mf/kReEG 16NEvzEThIo+kP7NfjnaQTWEXQeZ940= X-Google-Smtp-Source: APXvYqzIEUUPt6YRBzWZg1w/aImc1i7a/bsVIbifT6qIAVVOsO37jhM62WzUJn6KYRY7WadyRbxb1A== X-Received: by 2002:a63:483:: with SMTP id 125mr2782929pge.217.1575340192352; Mon, 02 Dec 2019 18:29:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/40] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Date: Mon, 2 Dec 2019 18:29:07 -0800 Message-Id: <20191203022937.1474-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/helper.c | 27 ++++++++++++++------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdb868f2e9..0714c52176 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2882,8 +2882,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* Bit macros for the core-mmu-index values for each index, diff --git a/target/arm/internals.h b/target/arm/internals.h index ca8be78bbf..3fd1518f3b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_S1E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); #ifdef CONFIG_USER_ONLY static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { - return ARMMMUIdx_S1NSE0; + return ARMMMUIdx_Stage1_E0; } #else ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 97677f8482..a34accec20 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2992,7 +2992,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, bool take_exc =3D false; =20 if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) - && (mmu_idx =3D=3D ARMMMUIdx_S1NSE1 || mmu_idx =3D=3D ARMMMUId= x_S1NSE0)) { + && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 + || mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -3140,10 +3141,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1E3; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3156,10 +3157,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1SE0; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3213,7 +3214,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3226,7 +3227,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; @@ -8571,8 +8572,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_S1SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8630,7 +8631,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } =20 if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { + (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -8675,7 +8676,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0); + mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_EL10_0); } return mmu_idx; } @@ -8710,7 +8711,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -8941,7 +8942,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && + if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340766; cv=none; d=zohomail.com; s=zohoarc; b=S03sh7hA0ZQfDp/dZJ2J8B9fvIGAujGWlb+iLkTKXri/XULjwjCRiIZLra4VH+S4kUaW5LOWmD+33siXrSjbEiAI1GhjIbJruOmqLTHlzgQ0ufVP5tgNyuxtVN3C9X+dyKXyybsSzDDjh9QmekoqyFenizTKKxlFKmVIVWlyDck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340766; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=WeZRzsGyAYlGhck3WxuFXMlnAxw7pFnicVDnjAR9k4Q=; b=d7t3DjuO61hqmbdrGcGemAqBmUvKsWTAj4TWrDfmGRH3faLLGr7yfO3KxQH+/AnmqBwT6tgz44UZKtmeYK9UB+SkXghb8y16ow1kVIhiYVjXTT4GhWYcY0EziUGYHdceZYOMyVBstYbjmHaBMi5REaJEJlpb9Z4kAFwDhAyMia8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575340766954645.7544588484785; Mon, 2 Dec 2019 18:39:26 -0800 (PST) Received: from localhost ([::1]:47248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby61-0004Cr-OF for importer@patchew.org; Mon, 02 Dec 2019 21:39:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60022) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwt-0003Bt-2Y for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwq-0008A3-US for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:58 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45213) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwq-00087a-Dh for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:56 -0500 Received: by mail-pf1-x443.google.com with SMTP id 2so963437pfg.12 for ; Mon, 02 Dec 2019 18:29:55 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WeZRzsGyAYlGhck3WxuFXMlnAxw7pFnicVDnjAR9k4Q=; b=x7+sWNn1LjIC60mkzA5oK58DcLGLIyuMKyGN7/eGd0n30X1CncrOw3Grhqdn08qX7X 9PRE2IBm1dHI3wB9kttp5KsF1DCjwdEleSHPqb7xuZFzi2u4BDKTpjZKcmA7hR5Jxg48 TCKpHP7VJg8iwjShYsxE4R9Liews5WQWKWyubqKs0u8R1A04SzTfYxZAdbCb95hh+C3w fib96yXtioiaPF5yd5/nbCD9HmLaw43IPysuK1T5FUwuN3SuuZpgbg3BC34o1Lw21Ph7 64M/Q2L/EKrB5LrKdgdfGxAm3k62aRiSEHuXPrstSczlo47SCDxJhnkmnUxZR1mzI2lE H4wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WeZRzsGyAYlGhck3WxuFXMlnAxw7pFnicVDnjAR9k4Q=; b=Qm5OOtPx50hBKNSTZoofzwwggyBEvHh/q0i7eJzUsNgakIfQEkvKj5EwepylbwSfn7 vL4STuJ7fiJlMTZHDBi3e8WFt+wwEDbTYFYNIR/C7hgkynmbn0/yQyV5XMtSu7kdEMCI A4VGMwYtPPOpPDmxwwYyrH1cMThFjCAP1EXDVSXKXtULmprSpet2dMd0Cup8k+Jw1VJL oq6q+XLe8mls+qk+g0XYxI5CNjboZCqGpDa5Si9AcMU73Q3bBt3NafofhJuv4bvHCgct 4WkMbloQ/hq/p+jTtue4ZfAjyko/Cnmnny1Fh1mRapbENX3QoQCysFfRPZjIm+Gnn8DZ pHZg== X-Gm-Message-State: APjAAAXZhPKO/dGH1LM9H7Nct5hmuGG7DQWUbe/fncgHGzVszO32s5zq M8RwAECrv8TdhMANLF9lJWnfwvxFSkI= X-Google-Smtp-Source: APXvYqzNGtNXNamyImUkSHZKZJW0Lcp9NPZszqrC6LW3/7LhVpEfREM1H1CKHxlHk/7Ov/C4TXNkng== X-Received: by 2002:a63:d551:: with SMTP id v17mr2867349pgi.365.1575340193900; Mon, 02 Dec 2019 18:29:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/40] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Date: Mon, 2 Dec 2019 18:29:08 -0800 Message-Id: <20191203022937.1474-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The Secure regimes all have a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- target/arm/helper.c | 26 +++++++++++++------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0714c52176..e8ee316e05 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2868,8 +2868,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, @@ -2894,8 +2894,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, - ARMMMUIdxBit_S1SE0 =3D 1 << 4, - ARMMMUIdxBit_S1SE1 =3D 1 << 5, + ARMMMUIdxBit_SE0 =3D 1 << 4, + ARMMMUIdxBit_SE1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, diff --git a/target/arm/internals.h b/target/arm/internals.h index 3fd1518f3b..3600bf9122 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/translate.h b/target/arm/translate.h index dd24f91f26..3760159661 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,7 +124,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the high= er of * 1 or the current EL. */ - return (s->mmu_idx =3D=3D ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) + return (s->mmu_idx =3D=3D ARMMMUIdx_SE0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index a34accec20..377825431a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3144,7 +3144,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3154,13 +3154,13 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1SE0; + mmu_idx =3D ARMMMUIdx_SE0; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3214,7 +3214,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3227,13 +3227,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; + mmu_idx =3D secure ? ARMMMUIdx_SE0 : ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3895,7 +3895,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, static int vae1_tlbmask(CPUARMState *env) { if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -3931,7 +3931,7 @@ static int vmalle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; } else { @@ -8569,9 +8569,9 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) return 2; case ARMMMUIdx_S1E3: return 3; - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: @@ -8710,7 +8710,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env= , ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11150,7 +11150,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } =20 if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return ARMMMUIdx_SE0 + el; } else { return ARMMMUIdx_EL10_0 + el; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3a39315a6c..885c99f0c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_EL10_1: useridx =3D ARMMMUIdx_EL10_0; break; - case ARMMMUIdx_S1SE1: - useridx =3D ARMMMUIdx_S1SE0; + case ARMMMUIdx_SE1: + useridx =3D ARMMMUIdx_SE0; break; case ARMMMUIdx_Stage2: g_assert_not_reached(); diff --git a/target/arm/translate.c b/target/arm/translate.c index 1716bbb615..787e34f258 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: + return arm_to_core_mmu_idx(ARMMMUIdx_SE0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340952; cv=none; d=zohomail.com; s=zohoarc; b=JdMi5lF5oryBhY/HRvB06df+IwRU3hyrtcdZ2j06YEacqXdEzw7VayBKaAhXOU5os7Vf2UO+6jYKbghnt7mnmWPZxSjsyCqIYyMODnHDduW9qMoP6LtW5hyjoepvHYzVsSQT8VEL7yzKnttECU3AycSaFdlrjtaX9/VuzYGxoKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340952; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=we7uKubwThcukqtbMWKoh/5FH/qTILtxBXRWHVaXUD0=; b=Za6sxxACyqJT+2QxMEj8lMg5rIJTUFBudsmU7n9si1iaf3byeIs1Rl1L+F8sZKZrDi Moia2Tv9gL9MKLtncZ+jhXqGhaiOwCJyQ6PYfb/NFwVA0adKJYYpl18zbD7nWbBTNaBC N22OE9aBwR+xKyCTbjZ39UPRhVXGMVuuEoMUIlJrsCKGJdxh+gtm7to0UTkL3GiHHweB /RNhVdF56LKtZ+5AImk65GwrAzz+JkSdal4glPiL3J+5EziAy+16WIXp5tljuoOhfjhR 61iPXxgPdtXYcRaMn0PwPoQJ59ytqgoT+SbGJgF2wAxhfj/JqMCw41aw7T+7jsAIh7md 41Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=we7uKubwThcukqtbMWKoh/5FH/qTILtxBXRWHVaXUD0=; b=h2T7wsj3WQHUa1gUtrJzYgMQHQ0FC314ova3r+69qZtZ3hRM1HBP63TnxPLGyaRrPK 8zRpDAQFl7TqbBT38VGhZM5SZedTZEPIapptQi3rUEOsI0gMhNa7+YH2dcLh7dkCHlNO Ws4Coro6puyemRHuExxMKwMDHlOE6JeTtmGluEor8K35ojE9j7sTXwN5Uhbvrc3a6KuZ wDXLZoZyEmwcix0e6QTugWcDXOc+i1vHgj2XsQY8GhB73GURJKLHTyL9ZvIp7m+FJQuj K+4riTDXPUQUhkFlT/UxgU2br5j8SEWjM0qjD3Jl0w62nVXAecVazque9xMdMkDCvNJ6 KMTA== X-Gm-Message-State: APjAAAXMNnSYBAKRIeXutJ2JUzT+eu+I29PlaYKVKXiWKky8/xWsSO/j yk/8rdKA9fkEBHq1+XK7pp5no4zfA6g= X-Google-Smtp-Source: APXvYqzqNKDji+ipg536Uum1P4M+MT7vVpuBh5p3X0e7clgwhCPxmbuQd6Vt7kF2Nhl8uGSetH6Rlg== X-Received: by 2002:a63:e94d:: with SMTP id q13mr2898684pgj.160.1575340195058; Mon, 02 Dec 2019 18:29:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Date: Mon, 2 Dec 2019 18:29:09 -0800 Message-Id: <20191203022937.1474-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The EL3 regime only has a single stage translation, and is always secure. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 14 +++++++------- target/arm/translate.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e8ee316e05..f307de561a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2867,7 +2867,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, @@ -2893,7 +2893,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_0 =3D 1 << 0, ARMMMUIdxBit_EL10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, - ARMMMUIdxBit_S1E3 =3D 1 << 3, + ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE0 =3D 1 << 4, ARMMMUIdxBit_SE1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, diff --git a/target/arm/internals.h b/target/arm/internals.h index 3600bf9122..50d258b0e1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: return false; - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: case ARMMMUIdx_MSPrivNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index 377825431a..98d00b4549 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3138,7 +3138,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1E3; + mmu_idx =3D ARMMMUIdx_SE3; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E1; @@ -3220,7 +3220,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D ARMMMUIdx_S1E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_S1E3; + mmu_idx =3D ARMMMUIdx_SE3; break; default: g_assert_not_reached(); @@ -3963,7 +3963,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -3988,7 +3988,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4016,7 +4016,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4065,7 +4065,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E3); + ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -8567,7 +8567,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_Stage2: case ARMMMUIdx_S1E2: return 2; - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: return 3; case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 787e34f258..6cf2fe2806 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: return arm_to_core_mmu_idx(ARMMMUIdx_SE0); --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341003; cv=none; d=zohomail.com; s=zohoarc; b=NJzalhkF7qYa1zh15m3fIoauaVtiNnD+csxq0k7YAhrcdQA6Nrwz7cSNtOURz8NYvDUFVuBxbefiz86O0eJnr6ZQk4WrrM0UEchuFA2om79OlwoJ7qu0FYHEX+9SztfZuZEZUae1O1BN9f3yUySczCPICz7aaSHc/nsm6rt9V4U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341003; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=TJ8VFkgn78UHhlIDXlM380ufAZvl0W+vGuMVGwxrYbQ=; b=mnXmQjnSN/UP/PKd71YLs42xQwyh+eUUJZQiRYqkjcVMZzLL92wsiBrb+QikQ5qfhPQTcg80livQ/SYcOiP6qWNkGjI07OR8pZjDiwK13XAuQw8muAlmYrZydEMoDp1QPJ1F69y10VHOYhyHL/D2MNDPK0VWbUTAfSb58FEzcsY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341003685537.3046117705142; Mon, 2 Dec 2019 18:43:23 -0800 (PST) Received: from localhost ([::1]:47320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby9q-0001LV-75 for importer@patchew.org; Mon, 02 Dec 2019 21:43:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60237) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwv-0003Do-Jj for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwt-0008Bk-3w for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:00 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46430) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxws-0008AE-SV for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:59 -0500 Received: by mail-pg1-x541.google.com with SMTP id z124so850700pgb.13 for ; Mon, 02 Dec 2019 18:29:57 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TJ8VFkgn78UHhlIDXlM380ufAZvl0W+vGuMVGwxrYbQ=; b=LAGwsyYScIAPwk7of6Sx5F1o+VCIENoLghJ0Zt44wDSHmLCffY0y+H1R4zeFJuqaIA GruzynNm76hNi4PjsCL18r9IsdPj8NAqk/pvtAT2CKBB4DcfByw+uMsNf5J9qpSIKSJW WDlnn4LXSDru5sZKLe1RLtk6AycUTlCDubg9gNHXEJUGusSO2bdcXI9bg86AqZIoc9Gm YsknYigcUZ3AOEKd9PSD+2JyFMbY9uwtRPyJ/k3VoTi5NFo/CuDVZaTxtBEFvBe0kXSa 1SjddyB6TnjQcTs3vFizTpM16agWLHHKL7wcHH23R0JIBdxqR3HhZqyhDeuorMM14s4K 7D8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TJ8VFkgn78UHhlIDXlM380ufAZvl0W+vGuMVGwxrYbQ=; b=Xe52Bbbof6J05Cd/T2x/2Bp0IvwCOqSxkLzTM4HNjQzXbxVpzWGMJDgpqBZfddeNGu oTGb2Vxl94Mp7vXvJGRGtHr8lXjIiQ/7Ud9kfjJfvDhmBjbc5N04lK2kMUBao46izI19 8qf72plDipGvIHlkH6IqgAQff8HOF+Jk182JsQMGnyyZyiKpP1u40/2JQJS+6f54JFsL IQMh/XW7APYd6LT14vD6RgksVbRImjJzIf++UZWnCoNCr5ulGt8tw/1zmaa1zIg1nE4B WHM/X9J/VtqBDGs+d0xpRJj8+iGrf+AD4/ubZp/iwwCPU0HmAdhzF2KhTvFL3nLMwk8X Hg+A== X-Gm-Message-State: APjAAAWuEtTfVvwzXYXVd4AZtvehvdtNKtFVTQcJIHldXHIOYC6NK2uU +tD1oavtIrW6K9GQ9nsfZCECDaVkn9Y= X-Google-Smtp-Source: APXvYqzVahw2s02WtqFsNVV+Gd99cNUVxIXweipOmeqxDa1v8irOIzG/1Bp/e+7bg9PX9gntF2UbLQ== X-Received: by 2002:a65:5c48:: with SMTP id v8mr2842243pgr.419.1575340196446; Mon, 02 Dec 2019 18:29:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Date: Mon, 2 Dec 2019 18:29:10 -0800 Message-Id: <20191203022937.1474-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 22 +++++++++++----------- target/arm/translate.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f307de561a..28259be733 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2866,7 +2866,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, @@ -2892,7 +2892,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_0 =3D 1 << 0, ARMMMUIdxBit_EL10_1 =3D 1 << 1, - ARMMMUIdxBit_S1E2 =3D 1 << 2, + ARMMMUIdxBit_E2 =3D 1 << 2, ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE0 =3D 1 << 4, ARMMMUIdxBit_SE1 =3D 1 << 5, diff --git a/target/arm/internals.h b/target/arm/internals.h index 50d258b0e1..aee54dc105 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_EL10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index 98d00b4549..5172843667 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -728,7 +728,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -736,7 +736,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -745,7 +745,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -755,7 +755,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static const ARMCPRegInfo cp_reginfo[] =3D { @@ -3189,7 +3189,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -3217,7 +3217,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -3954,7 +3954,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3980,7 +3980,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4002,7 +4002,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4055,7 +4055,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -8565,7 +8565,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage2: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 6cf2fe2806..51ea99e6f9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5/YAtKa3WnIkaYSpx8eXnl6bZdS/00Vj/dGucoxzJq8=; b=plT/L3/7AR9eHO+T+YyHlYlqgi5/NCgbuLn2gyH7nCSkgAy83Q+WyBVEQNuwpOKG45 tIBZOCQAvSboNU8k2M8GbejQqOcSrkFwT9u4OOTR44a9r1oeOyR2JJonqrV5ruKLW/rm OYM/6T/svGXwotj9xIf2zNJX4rpgisghRXLnK/CdmVF+ZzzUS9AiCRnaCRv7DWBPvO8Z KHjGlxlmPkutZEMYAWzhdObCpYaw1qjehJDOtyrhlEaYWEKCURoJH06dBHwXpt0mas2Z aJP9PZ3OaFD25E5maVwEejcHNlNZwpyT+Vk6UWrm4IxSb6oFSCOiyuNV3PE2hh4h7TC9 XodQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5/YAtKa3WnIkaYSpx8eXnl6bZdS/00Vj/dGucoxzJq8=; b=bge+vV1mNr2zZtdDBDqIhgB2tr9UNU6BkY+pd9mf2cscz7SonFY4Jb/CSsfLZSC6Bf WAVkWDXm4uUp7YOP1b4DprUQUgh0jMjGNZu431S1mzfUy4gQw9gzX9rmmcbIXDfWgXtN NiJbJAr43jArEg/bhZ1Lxie6HuI/5oBR6DA5OExJr2Jn2nVFAyGUEG7pTVy1rEXrJEjT bXP3sJmMXMh7MUVTG6UHgcJqbYlR0ploOxp1M+NKSVSqRhI3mpH00KftEUtHEzDnr2ty /Yst2lUlnRYne7PFW+NK9/KZ8j7t2NsTLkSVP2PU3DAcNBtvFeoLAqXa4cSnt4bkFmkj NcfQ== X-Gm-Message-State: APjAAAVzKiGOG0tbYhz9rJsDHqc1E/Z9co/uo7WyXT9GcPZoORLqmT/R F7c9uVlymM0ArdNvZCrXY0nhDgaFCNA= X-Google-Smtp-Source: APXvYqy5DE+VKjmgt1WG4K8GNTSJSUPPHFCB6Q8C9IO0UyhBwgzmgK22jVN/+m13yBI3nM7a6nRGfw== X-Received: by 2002:a17:902:7205:: with SMTP id ba5mr2580962plb.95.1575340197732; Mon, 02 Dec 2019 18:29:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/40] target/arm: Recover 4 bits from TBFLAGs Date: Mon, 2 Dec 2019 18:29:11 -0800 Message-Id: <20191203022937.1474-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We had completely run out of TBFLAG bits. Split A- and M-profile bits into two overlapping buckets. This results in 4 free bits. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 52 ++++++++++++++++++++++++--------------- target/arm/helper.c | 17 ++++++------- target/arm/translate.c | 56 +++++++++++++++++++++++------------------- 3 files changed, 70 insertions(+), 55 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 28259be733..ae9fc1ded3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3188,38 +3188,50 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) =20 -/* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ -FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ +/* + * Bit usage when in AArch32 state, both A- and M-profile. + */ +FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ + +/* + * Bit usage when in AArch32 state, for A-profile only. + */ +FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) +FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) +FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. = */ +FIELD(TBFLAG_A32, SCTLR_B, 15, 1) /* * Indicates whether cp register reads and writes by guest code should acc= ess * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. = */ -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ -FIELD(TBFLAG_A32, SCTLR_B, 16, 1) -/* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ -/* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ -/* For M profile only, set if FPCCR.S does not match current security stat= e */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ -/* For M profile only, Handler (ie not Thread) mode */ -FIELD(TBFLAG_A32, HANDLER, 21, 1) -/* For M profile only, whether we should generate stack-limit checks */ -FIELD(TBFLAG_A32, STACKCHECK, 22, 1) +FIELD(TBFLAG_A32, NS, 16, 1) =20 -/* Bit usage when in AArch64 state */ +/* + * Bit usage when in AArch32 state, for M-profile only. + */ +/* Handler (ie not Thread) mode */ +FIELD(TBFLAG_M32, HANDLER, 9, 1) +/* Whether we should generate stack-limit checks */ +FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +/* Set if FPCCR.LSPACT is set */ +FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +/* Set if we must create a new FP context */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +/* Set if FPCCR.S does not match current security state */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ + +/* + * Bit usage when in AArch64 state + */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5172843667..ec5c7fa325 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11207,11 +11207,8 @@ static uint32_t rebuild_hflags_m32(CPUARMState *en= v, int fp_el, { uint32_t flags =3D 0; =20 - /* v8M always enables the fpu. */ - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - if (arm_v7m_is_handler_mode(env)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); } =20 /* @@ -11222,7 +11219,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env= , int fp_el, if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); } =20 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -11385,7 +11382,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.secure) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); } =20 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && @@ -11397,12 +11394,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * active FP context; we must create a new FP context befo= re * executing any FP insn. */ - flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED= , 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED= , 1); } =20 bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); } } else { /* @@ -11423,8 +11420,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } } =20 - flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); + flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); + flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b= its); pstate_for_ss =3D env->uncached_cpsr; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 51ea99e6f9..cd757165e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10841,37 +10841,46 @@ static void arm_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); - dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); - dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; - condexec =3D FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); + dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB); + condexec =3D FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC); dc->condexec_mask =3D (condexec & 0xf) << 1; dc->condexec_cond =3D condexec >> 4; + core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); - dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); - dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); - dc->vec_stride =3D 0; + + if (arm_feature(env, ARM_FEATURE_M)) { + dc->vfp_enabled =3D 1; + dc->be_data =3D MO_TE; + dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER); + dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && + regime_is_secure(env, dc->mmu_idx); + dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK= ); + dc->v8m_fpccr_s_wrong =3D + FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG); + dc->v7m_new_fp_ctxt_needed =3D + FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT); } else { - dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); - dc->c15_cpar =3D 0; + dc->be_data =3D + FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + dc->debug_target_el =3D + FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); + dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + } else { + dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); + dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + } } - dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); - dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); - dc->v8m_fpccr_s_wrong =3D FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRO= NG); - dc->v7m_new_fp_ctxt_needed =3D - FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); - dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -10893,9 +10902,6 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; - if (!arm_feature(env, ARM_FEATURE_M)) { - dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TAR= GET_EL); - } =20 dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; =20 @@ -11332,10 +11338,10 @@ static const TranslatorOps thumb_translator_ops = =3D { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { - DisasContext dc; + DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; =20 - if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) { + if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341093; cv=none; d=zohomail.com; s=zohoarc; b=m5L56GyGd+CpHR/r2FyXEbOOMEGIH6JeS6hK07MfrZ/7NW5XDXE/P6D/MdW3/cL3tVi3hwCrCDambC247GU1XXlUExPUCl085vol38SYHnfahvW7RT7D2upFro+6xlmNNVP7Z8oHuQKHHXeHLfeksFIfVCZeKp7xgBOLFznEb/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341093; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=C5bF3i8DWT2f5RYnZflxU7iVnJmRJeE7IGuazbjeOWk=; b=mzHBVpSGkYg5JIoIQSKhPj5Y6q55Cy0n/FW6SIwLnPvALNoeDFike6E+L9xac6zFoCgvm3z46/RAipSwTT44aRj1wTXJm01G2DCtY8NwF3xrwnlOCdQ1sFeKRwIftRNXAPVabK0lzT8XAljcLeyx9WNHDp/WVGCD93m9Ei/ezGE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341093079921.9843815877824; Mon, 2 Dec 2019 18:44:53 -0800 (PST) Received: from localhost ([::1]:47356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyBE-0003it-Th for importer@patchew.org; Mon, 02 Dec 2019 21:44:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60455) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxB-0003HH-3W for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwz-0008HR-QO for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:08 -0500 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:33294) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwu-0008Cs-ME for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:01 -0500 Received: by mail-pj1-x1044.google.com with SMTP id r67so833027pjb.0 for ; Mon, 02 Dec 2019 18:30:00 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C5bF3i8DWT2f5RYnZflxU7iVnJmRJeE7IGuazbjeOWk=; b=fEud/aFLjXvpezvj1+nNR1bPr50j9b2EZrSJQOBkBtuRrWn0jVEYGKgqhJDck2dryb fQZuG4bbOX/Bx5Y6sYnCVK5Imb+pc4SaeS+S3Jy8hqhG9ihXaep5BUHYpFCJu8C0CBXF y/hss2b6tlpbQSvRjcCL28cf1pIBuBcsDcyYeRY6xg1Xy8YvY6bGvnkMReKglt8eUxKE 6ENkxnGk8ruknFYWqsNO6GFmu2tt155HLJ9sOQ9e1maByI639APyAEo25SqGalHYZt/U h9cQU6bZeTdTyGjj4wwcjpmh/VYuRpLZRD4hdN3Wp5JxIiRGO810ceKsSu7Q0ch0s9Vz SwnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C5bF3i8DWT2f5RYnZflxU7iVnJmRJeE7IGuazbjeOWk=; b=amm0c2t3ZbJVLt7o4t5ZH7TvZbh0kWFSKAjhrVq2COigs6t7K0SDna3tHzxkSjuKrQ tsUUQm95DhBgmdkoXcNxSnKY58+He0TzlH/xSBeK/tYO2tb1fulrcJ4u4ayTWZzZCOcs uo2HeKVYKCYO0PwUn7R6PJIdtiO+dJyA3hZjlD2IEDa/FYfsH1yvRuaE/N/4sMDp+x7G KIvijbSdLTaD3SlY2tQ72A4A+PtZnRFklYh+u+YCK9gVFNua+fXBq2JBW5EqqPycExco J3RRZ2FaW84/ts3w8jfViHXgU282rIcjZYChzA/CwFhCWCUcVNm3roxykJ/0jqc2G4dL m1Lg== X-Gm-Message-State: APjAAAVWPJ+NoRt1+sPuUec3YsvQP+uLN1N68SO+h/17OfqRtp++gATP AiVTvw2su9D0qb9wpxPpJ5/7PXIiofY= X-Google-Smtp-Source: APXvYqxQtr6DoUTtWrEuG244TmXbXnGT319VUhUwZUrIO8kkEjfjR3Ixw7/7hciLFuZvIcQfa72cYQ== X-Received: by 2002:a17:902:b68c:: with SMTP id c12mr2652690pls.126.1575340198790; Mon, 02 Dec 2019 18:29:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Date: Mon, 2 Dec 2019 18:29:12 -0800 Message-Id: <20191203022937.1474-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are about to expand the number of mmuidx to 10, and so need 4 bits. For the benefit of reading the number out of -d exec, align it to the penultimate nibble. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae9fc1ded3..5f295c7e60 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3176,17 +3176,17 @@ typedef ARMCPU ArchCPU; * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, MMUIDX, 28, 3) -FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 28, 1) +FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) -FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) /* * For A-profile only, target EL for debug exceptions. * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK = bits. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575340947; cv=none; d=zohomail.com; s=zohoarc; b=XOxxJLCsEOEnoDNtYke46kIpHLuN4QCLVluWmD/tfHt1gA1xS3BQWYaVtL6FUQiAMZG4Ci4B2BG6ISJIpqPyGKdYNVzppIQqiAAbIl6p94u0p/nvcXeWVgO39cQyY70YTtzvJIkhbKFsdzkK7SVZB7w6/RwHnKsLxljw7rqmyXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575340947; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=V6eJMgEVwwwLTOsUaAZFgTn7D/MmDBjIMWbldPsAU4M=; b=ZpNDF/Tk2ba0LUpQ3vD+RucGx2NWPLXWXOmXaIJ5vo21l1EkwAVkk2jtMhBuCk0GP+v59Hs2n4EA+am0q/XxALc/Vd+vbpegKdyEjhrhh/Vu9UQ4noW8TyRe1mT2QunOPq/ghnGNr17uNfsOOTqMexPIyhDmJIiDL974HdRkwac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575340947591665.6000029862943; Mon, 2 Dec 2019 18:42:27 -0800 (PST) Received: from localhost ([::1]:47312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby8w-0008EV-4x for importer@patchew.org; Mon, 02 Dec 2019 21:42:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60496) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxC-0003HS-Ae for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxx2-0008Id-TX for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:13 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:38384) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwv-0008Df-Lb for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:01 -0500 Received: by mail-pl1-x641.google.com with SMTP id o8so1006940pls.5 for ; Mon, 02 Dec 2019 18:30:01 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V6eJMgEVwwwLTOsUaAZFgTn7D/MmDBjIMWbldPsAU4M=; b=Kipn0Vqk3WbSdKRivLTyZ9SdBjOwGpI5MWlNzXmJxrYHZFev0iXfWCwTlwviruhC0W avq3pHuLS6uAdmEELtYoh8AKFLCcUEw9oONpGM4v+w5+L6yjXXYNCmYEP/BZG1SQEqwh QwhrYtM++brPiAreSh/Wj3K3P+LzSxC0xRYpJZbgzKdABSQhNjNWMIhXQICLxisED4xE mTzgHkTLebcKzBFItNDGOS9v3xpPES1/z9nOP26L4WIXCnEJAsyrnO5NSPGd2C0LI9Gs S7xeVmc2ProIdsZcNu9Gl1yqxfzo0e3PubYjrytbiTQEaeR4NNlfVVefI15ad3R1tKs2 HXZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V6eJMgEVwwwLTOsUaAZFgTn7D/MmDBjIMWbldPsAU4M=; b=aHdVBJ0YPzhhuWr9D8YCvZAyiM/23R5kAjLAQH4VMGV0GagRlEtNDMyhIz+DDpPvYP RkEbOm5eLmHDSvldvijGu1FjZFN0fUy6dZQYGAF2zID7A+z3eZDWwwe41jbdnHGx3wbo nl3WFSS72h9GIx+88OFU+bVOvo4ZFe9kfIcOwOyiTdDEwfs272IaW5VqJ7i2Jx440DoX 0aLfgrRhG083DwxCGvSoELAXXnosZAH+xc+G33PrTDtK4+oQ6j1pHJnG9bEsjU8mTvuK SyyekB34PNWlun4Dibszp/mjjK/HWoN1Hwc0LsPRHfTlaxvFVAYOr86XHOGdY1K0UFj2 3EPg== X-Gm-Message-State: APjAAAVme3qkQE+ZAWBeNAs8kxjOUAXlGfWVoVuJSczBt0yT2wwB6bUq hPjIUWcMggORB5lZmfiJFwkEjww8SnI= X-Google-Smtp-Source: APXvYqwKrM6643N2ZGeJSGw/Ipf/VUhHsDQZfcJT0WaOilx+SLLJpBTM08kdCXLF/vOjO3OpuuOFsw== X-Received: by 2002:a17:902:9b85:: with SMTP id y5mr2633984plp.334.1575340199965; Mon, 02 Dec 2019 18:29:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/40] target/arm: Rearrange ARMMMUIdxBit Date: Mon, 2 Dec 2019 18:29:13 -0800 Message-Id: <20191203022937.1474-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflexed in the bit definitions. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f295c7e60..6ba5126852 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2886,27 +2886,34 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 -/* Bit macros for the core-mmu-index values for each index, +/* + * Bit macros for the core-mmu-index values for each index, * for use when calling tlb_flush_by_mmuidx() and friends. */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_EL10_0 =3D 1 << 0, - ARMMMUIdxBit_EL10_1 =3D 1 << 1, - ARMMMUIdxBit_E2 =3D 1 << 2, - ARMMMUIdxBit_SE3 =3D 1 << 3, - ARMMMUIdxBit_SE0 =3D 1 << 4, - ARMMMUIdxBit_SE1 =3D 1 << 5, - ARMMMUIdxBit_Stage2 =3D 1 << 6, - ARMMMUIdxBit_MUser =3D 1 << 0, - ARMMMUIdxBit_MPriv =3D 1 << 1, - ARMMMUIdxBit_MUserNegPri =3D 1 << 2, - ARMMMUIdxBit_MPrivNegPri =3D 1 << 3, - ARMMMUIdxBit_MSUser =3D 1 << 4, - ARMMMUIdxBit_MSPriv =3D 1 << 5, - ARMMMUIdxBit_MSUserNegPri =3D 1 << 6, - ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7, + TO_CORE_BIT(EL10_0), + TO_CORE_BIT(EL10_1), + TO_CORE_BIT(E2), + TO_CORE_BIT(SE0), + TO_CORE_BIT(SE1), + TO_CORE_BIT(SE3), + TO_CORE_BIT(Stage2), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), } ARMMMUIdxBit; =20 +#undef TO_CORE_BIT + #define MMU_USER_IDX 0 =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341468; cv=none; d=zohomail.com; s=zohoarc; b=NNW+ChQKR0WeBL3fU2YQWNabaP2/jt1AQ7ry2ipxbTS/RxyynDyYsyYVR1jmB3g/Hqq2AFRphO9rB6p6bK+OU24WmY0uyheaZufDiPy4feJWMgSQhy5VmPRegyi2eiOlrc6cmA/5iBVDptu1IUEpg7793UXfuy0hMbmHH+Sryos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341468; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=lQbiu/SxmR9ri07lGyjSz1lcJZjKc1rywBJ6yn3nMng=; b=WSLHeKylLVhXmIUYi4xO+jOAhD+EU8FkNuAV7OHksvMM3/egr20mhIS6k/BQfjz7yc62xo3pKfo49A2fYIN+QGQnBgdxC5ubsOAWjJU63wGu5CKhEZHbv2wLCy/XfQztQ+9bf1g/nccgHhJOOtAPq/YyCTtm25N8ImOG95PeVUo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341468090359.1523047884201; Mon, 2 Dec 2019 18:51:08 -0800 (PST) Received: from localhost ([::1]:47490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyHK-00032Y-Ck for importer@patchew.org; Mon, 02 Dec 2019 21:51:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60728) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxD-0003Iw-2O for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxA-0008P0-5i for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:18 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:44391) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxx1-0008Ec-Kn for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:09 -0500 Received: by mail-pl1-x644.google.com with SMTP id az9so990953plb.11 for ; Mon, 02 Dec 2019 18:30:02 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lQbiu/SxmR9ri07lGyjSz1lcJZjKc1rywBJ6yn3nMng=; b=LDfre/tOQ28OmXBXhIvRmbsI9D3oWyEr2PIwdSXkCQfQQFF9KhUFgaZSNYmAuDuHPk +xO8D2tikvUlCC4nA1Hk0uqPqMdoy+9wztwdT0gEgP9zN+N2RIrPIwXzBtYGnigbJZui AbxZIPJra4TRXj/+A/xy4Wq13eoZhJQgxbz8MV3Mp6GQO8l556QMzND3SfhXnP0/sfUe m19smqWh4OGaHCp+B4E5WPk/UTJgDtoFXzrFemTZDZqS08yzZQY9jmgXMdQgratDlHG9 RX4Ra2o2rMr/+pNmeg/SHufpZgvkVpw/dOJ8oYX9d3TGTNvQMttFEK+8kH1JT7Xwl2qB SsiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lQbiu/SxmR9ri07lGyjSz1lcJZjKc1rywBJ6yn3nMng=; b=hDfEKJsoAQXGLouKOSo9S4oZfrKtkWzqn0+LP9+35E6exingF+hzMdX/i1jvTzY76C t/vdQqGHyz9voOciOPddIHDcnwAGhDs3UUCRcFUPXNbJtBr3Tv8t0uPcsZynikF67FJi l81I6SNGZUCMxBfE3HCrpt1gnUmZTacMdLChNhpDvImup1tQD0jOV/dt5E7YcL82aN6R tFbAp1sFu7NFdfPP0u07+jE8+tGDtD1+1bKpT+HRZGvpWxwgbngCBKxPAZizx5Dnucuh +fNCDmyg+yG+CSNEG5pMUwU23EJ6cz1fYs3fq19vn2MtyxgIVoLWo8MImSv3gTiXRxom uVCQ== X-Gm-Message-State: APjAAAVEI/8ofZkwGRw4SXo614Ylpob1YAr48D5S8RITkuyJq/ReatbA yRczNuxzAsZKV+lGDpV8GoRRiI6uHh8= X-Google-Smtp-Source: APXvYqwAwrw1Y0olNvR2AzMK71SHNqvgqU+bAqgdiLM4woow0wzHytmkzQW74PNi6EN5PkMlLEA5qw== X-Received: by 2002:a17:902:854c:: with SMTP id d12mr2660819plo.264.1575340201081; Mon, 02 Dec 2019 18:30:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions Date: Mon, 2 Dec 2019 18:29:14 -0800 Message-Id: <20191203022937.1474-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants. Keep the definitions short by referencing previous symbols. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6ba5126852..015301e93a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2871,14 +2871,14 @@ typedef enum ARMMMUIdx { ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, - ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, - ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, - ARMMMUIdx_MPrivNegPri =3D 3 | ARM_MMU_IDX_M, - ARMMMUIdx_MSUser =3D 4 | ARM_MMU_IDX_M, - ARMMMUIdx_MSPriv =3D 5 | ARM_MMU_IDX_M, - ARMMMUIdx_MSUserNegPri =3D 6 | ARM_MMU_IDX_M, - ARMMMUIdx_MSPrivNegPri =3D 7 | ARM_MMU_IDX_M, + ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, + ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, + ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, + ARMMMUIdx_MPrivNegPri =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, + ARMMMUIdx_MSUser =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575342036; cv=none; d=zohomail.com; s=zohoarc; b=YklHdejsvYNmAGZMexhHqEOtXdzo5SreWO7jB/zixPo1YRkb/Ze9OUHzYNAG59HjGKr8sLjmNB++lJxHxoWOSDiDNbKXVzEAeO9YijVwXU48ak4LueGuSCcUQlfkNnt0UXQxMNM2tBQ2nWoMFqffP9Wqb46CW3Rv4Rlw8JhG3Dg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575342036; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=p0K0S79M7ok7EaDRUT7kaMdT8Ynj+UHY35g+DPpaj9o=; b=hUK7w/RZTfE8oGgU3pclyI/6A4YNdgXWrcrlarBlHPs4eraDZ1o+pMzE5sGL3UarLZ8ycPISRkT7IRhwj43W/5QXXRdNAUs2wGoRnAYkb9smL3/+FvHpmt3q9TRJsNWjJjo7ppSfhBh7VxxIcbk1Q1xJL7uTqVBT1hcvZDgURSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575342036232286.30159124943043; Mon, 2 Dec 2019 19:00:36 -0800 (PST) Received: from localhost ([::1]:47660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyQU-0006vT-Ha for importer@patchew.org; Mon, 02 Dec 2019 22:00:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32807) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxI-0003MA-Te for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxB-0008T5-Ck for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:21 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:39166) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008Gk-Pu for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:17 -0500 Received: by mail-pf1-x444.google.com with SMTP id x28so978533pfo.6 for ; Mon, 02 Dec 2019 18:30:04 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p0K0S79M7ok7EaDRUT7kaMdT8Ynj+UHY35g+DPpaj9o=; b=IY26pGtpPRQ3B2i5aiupS5wjCtFbINIGza4TN1CrajyBvWxpVcrDdlwDjrTt1e8iKs 5ViScldSVIOV0rxTtr4uscPxgt1l2KbvWt4dc5Q8Dt/iJMRaudiiQuxM9p3DgoOdwO09 vKiK5GTuXMe3r/wIXemvTKzVWP1o6MsJKingR82Gz3nGZs/3ZyoMsn15ikuGgYeerimw 61o3jvrjsCxFToTA5WsiWvJwymQtoSGUIClUkqOb06HLyGLf63RCzrTtm2lLWXndqGJa 7NTsksu0QhZWuu5muQPTQPcQYqg4OsuqmJn4FssIf4dqUmTlf69mAD07o+r/E7YXnTq9 EWCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p0K0S79M7ok7EaDRUT7kaMdT8Ynj+UHY35g+DPpaj9o=; b=Ei2thOsYQW2u/QueSzrlS8G00VGeq+e3O6yWmOlWeIxK/t69ue1SjwE+JnYIg4ax+h yRG8rZbA93ySHKoMQ6fV0i8Un5TTlaZaqCiNt4f44I7WGVKHCeZvec9C9MLZCm9U7gxG pU1vZXkdzP9lG4tYlh989QVfU4DU9l5MgybiF3aybLWc4OzRIyT+DrX8KVvUeU66AqVt HrT5h6uW4NMyo4xD3tjW7v0//LamDkn8bXS8zi9i0L5rl/AgV5UPnlh+QDZfcxqdlcPI xVGnTMRowOMzCQJzr7Cc+n5j0lWnSBXCndGR9lW4lyNzISQyFGOM592lYyQshWY82SrH 8NqQ== X-Gm-Message-State: APjAAAVPRVw5dTIeBV9JVVs3BioKm7pHxBn/OPTPxPOFOJp5vc4JZChU 3StKAHMZcdDkIb1f0n38w3rOzVTefAg= X-Google-Smtp-Source: APXvYqyI9rpi2p8qwfTXPz4YHOIXc/iwLauw349zJwrFXnvzbGBE1vIxIlzkPumTlbscLVKojJpEdQ== X-Received: by 2002:aa7:952a:: with SMTP id c10mr2213539pfp.77.1575340202657; Mon, 02 Dec 2019 18:30:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/40] target/arm: Reorganize ARMMMUIdx Date: Mon, 2 Dec 2019 18:29:15 -0800 Message-Id: <20191203022937.1474-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prepare for, but do not yet implement, the EL2&0 regime. This involves adding the new MMUIdx enumerators and adjusting some of the MMUIdx related predicates to match. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 128 ++++++++++++++++++----------------------- target/arm/internals.h | 37 +++++++++++- target/arm/helper.c | 66 ++++++++++++++++++--- target/arm/translate.c | 1 - 5 files changed, 150 insertions(+), 84 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6e6948e960..18ac562346 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 9 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 015301e93a..bf8eb57e3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2778,7 +2778,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * + NonSecure EL1 & 0 stage 1 * + NonSecure EL1 & 0 stage 2 * + NonSecure EL2 - * + Secure EL1 & EL0 + * + NonSecure EL2 & 0 (ARMv8.1-VHE) + * + Secure EL0 + * + Secure EL1 * + Secure EL3 * If EL3 is 32-bit: * + NonSecure PL1 & 0 stage 1 @@ -2788,8 +2790,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) * * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: - * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because = they - * may differ in access permissions even if the VA->PA map is the same + * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_i= dxes, + * because they may differ in access permissions even if the VA->PA ma= p is + * the same * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage= 1+2 * translation, which means that we have one mmu_idx that deals with t= wo * concatenated translation regimes [this sort of combined s1+2 TLB is @@ -2801,19 +2804,23 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" * translation regimes, because they map reasonably well to each other * and they can't both be active at the same time. - * This gives us the following list of mmu_idx values: + * 5. we want to be able to use the TLB for accesses done as part of a + * stage1 page table walk, rather than having to walk the stage2 page + * table over and over. * - * NS EL0 (aka NS PL0) stage 1+2 - * NS EL1 (aka NS PL1) stage 1+2 + * This gives us the following list of cases: + * + * NS EL0 (aka NS PL0) EL1&0 stage 1+2 + * NS EL1 (aka NS PL1) EL1&0 stage 1+2 + * NS EL0 EL2&0 + * NS EL2 EL2&0 * NS EL2 (aka NS PL2) - * S EL3 (aka S PL1) * S EL0 (aka S PL0) * S EL1 (not used if EL3 is 32 bit) - * NS EL0+1 stage 2 + * S EL3 (aka S PL1) + * NS EL0&1 stage 2 * - * (The last of these is an mmu_idx because we want to be able to use the = TLB - * for the accesses done as part of a stage 1 page table walk, rather than - * having to walk the stage 2 page table over and over.) + * for a total of 9 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2851,26 +2858,47 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * For M profile we arrange them to have a bit for priv, a bit for negpri * and a bit for secure. */ -#define ARM_MMU_IDX_A 0x10 /* A profile */ -#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ -#define ARM_MMU_IDX_M 0x40 /* M profile */ +#define ARM_MMU_IDX_A 0x10 /* A profile */ +#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ +#define ARM_MMU_IDX_M 0x40 /* M profile */ =20 -/* meanings of the bits for M profile mmu idx values */ -#define ARM_MMU_IDX_M_PRIV 0x1 +/* Meanings of the bits for M profile mmu idx values */ +#define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 -#define ARM_MMU_IDX_M_S 0x4 +#define ARM_MMU_IDX_M_S 0x4 /* Secure */ =20 -#define ARM_MMU_IDX_TYPE_MASK (~0x7) -#define ARM_MMU_IDX_COREIDX_MASK 0x7 +#define ARM_MMU_IDX_TYPE_MASK \ + (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) +#define ARM_MMU_IDX_COREIDX_MASK 0xf =20 typedef enum ARMMMUIdx { + /* + * A-profile. + */ ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_EL20_0 =3D 1 | ARM_MMU_IDX_A, + + ARMMMUIdx_EL10_1 =3D 2 | ARM_MMU_IDX_A, + + ARMMMUIdx_E2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_EL20_2 =3D 4 | ARM_MMU_IDX_A, + + ARMMMUIdx_SE0 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, + + ARMMMUIdx_Stage2 =3D 8 | ARM_MMU_IDX_A, + + /* + * These are not allocated TLBs and are used only for AT system + * instructions or for the first stage of an S12 page table walk. + */ + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, + + /* + * M-profile. + */ ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, @@ -2879,11 +2907,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, - /* Indexes below here don't have TLBs and are used only for AT system - * instructions or for the first stage of an S12 page table walk. - */ - ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* @@ -2895,8 +2918,10 @@ typedef enum ARMMMUIdx { =20 typedef enum ARMMMUIdxBit { TO_CORE_BIT(EL10_0), + TO_CORE_BIT(EL20_0), TO_CORE_BIT(EL10_1), TO_CORE_BIT(E2), + TO_CORE_BIT(EL20_2), TO_CORE_BIT(SE0), TO_CORE_BIT(SE1), TO_CORE_BIT(SE3), @@ -2916,49 +2941,6 @@ typedef enum ARMMMUIdxBit { =20 #define MMU_USER_IDX 0 =20 -static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) -{ - return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; -} - -static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) -{ - if (arm_feature(env, ARM_FEATURE_M)) { - return mmu_idx | ARM_MMU_IDX_M; - } else { - return mmu_idx | ARM_MMU_IDX_A; - } -} - -/* Return the exception level we're running at if this is our mmu_idx */ -static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { - case ARM_MMU_IDX_A: - return mmu_idx & 3; - case ARM_MMU_IDX_M: - return mmu_idx & ARM_MMU_IDX_M_PRIV; - default: - g_assert_not_reached(); - } -} - -/* - * Return the MMU index for a v7M CPU with all relevant information - * manually specified. - */ -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri); - -/* Return the MMU index for a v7M CPU in the specified security and - * privilege state. - */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv); - -/* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); - /** * cpu_mmu_index: * @env: The cpu environment diff --git a/target/arm/internals.h b/target/arm/internals.h index aee54dc105..d73615064c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -769,6 +769,39 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) +{ + return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; +} + +static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return mmu_idx | ARM_MMU_IDX_M; + } else { + return mmu_idx | ARM_MMU_IDX_A; + } +} + +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); + +/* + * Return the MMU index for a v7M CPU with all relevant information + * manually specified. + */ +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri); + +/* + * Return the MMU index for a v7M CPU in the specified security and + * privilege state. + */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); + /* Return true if the stage 1 translation regime is using LPAE format page * tables */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); @@ -810,6 +843,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_E2: @@ -819,9 +854,9 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: return false; - case ARMMMUIdx_SE3: case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: + case ARMMMUIdx_SE3: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/helper.c b/target/arm/helper.c index ec5c7fa325..f86285ffbe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8561,9 +8561,11 @@ void arm_cpu_do_interrupt(CPUState *cs) #endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -8574,6 +8576,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_SE1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8675,10 +8679,14 @@ static inline TCR *regime_tcr(CPUARMState *env, ARM= MMUIdx mmu_idx) */ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { - mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_EL10_0); + switch (mmu_idx) { + case ARMMMUIdx_EL10_0: + return ARMMMUIdx_Stage1_E0; + case ARMMMUIdx_EL10_1: + return ARMMMUIdx_Stage1_E1; + default: + return mmu_idx; } - return mmu_idx; } =20 /* Return true if the translation regime is using LPAE format page tables = */ @@ -8711,6 +8719,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_SE0: + case ARMMMUIdx_EL20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11136,6 +11145,31 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 +/* Return the exception level we're running at if this is our mmu_idx */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) +{ + if (mmu_idx & ARM_MMU_IDX_M) { + return mmu_idx & ARM_MMU_IDX_M_PRIV; + } + + switch (mmu_idx) { + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_SE0: + return 0; + case ARMMMUIdx_EL10_1: + case ARMMMUIdx_SE1: + return 1; + case ARMMMUIdx_E2: + case ARMMMUIdx_EL20_2: + return 2; + case ARMMMUIdx_SE3: + return 3; + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_TCG ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { @@ -11149,10 +11183,26 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 - if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_SE0 + el; - } else { - return ARMMMUIdx_EL10_0 + el; + switch (el) { + case 0: + /* TODO: ARMv8.1-VHE */ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdx_SE0; + } + return ARMMMUIdx_EL10_0; + case 1: + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdx_SE1; + } + return ARMMMUIdx_EL10_1; + case 2: + /* TODO: ARMv8.1-VHE */ + /* TODO: ARMv8.4-SecEL2 */ + return ARMMMUIdx_E2; + case 3: + return ARMMMUIdx_SE3; + default: + g_assert_not_reached(); } } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index cd757165e1..b7f726e733 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -172,7 +172,6 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPrivNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); - case ARMMMUIdx_Stage2: default: g_assert_not_reached(); } --=20 2.17.1 From nobody Wed Nov 12 23:10:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341473; cv=none; d=zohomail.com; s=zohoarc; b=BUK3wUmkkPEJ+RmyvPGij3gwlAdD7TbQFEBVD9ZgtkCD1mf9kgQ0C3R/mM1NflougDpVSgECiBMRg3AL7TN/mx1OmyRSxErjlvrRfgHwQZ05s5tj9bsu3WNspcIhMd6WgO5d5pO8bnziWlaH8etDYm7dOjUYNAcCOIJC6O/5h8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341473; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Xos4Pslsfo4lMRc6yGUlLi8dcXsFQtvPjw86xkjAaB4=; b=Q4MyJw/MPPJJLnumBttiKd6PWw2/qCyRSnsED03QpmI3408zBN8QUDgCCBEMnT63RF 6LvGpvw96bFsVuVQubRf7yPryZZj7ZgJRgTsGNuJRca6EdZr/aI5cMg3S6DE0y20avs+ Pyi8q//BDqYpsdZC89wliKYuN+9fWwn1iSPbFEpKwZOVsDG30KFKtKtg3MTfyORK2q1N gfVPqdYGopMTzm1kFydqesuXBAEtymkeGMjnx1+cafAYPiEoVwAFm9udh2k34/K5NNOP v2DwUpGt6e/Lu43l3HSYBYQUdYXuO7WWT6IVjblsmOLWkSvqrc5UzSGyveU32PkeS4th /DFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xos4Pslsfo4lMRc6yGUlLi8dcXsFQtvPjw86xkjAaB4=; b=NMyUwmW0vfDpo8RTgfCm/oB6YD8DtH5SqWtzEB8DELMbeqqfKAOrO+kK+6OwcwWnsf yBhY8rWpNxbMULpFa6aWPqSSxnScdum5ECNSTmoh27ihEZc/ltSwIvixZRcAB6QUsj0y RmXo1VZqWApR8oBeA+/cmKA/uBk79c66NTXK0LqUzLvw5jf7k9aIYMgs6ehzNIwI7XvR vX3vdOBOi/pem3DNHYt8sT2w/kD/hTkJpGNSHed/DK//ks2EhDD+mU70w2b1uHr+xfte iFuh6t9XlreOiX5iS4JVGqYgPk1uvy+1JvjTqss9RTfflCF3k4VrWrrAgL0iNutMP/z0 iVmg== X-Gm-Message-State: APjAAAVWtDqwa6vU0TW0r9muo55udmG0U4255NiSUnp717FucgAqXDNQ GN6XWTuzT/ghmdBCfCeq6OMXoHYthAg= X-Google-Smtp-Source: APXvYqwGopLQkhOth2E4ve2RCS7+E9qTQ9Px53188YN/3AAd5eh+lTg8LLFspAIyr9gXG22QXiwN7Q== X-Received: by 2002:a65:590f:: with SMTP id f15mr2729309pgu.381.1575340204022; Mon, 02 Dec 2019 18:30:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/40] target/arm: Add regime_has_2_ranges Date: Mon, 2 Dec 2019 18:29:16 -0800 Message-Id: <20191203022937.1474-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/internals.h | 16 ++++++++++++++++ target/arm/helper.c | 23 ++++++----------------- target/arm/translate-a64.c | 3 +-- 3 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d73615064c..1ca9a7cc78 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -837,6 +837,22 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } =20 +/* Return true if this address translation regime has two ranges. */ +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: + return true; + default: + return false; + } +} + /* Return true if this address translation regime is secure */ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/helper.c b/target/arm/helper.c index f86285ffbe..27adf24fa6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8885,15 +8885,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mm= u_idx, bool is_aa64, } =20 if (is_aa64) { - switch (regime_el(env, mmu_idx)) { - case 1: - if (!is_user) { - xn =3D pxn || (user_rw & PAGE_WRITE); - } - break; - case 2: - case 3: - break; + if (regime_has_2_ranges(mmu_idx) && !is_user) { + xn =3D pxn || (user_rw & PAGE_WRITE); } } else if (arm_feature(env, ARM_FEATURE_V7)) { switch (regime_el(env, mmu_idx)) { @@ -9427,7 +9420,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, ARMMMUIdx mmu_idx) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el =3D regime_el(env, mmu_idx); bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; =20 @@ -9437,7 +9429,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, */ select =3D extract64(va, 55, 1); =20 - if (el > 1) { + if (!regime_has_2_ranges(mmu_idx)) { tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); @@ -9593,10 +9585,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, param =3D aa64_va_parameters(env, address, mmu_idx, access_type !=3D MMU_INST_FETCH); level =3D 0; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark = it - * invalid. - */ - ttbr1_valid =3D (el < 2); + ttbr1_valid =3D regime_has_2_ranges(mmu_idx); addrsize =3D 64 - 8 * param.tbi; inputsize =3D 64 - param.tsz; } else { @@ -11306,8 +11295,8 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, =20 flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { + /* Get control bits for tagged addresses. */ + if (regime_has_2_ranges(mmu_idx)) { ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); tbid =3D (p1.tbi << 1) | p0.tbi; tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 885c99f0c9..d0b65c49e2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i= 64 dst, if (tbi =3D=3D 0) { /* Load unmodified address */ tcg_gen_mov_i64(dst, src); - } else if (s->current_el >=3D 2) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ + } else if (!regime_has_2_ranges(s->mmu_idx)) { /* Force tag byte to all zero */ tcg_gen_extract_i64(dst, src, 0, 56); } else { --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GDr0htatS+6R/DlKCxhohN0bwVQjve2P3dt6OUDDnew=; b=xXgQ6/qXBmXh0e7CTiB3ETD86w6CeII2P9TYDc63utlIjSzZ6sasDKHiQFFzROaNB1 JkgjhWbHsgS/w3jCa1DvrF0a/TOkKeW9Qv+k4x/W4ly3oos9A77pbXDxiGkFRQlCXpYd 7G5okRO0M24CcrXQe4DmwgSQvFQRoKdy8+F9pB0D38N3EnRuN7eGXk+pKohwd7OwpemD Dg3qgo2KWxy7bR1XukY0JckWVpUp2JilYnkwkqd8EHd5otnbwenfXd5mqFlSx7OQgmfn 200ly/oXvGJgDbUkrIshqHP7FpOR/eKVuX8S2ILCGnEitmX4z7MMFHYzq9GexjbHqx8s VJTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GDr0htatS+6R/DlKCxhohN0bwVQjve2P3dt6OUDDnew=; b=VmMd3KMGmzSgJ3jXKotBwRj3u/0Z0QABajz9K15LLJcj2cUf6H9LRqnIIxjXmqqF58 HeURn6XseMt/DXbt+vfKshZ6o0uiAhrztl7YNmsTrMR/z9nRmHwZTpc6HyBvjpIDtrov dh4SrexdH/Q44gvIWVF358WgFGtgqhzSD00TvWtaWboEfzztwm5p81vj0JdWG8jogUUP 4pOVuf4rFbtT+1I1g1bt0adN8ayj76LWfZNL+jRlFjhLlqLWrVxxbsAlczl8jo0FxSqL NC9gCpRClokCYm5ZBybMjFk9kAXCtZlWNSBuaNFeplsb+RCAFYDx16qHF2JlyQnMheKS nAVg== X-Gm-Message-State: APjAAAWnHdO6iLzxcorZX8gMSIE2FpB2nxR8/NeGa1R7ZiDtm4j1naNz bWsKpiB54MD/T6ee9QqH8MFKpVNig70= X-Google-Smtp-Source: APXvYqyzhDrlLS21TTEEdHFXT/H6A+YjV1HVXuc+4ofrVctgXS6Sw+aR2MLexiLaxcxYw6ayP4IwGg== X-Received: by 2002:a62:3141:: with SMTP id x62mr2359713pfx.214.1575340205188; Mon, 02 Dec 2019 18:30:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/40] target/arm: Update arm_mmu_idx for VHE Date: Mon, 2 Dec 2019 18:29:17 -0800 Message-Id: <20191203022937.1474-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Return the indexes for the EL2&0 regime when the appropriate bits are set within HCR_EL2. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 27adf24fa6..c6b4c0a25f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11172,12 +11172,16 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 + /* See ARM pseudo-function ELIsInHost. */ switch (el) { case 0: - /* TODO: ARMv8.1-VHE */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdx_SE0; } + if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HC= R_TGE) + && arm_el_is_aa64(env, 2)) { + return ARMMMUIdx_EL20_0; + } return ARMMMUIdx_EL10_0; case 1: if (arm_is_secure_below_el3(env)) { @@ -11185,8 +11189,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } return ARMMMUIdx_EL10_1; case 2: - /* TODO: ARMv8.1-VHE */ /* TODO: ARMv8.4-SecEL2 */ + /* Note that TGE does not apply at EL2. */ + if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + return ARMMMUIdx_EL20_2; + } return ARMMMUIdx_E2; case 3: return ARMMMUIdx_SE3; --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341215; cv=none; d=zohomail.com; s=zohoarc; b=l7YVtCP8LfJJikkDsbUMpiAfrdfzLfGMHUc40u/aM8tnG3jRBiccZp1TgasEr/ZbWbo6TFPd+WrdqcebA/sboN/sxUgUrpKK+hLKJ3b37gMGcbL3BMTVJsA9XuHW60P4h+GtgNnuN6W9A6/fSatz0hXe5nANYDSM25aaYls37jk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341215; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AIS/DQiMYw3p+zAAk8FWlKdfeq2a/nHlVUG1M8AUF24=; b=ir1VSEtMbhRMTvrlrsFih/Lchg0mhIn04sUdb1Ch11Q6IC7rlKd7UHqJfM0G+jBl3s58lV3FJtpkSDK80zoKk2igouhLMMQmnFj0zfuFTcLLSOQkJKObQ161VE6DUHBV4GIcI0wFbpHyM9/5ArRh9EwaigMfzMp7Le/2ninAkIc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157534121528229.067701214749945; Mon, 2 Dec 2019 18:46:55 -0800 (PST) Received: from localhost ([::1]:47388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyDF-0005TF-O8 for importer@patchew.org; Mon, 02 Dec 2019 21:46:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60717) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxC-0003Is-Tz for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxA-0008Ql-Se for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:18 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:36819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008Hw-HD for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:16 -0500 Received: by mail-pg1-x542.google.com with SMTP id k13so875864pgh.3 for ; Mon, 02 Dec 2019 18:30:07 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AIS/DQiMYw3p+zAAk8FWlKdfeq2a/nHlVUG1M8AUF24=; b=n8CKV3jQVf6vF2bbZS7GnPdy0QfEO83Z2HdqtkOrzZoDdCe9HqWG1zRJfp3D4mixJ9 kvkVxWQTOXi5nVCesT2AzZlUXZPVw23gDmXurc4jehYbW4ERkgN9DuSM9SUbz7M8kk8O hcafwkZMiQH7epvgW3KzM3elPJqA52v2PZffxQhukP/5oJbdgj3qNB7N40ndGF/c+kV6 MRAH5a21RRKcELDpolvV64Gjn+nQmFpkKucaZJysA9FgXwM34eYXKQmuNN7aslfzcL7m SJQe/wxWvZA+8dc1d+famOjE9NjFxJTo8sScxwugWTl5SJquFA3niVl2iIDPMUhPXYl1 SdCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AIS/DQiMYw3p+zAAk8FWlKdfeq2a/nHlVUG1M8AUF24=; b=uEHzVvpxBRAyHhSe9PLLnh2XW1U09ncWH1g9BRYYSsd3d1kMKIIjQAWgfJdJrbpGAT RAUZMJvc4LGOBRIof5KuS+GLKcQfOtB+XJEno1uHwru7BVV4taFvIYSKq6XZTm0sJj+Y nqTGtK1NTOSRGdZ6Hh89sdiQBKF6SxvtFVDu1ha49X+Hc+VGy8ZCE95cEgiTAcrAELVx W+Hw/wn5Ve1Y+feqJtOqJiBsWnrm539i+WMamfA9q96x/oLEqc1AAp7R00xkBT248KSg /z9MrMfghazeyRiPzIVOiuBazA7ftj3bez84ZJj+bKgZinNxlCOPrUADpgkt5iAoSW6E 5f/Q== X-Gm-Message-State: APjAAAX11+rvA/ImUl9hoNbdo+kN3rzp2wobWQdV4AmvLPpbFxyyxlSP 2Fkdyt80+Ti7UuEx4AHW6dBZK1AiD6w= X-Google-Smtp-Source: APXvYqwn/SJcN3t5svXfg0GPSAVBBtn8XrHwqjRD4U8m5ozXUIbO+T2h9VL0dv+UXhCTTSRn+pfBSA== X-Received: by 2002:a63:f658:: with SMTP id u24mr2704651pgj.129.1575340206684; Mon, 02 Dec 2019 18:30:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 21/40] target/arm: Update arm_sctlr for VHE Date: Mon, 2 Dec 2019 18:29:18 -0800 Message-Id: <20191203022937.1474-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use the correct sctlr for EL2&0 regime. Due to header ordering, and where arm_mmu_idx_el is declared, we need to move the function out of line. Use the function in many more places in order to select the correct control. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 +--------- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 20 +++++++++++++++----- target/arm/pauth_helper.c | 9 +-------- 4 files changed, 18 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bf8eb57e3a..8aa625734f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3100,15 +3100,7 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 -static inline uint64_t arm_sctlr(CPUARMState *env, int el) -{ - if (el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - return env->cp15.sctlr_el[1]; - } else { - return env->cp15.sctlr_el[el]; - } -} +uint64_t arm_sctlr(CPUARMState *env, int el); =20 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, bool sctlr_b) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index b4cd680fc4..abf15cdd3f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { raise_exception_ra(env, EXCP_UDEF, syn_aa64_sysregtrap(0, extract32(op, 0, 3), extract32(op, 3, 3), 4, diff --git a/target/arm/helper.c b/target/arm/helper.c index c6b4c0a25f..4f5e0b656c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3863,7 +3863,7 @@ static void aa64_fpsr_write(CPUARMState *env, const A= RMCPRegInfo *ri, static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -3882,7 +3882,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless * SCTLR_EL1.UCI is set. */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= I)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -8592,14 +8592,24 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUI= dx mmu_idx) } } =20 -#ifndef CONFIG_USER_ONLY +uint64_t arm_sctlr(CPUARMState *env, int el) +{ + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + if (el =3D=3D 0) { + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); + el =3D (mmu_idx =3D=3D ARMMMUIdx_EL20_0 ? 2 : 1); + } + return env->cp15.sctlr_el[el]; +} =20 /* Return the SCTLR value which controls this address translation regime */ -static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } =20 +#ifndef CONFIG_USER_ONLY + /* Return true if the specified stage of address translation is disabled */ static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -11332,7 +11342,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 - sctlr =3D arm_sctlr(env, el); + sctlr =3D regime_sctlr(env, stage1); =20 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index d3194f2043..42c9141bb7 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el,= uintptr_t ra) =20 static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) { - uint32_t sctlr; - if (el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[el]; - } - return (sctlr & bit) !=3D 0; + return (arm_sctlr(env, el) & bit) !=3D 0; } =20 uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341331; cv=none; d=zohomail.com; s=zohoarc; b=JHBQD6T+IBB9oLBDwF4hyujZSEGBJAng99O8x/PP1CcR9FhwBQOIYqdRQcSa3zAw7yo6Ghz5KnsSiDlKMgdoQ3DJXRFnGDMwaoNvI0UjlFQQrfpIc87R4XrkYkTMqvUUGKhDg7LZo0kKSaB6fD6WRxkbQ2M4JdYNDfrn/dyHmeI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341331; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Yw6liUOnTrdCiX1bj2V8EHNGM2nemLD+p3/vAl9e62o=; b=fU9CT5qX1WZIkQt0pC2CFcQSbGfWC+pH6UB5g+3EE+e75tcycJc6Ke/Hb9zsGdn6P9QEl+Olx1PmhasXiy3aPo/v5Hlz667mmpyzjRm5cckHxFoX7q8zLTBLItMV6nm8dSOmePUHW0+cFte2OL1wnyITanCeTFq4T50FbzIrpto= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341331734101.07626832568167; Mon, 2 Dec 2019 18:48:51 -0800 (PST) Received: from localhost ([::1]:47432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyF8-00081T-9R for importer@patchew.org; Mon, 02 Dec 2019 21:48:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32781) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxI-0003M6-SD for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxB-0008SV-8G for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:21 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:46435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008I9-Np for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:16 -0500 Received: by mail-pg1-x544.google.com with SMTP id z124so851076pgb.13 for ; Mon, 02 Dec 2019 18:30:09 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Yw6liUOnTrdCiX1bj2V8EHNGM2nemLD+p3/vAl9e62o=; b=PQrgbuw6OQKZbq9XNotG18JWkKYmvYeFzME4EbDrrbPaNcX3DEbB1R+vBZJ9YF0Yko 29+xR7O8uRjBzhNMjwWd3vCnkOLpiggI7ZIAO/UO0RSWwW9c9QTr0+qSFbqREEampCjL Ks1AoQ6zqmOWsEQK90/MljU6c+mPAHYTogYBOxBHQ6GkpUj53kguQ414KPzN8N9luL7x jXATIfwqwECM1OsqqfL9XnTbWJktJ6AOPGJzh7D4EbzKqVFZsiiPkORAa+QDF6RObsbQ Z2S9nWnpbefgoZFGw/WhLNKykomLJ/eE6L3VFz7aS+VX+cmnsM1TmCWnkb1W9/Y2+xbS IN+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Yw6liUOnTrdCiX1bj2V8EHNGM2nemLD+p3/vAl9e62o=; b=fXVcVPyuCOL7B6Bm+70oc8IMewEv292vFZy9TfPo/Th1brRzozehUerxS+Km7mZEor iAfWonK8/Z9ed3elzoo8jaYQsXYwBrv4JXXEbYGSytt1uzitM/XLQmZuZmGwtOlH0rex IbfuemT9rkaqDPTAFPEOA6Xe9q943zjJrccxVmkhT5DipPz4nVhHAr6PqA0kJRkXeUmH N8E2Mjgrs7UQI08PXsBhoHm9yOHCbbwPcGPzYuFt+b6h6fWA4EXxQaNiPHpsxf4S2bMS u8PGeEPsnGIGA0pjyi7xggzyz39g+ETk/2aF0NT0lppq4cs6qtmO/t11AmUbnPK1mz6Q n1Jw== X-Gm-Message-State: APjAAAV9DEPi2GwlqF7e2XsJhlO/+mAZUvUiqb6G7nM4eXqPEWKcV9Su QN0m0Hp1357pgzZHhWxzx+rJAjKTy0o= X-Google-Smtp-Source: APXvYqxYc1QvRA+b1Ge6RQYbSQCW7JWzGjz4+Jzwy1VlKXBuqeawnOkwJGzuY7++qAVidz97Qv6i+A== X-Received: by 2002:a63:93:: with SMTP id 141mr2758722pga.411.1575340207863; Mon, 02 Dec 2019 18:30:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2 Date: Mon, 2 Dec 2019 18:29:19 -0800 Message-Id: <20191203022937.1474-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The comment that we don't support EL2 is somewhat out of date. Update to include checks against HCR_EL2.TDZ. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f5e0b656c..ffa82b5509 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4109,11 +4109,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *= env, const ARMCPRegInfo *ri, static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { - /* We don't implement EL2, so the only control on DC ZVA is the - * bit in the SCTLR which can prohibit access for EL0. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZ= E)) { - return CP_ACCESS_TRAP; + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } } return CP_ACCESS_OK; } --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341328; cv=none; d=zohomail.com; s=zohoarc; b=O3UZaxsosEMHav8aauAE9UShmnAxUYj0bpU/DU1vIttnYy7jz7PLUfxaUfJ4rEjnbtII8SnzjcvsC/oK76FNHypzubYe7wMQu6aT7F5r0ixr9Eo9hY/ALk4dE1jKjXAv7rZi9ATXRwGRdI6OPDtAuvJbJzxfO9Z8lY4XgzkTJf8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341328; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=bOBBih3JRg5ecnanCNy6UVzBnae0IWceZ3dWmja0LB0=; b=Yzf0+c4uIUi8CD8cdEC7MdirWHAHnR/NYMn6SybeqLQFgTr9dMxOEV58mqiIbznT7y5HWpizVDKNTg1dS395cgXgDGFu29E2n16KP6MjR3QaejT70BWegXclv+AatHDSdVbCEUWHqPaN85NuNcFTbRIoe/PMdGPtnUZ1pMuUCw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341328926878.1433450855075; Mon, 2 Dec 2019 18:48:48 -0800 (PST) Received: from localhost ([::1]:47428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyF5-0007wd-6f for importer@patchew.org; Mon, 02 Dec 2019 21:48:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60920) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxF-0003Ke-OW for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxB-0008St-Au for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:19 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:38834) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008JL-Sq for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:17 -0500 Received: by mail-pj1-x1041.google.com with SMTP id l4so820902pjt.5 for ; Mon, 02 Dec 2019 18:30:10 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bOBBih3JRg5ecnanCNy6UVzBnae0IWceZ3dWmja0LB0=; b=edKy5gsqSGsIb/Aqrmu0qeeKI61BFr9bt/o0qqxYEGF+lQDctNPGEMbqsFq0/bmaO6 MZwR1OemnaTSNANgBoK8dgxPg3WQocTHMMN9r8mMURq4Qv4nrA9HDKPM0ctAOWOG55w9 XcocPm3qRE1j1j3sNN+yyTc97TKQ4+MuPJDdPuIacCbDL6roV/cyNdFH7GbIow3L0M3g C/UVgElaX9sTrAA1fzuBPhM47s4MoEStcVIj6hsVfRz+qE38ztDRG3sx5Xh8C1CMNc6r MlPsgTfBZXQik8+HyG6niii47+zRiPE++DHnKoPz8nguZCGyXeAmX2PcS/YT0mN0fAlP 2Cpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bOBBih3JRg5ecnanCNy6UVzBnae0IWceZ3dWmja0LB0=; b=SUo7kjESgMLE+10BqS8enmdr3bhnupWRcaY+9vHYuthzQ89qNWTLwrGdu0MdRE6yls C2OPJaGQkM6XsnAwEUGusF3cvhO3xAYGBgkiszU88AlOwbe54ySYf009rXVnGj3pjqVs IxGJoHC6a2SK2iEbQUCHbclt7t4De8kEkhRsdkDzsiwy7oDrwMs3unuzO3Ga0JGxH4bB EAh6hzGt4HENtG7BK20rw5g6om4hZaetZ9zFxNiNE+v0zs51RxuAwtwQKlrvTEjUTr8D 90FsJDNBrUgF8gLqSoPIoR89fTuPPGRhzq0vNwFn18KgWEH+G2St3JvrXPQCJJChvOx3 ll+w== X-Gm-Message-State: APjAAAU1IAa0HXx1jNJmpxM/lJbW4NHc/NGGokSryey8KNjsiN3Zi8wp VRt5WbEf0ZhV7eSdEA5Vchi5PlJernw= X-Google-Smtp-Source: APXvYqw4vPzxpEryNUONVsjLoHitknAN7OaJAi57P4XVvRvgjMwUbcladx0doFl1XAU92j4188ioAA== X-Received: by 2002:a17:902:b188:: with SMTP id s8mr2570088plr.206.1575340209136; Mon, 02 Dec 2019 18:30:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 23/40] target/arm: Update ctr_el0_access for EL2 Date: Mon, 2 Dec 2019 18:29:20 -0800 Message-Id: <20191203022937.1474-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update to include checks against HCR_EL2.TID2. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ffa82b5509..9ad5015d5c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5212,11 +5212,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { - /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, - * but the AArch32 CTR has its own reginfo struct) - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { - return CP_ACCESS_TRAP; + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } } return CP_ACCESS_OK; } --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341381; cv=none; d=zohomail.com; s=zohoarc; b=RubK3uNCM8nvU723lIjT6s+tu63cYNk58E8e3FRsq7Q5OcpZ4cchq7K4dFgqnOX3xqUqXbaetd5orNoWNmGsN2wXGZAnPjL1/laVVBhGsy5hAnoLzVATt1HCs6dpbWoZKYpY5Am/hv28riyfgo/+SCbEQ49St8ePBiMWrgI1I24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341381; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E8yk4OTb4DM68OtMu/yGYISogJYWI7EJZxpxxXSYsqE=; b=kfH4kPvvoVpk91tNrVsuGWiJvArCl+V9cQYADn2ZjizzLbwKkSIX7oO3gq9ogk7sHqXYdQD/29ehCOlhkDiYkf1mhZAKrlo+HgCg7Sy39sHZ253uiD6aAF8j41cpRu21x8lG6iqshbCl4OK52fXTjgpLiICquYHjZ7ueqlxN1OM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157534138194794.8882704755315; Mon, 2 Dec 2019 18:49:41 -0800 (PST) Received: from localhost ([::1]:47438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyFw-0000qG-BK for importer@patchew.org; Mon, 02 Dec 2019 21:49:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32782) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxI-0003M7-SS for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxB-0008S0-58 for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:21 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44823) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008MG-LN for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:16 -0500 Received: by mail-pg1-x542.google.com with SMTP id x7so856061pgl.11 for ; Mon, 02 Dec 2019 18:30:11 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E8yk4OTb4DM68OtMu/yGYISogJYWI7EJZxpxxXSYsqE=; b=sE+KrcDlU+6nT18OIC8EFUiq/+P7tYlBURoB6x/qOKo+PsbTTV2mVzfDAJvyfI8Dgx DVeQztNveHI2/tqoS9ln9OMmnn3vd/5C6sjTuwnJpavys0kzqirKzEROYmqWkEiMrxsj 2S+VoFh5bp0xiIcRtK5mjbBpQUb953BczmSe+zXx7m2zRed1NYL8JWVsmsWfPvWH7fyG VswyB8X31AqVaDoO2R20QzAhmV0p/ddllbv5LIuZY2s3opzAA8+OMKdgX61Jn7Px89hz uCmk4x1X8uloZzNKuSyTNfIrpqFKh+pQaVIC1glY2SVTBkMPVXUkfIbkWEyfj28EW1Gq dSzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E8yk4OTb4DM68OtMu/yGYISogJYWI7EJZxpxxXSYsqE=; b=dOnE15Zr3ogT2ArRNanixsq6iMbLtP3UfNlAwkd9YwMCJNxq3Up1+W2+CaLo3ngwaI bwup1QcuUjlwzuusyx024Pq9LeRITfJW1fIrbW27zh75u9x4tVjIGNGeqGsI7qBoUBzU 9jZgVmFt0oJJqFBwI35lkT2LA6JvlnMQLXAf55QuccCpHdSlxsshZjXH267gYo/l2j7B cmOfi5CZs+5Och0MMXYt246MW/delVmmx1x6l5MElKut+4Q2rpY+NKLFoJLPuaRagfet a8Rzzdz8RkQx0TbcpXnzNp7KRiqtsNhP+y6e/gegXLXKtmnY9Y1NAHV9mzf1xRJ3CnIJ EXWw== X-Gm-Message-State: APjAAAWGxz4N3hNAywXdxX6X6xyWNe/SfrEpxsjHLBW1jZAn+0yMuqO6 E/foAIxhhmZJA0tiTqinIwHjYVlOVOw= X-Google-Smtp-Source: APXvYqweSP5BWNjqvubWqdFgg373QPHkltVWC/m/Fmr0n/FR9LEntZIGt7LDSjtsugOINVnTNEhzsQ== X-Received: by 2002:a63:36c4:: with SMTP id d187mr2859006pga.108.1575340210716; Mon, 02 Dec 2019 18:30:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 24/40] target/arm: Add the hypervisor virtual counter Date: Mon, 2 Dec 2019 18:29:21 -0800 Message-Id: <20191203022937.1474-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 11 +++++---- target/arm/cpu.c | 2 ++ target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 7f5b244bde..3a9d31ea9d 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -76,6 +76,7 @@ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); =20 #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8aa625734f..4bd1bf915c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -144,11 +144,12 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define NUM_GTIMERS 4 +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 =20 typedef struct { uint64_t raw_tcr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339b..81c33221f7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1259,6 +1259,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) arm_gt_htimer_cb, cpu); cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCA= LE, arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER= _SCALE, + arm_gt_hvtimer_cb, cpu); #endif =20 cpu_exec_realizefn(cs, &local_err); diff --git a/target/arm/helper.c b/target/arm/helper.c index 9ad5015d5c..a4a7f82661 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2516,6 +2516,7 @@ static uint64_t gt_tval_read(CPUARMState *env, const = ARMCPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2532,6 +2533,7 @@ static void gt_tval_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2687,6 +2689,34 @@ static void gt_sec_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } =20 +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu =3D opaque; @@ -2715,6 +2745,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } =20 +void arm_gt_hvtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYPVIRT); +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { /* Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. @@ -6989,6 +7026,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 2, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hv_timer_reset, + .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write }, + { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 1, + .access =3D PL2_RW, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), + .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, +#endif REGINFO_SENTINEL }; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=foIQHgib5OJD+DVqFbHLebtrbVaKenjz5fFYNBd8YXw=; b=PWviWWm9BJulpYkjnp1LHoe0Zud2ZXYzUSId23LGfqJDKRQWf3NvXfbimwqjUlcxSf vWp4vKvajwyQ1m5WZotOINZBjlkDt7bBlhzDw/XG8e/VwipuGa/xul4XDSnG/Pz7t4yp COPRdx9RLwXKzV41a5yQO45g99IIMOlUYQiwbsxUN8vp2UCbTwA67krcitxr75MVzdLA TLCQvCZCRd/IIeLNAvFzgMUcZXIO01vHE3JDXzgeoQWSPsqEfxxRNYiyE5pe3Hmko1lh 6f8zKzZrnef+Ao+H4LTdaAFiomMYlbHG05E/Oo6FQfS7ltCP3hOkZYWiokwJetOGjFU7 PSAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=foIQHgib5OJD+DVqFbHLebtrbVaKenjz5fFYNBd8YXw=; b=W7srrR3aCJNvWxoE5KyQtvznP4kZTx8Dglc39d1drsD/yK+8rA1Gx338hpJ2TdKC5M msd0fABjQEa0r53lBtug7wa4HqtFcrOJT2wE4bx3Iy52+eR63e+gXhslYEHKuUikv5ee xrEn3N8zTm+i92wpJxm3PhGdJBtBg/j9ET1CMRygvJeDk4nqTrsO6j/Pe0sHYUBgDv5V zhb2+sALJkMPMLeTBWunsB5elhhJuPghsAMXfJWtx++D6LN2Ba46Qo7bjk92BwcWtV3a liJCfu4TgCokvhaqkW71SoIOKpdZW491ZTACmMv+ndxET8qnCGPuMcEiF4Xls4tp/BfD jcCA== X-Gm-Message-State: APjAAAW3Bj4jBryEGSAoyPH/Td3pB+9apzCGPUWFxWbyPF0rhmS2iC8k Ha0Ea2I+Kge0F0GHVRUZFqHbS36/YJQ= X-Google-Smtp-Source: APXvYqwASr95QiG2wt5dhr6jKrC9ecTNFg88ozaCXty3QZJbUQgqES13S2c26i9aabVvPXPYhB33ZQ== X-Received: by 2002:a17:90a:ff12:: with SMTP id ce18mr85891pjb.117.1575340211814; Mon, 02 Dec 2019 18:30:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 25/40] target/arm: Update timer access for VHE Date: Mon, 2 Dec 2019 18:29:22 -0800 Message-Id: <20191203022937.1474-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 81 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a4a7f82661..023b8963cf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2287,10 +2287,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState = *env, const ARMCPRegInfo *ri, * Writable only at the highest implemented exception level. */ int el =3D arm_current_el(env); + uint64_t hcr; + uint32_t cntkctl; =20 switch (el) { case 0: - if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + cntkctl =3D env->cp15.cnthctl_el2; + } else { + cntkctl =3D env->cp15.c14_cntkctl; + } + if (!extract32(cntkctl, 0, 2)) { return CP_ACCESS_TRAP; } break; @@ -2318,17 +2326,47 @@ static CPAccessResult gt_counter_access(CPUARMState= *env, int timeridx, { unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); =20 - /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ - if (cur_el =3D=3D 0 && - !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { - return CP_ACCESS_TRAP; - } + switch (cur_el) { + case 0: + /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]CTEN= . */ + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return (extract32(env->cp15.cnthctl_el2, timeridx, 1) + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); + } =20 - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && - !extract32(env->cp15.cnthctl_el2, 0, 1)) { - return CP_ACCESS_TRAP_EL2; + /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ + if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { + return CP_ACCESS_TRAP; + } + + /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1PCTEN. */ + if (hcr & HCR_E2H) { + if (timeridx =3D=3D GTIMER_PHYS && + !extract32(env->cp15.cnthctl_el2, 10, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure && + !extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } + break; + + case 1: + /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H= . */ + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure && + (hcr & HCR_E2H + ? !extract32(env->cp15.cnthctl_el2, 10, 1) + : !extract32(env->cp15.cnthctl_el2, 0, 1))) { + return CP_ACCESS_TRAP_EL2; + } + break; } return CP_ACCESS_OK; } @@ -2338,19 +2376,41 @@ static CPAccessResult gt_timer_access(CPUARMState *= env, int timeridx, { unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); =20 - /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if - * EL0[PV]TEN is zero. - */ - if (cur_el =3D=3D 0 && - !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { - return CP_ACCESS_TRAP; - } + switch (cur_el) { + case 0: + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]= TEN. */ + return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); + } =20 - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && - !extract32(env->cp15.cnthctl_el2, 1, 1)) { - return CP_ACCESS_TRAP_EL2; + /* + * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from + * EL0 if EL0[PV]TEN is zero. + */ + if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + + case 1: + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure) { + if (hcr & HCR_E2H) { + /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1= PTEN. */ + if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ + if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } + } + break; } return CP_ACCESS_OK; } --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341098; cv=none; d=zohomail.com; s=zohoarc; b=SoteuyTT+25/M4LwqzVTpTBojPLPbief+RLDLUFS2EBA3a3CClrozDIaDXB/r+IEL4RRT1VT75HXgSUo7hA+fHmug6drsXRUTlvClyQe84PIBSZZDJglPPfqx8DG92hbkuA4sbiXqgewHCdpX73C8DSJO8iAs7fOxe8Cx7xiswA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341098; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=t0KxplJe1stLtOSq2ERXdsGF3/Ph5ETCUlajlx5MnoE=; b=fKYIaHkhz1jLIW2gdufDfNcgBZOima7xwn2ElmFDHjDXYf1gMM5XwloeJSbpSs9q4jW7zujCbFXbK0l+7mJ5TNOWZZ/S1tRDEdCMutIWJ4VTYseGYkewEVr9Etq/DqXszxISlpNCY6f+xbqwDMFxZ42oChhvqFvpKONMytU7OkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341098678253.28327864858238; Mon, 2 Dec 2019 18:44:58 -0800 (PST) Received: from localhost ([::1]:47366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyBL-0003wU-SW for importer@patchew.org; Mon, 02 Dec 2019 21:44:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60997) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxI-0003M5-S1 for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxB-0008Rw-7v for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:21 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:38835) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008Na-OE for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:16 -0500 Received: by mail-pj1-x1042.google.com with SMTP id l4so821007pjt.5 for ; Mon, 02 Dec 2019 18:30:14 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t0KxplJe1stLtOSq2ERXdsGF3/Ph5ETCUlajlx5MnoE=; b=VkYp8+LlTxZ6CrbDqi45/knG3VSX+u9/Ew2+QOFi7KHeb/NN+o/LrbT7Zv8ZlS+ib9 OhSxo2sjeuy0HNU0cZKqthJ4n4pWPj20ryznqsXURWDqdCgOvk5FGrBVn2DwdB6yfP+n YeB2i6WImPisbmfQfvcbXdBuHZJtX82a5iT+dWesTJlNEimspx0z+tpSZA2Jzl5N3nEQ ub9L6SpPSljpaP5lbpw64LJcoX9d7nNNFaPe73w31pA+8Ufwu0CtTjjG9EMrTNRZDJqN bTB3Kt0y+yxAxVI8rMP/+6vOTAPs/w72VlNHGxfUj+MBDx5I+bzT5YXylh6VwY7xHV5o jOEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t0KxplJe1stLtOSq2ERXdsGF3/Ph5ETCUlajlx5MnoE=; b=XRucVarOiKuNfmA/hJeHr7Y+Szws09Bu5+7EWGyUNSfO219MhchmWO3FHCnPFh1DD/ XU9+g5PrLMulPoyHP+Jjmmn6YAJ3V/bYrGY0RMiCgTvl6CrvPZyX9vvUjnr2F+tJJwFr o2flLKIfF1/vBc5Z8WQpG2r2mbfD91kjqPECWeJP63WNlA+Urh1B3vPX1k5fGcU0pe8Q IOrJQy6dwtw4oD4rQ9Nm/sjo9/cOS6bETRdDSeSN8TbXJIwhSbUVDbibG+Qlj9nvI5Yu 6yeW4Z0mDUZ7D0enIjolUogLMhKrx1v1yImpDOOeVJSznNvye59d+9rDCFcHpeDk8lTZ emCQ== X-Gm-Message-State: APjAAAUR/c7M4AWEg/ivJeU+my9VqkXlAQTJL2+2150UqzfF/hsi7O6n wbQCbuHwynjB4PDazjDiF2sYxz9Bh9U= X-Google-Smtp-Source: APXvYqzQcjdhzzGKWbDaJeRyrAN9aefSVvL0xvVIZNKjFQRAfUkhQQkF8ML5B6chYV1aXcOaqA344Q== X-Received: by 2002:a17:90a:610:: with SMTP id j16mr2891477pjj.85.1575340213106; Mon, 02 Dec 2019 18:30:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE Date: Mon, 2 Dec 2019 18:29:23 -0800 Message-Id: <20191203022937.1474-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For ARMv8.1, op1 =3D=3D 5 is reserved for EL2 aliases of EL1 and EL0 registers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 023b8963cf..1812588fa1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7437,13 +7437,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, mask =3D PL0_RW; break; case 4: + case 5: /* min_EL EL2 */ mask =3D PL2_RW; break; - case 5: - /* unallocated encoding, so not possible */ - assert(false); - break; case 6: /* min_EL EL3 */ mask =3D PL3_RW; --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341713; cv=none; d=zohomail.com; s=zohoarc; b=QZFxQAkkIT5dHSHwctdra40vgQwDvUH1aUgNHJ7X3zA7y1k2uqc705vzl0SSVIhT0mQEmEkdlN4RPBKYjCYo42YWVE1o4ZhUBMVAgtL+2NXV5RVKmr1086LAHWxMipxAQJydXMvX4ba0G/Pundhq7v8Kh3aJhikmUYkggF7JqSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341713; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=2do0V8CqM/10UYZ2RnaFTjIn7GR8F62eVWz9oBJpzRE=; b=B/8gcncSjxixM9lGaQisLmwmFmWdwiVhEQ7TivzWR5ocbX+GRy9p5C59230FDs5fS8zontQJnzZWudHE4T3Mv5bHvt5vjXErGcWI4eYMLO+nMy5s2L9GN3UJKI7RUrGxt8AjmPqwc8kheF0mFXzyBMFn1K7Qjv76UqzWtO7N0V4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341713286493.05026299688495; Mon, 2 Dec 2019 18:55:13 -0800 (PST) Received: from localhost ([::1]:47547 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyLH-0007xX-Hs for importer@patchew.org; Mon, 02 Dec 2019 21:55:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60995) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxI-0003M4-Sb for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxB-0008Sd-Ba for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:21 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:43739) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxA-0008O5-PQ for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:17 -0500 Received: by mail-pj1-x1043.google.com with SMTP id g4so807900pjs.10 for ; Mon, 02 Dec 2019 18:30:15 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2do0V8CqM/10UYZ2RnaFTjIn7GR8F62eVWz9oBJpzRE=; b=ob/QqOW8SOuhQmV/G+ro7DLzN+UfUL+Z3X9LDVs6m+tQ7hyHDah4jZsQzzAf/14Wgy vGDsa5035Y1tMJ1jnEdshjlvr00sctsdAA69sFVZz/kl5+oyaHHwbWLpEzGyIgmBdSen avWDFtXuI1AoQjet8p0YBwQNkj3i/ZYjACQRufIDm+nLkFwirfeGHctikgGKsoUZcH1a M82b877BeadjyS1KAz51QEkCl6mKvwe2FvjxEeD1JL7hJ+xTNQkdaEa7TByRrMtD2YiU ddyn0j3H5gHDaUoE3G1zhr8KeXNl82Vr81c3YFrGLNrTmwL9GRRvVYVyJK3DNIkYekRV eYXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2do0V8CqM/10UYZ2RnaFTjIn7GR8F62eVWz9oBJpzRE=; b=ZOoBMdYJvnM8HwPL/ZrJAmD5MyDADgXZIvErv2DgXzpYIlY5aAmCvIJLQFqhAJasiP 6J8UhDvsqkBIWO7M+ZBS0ZtJSjQxLHJrN8MD0l41uTX+3v4NPZ4c8hAJplQagUB3Ktx4 4sq7mwA0qJjsK1XjMPcU3g5PFrulD1cJqMKRlJ8gbdUwAdQGIeNBh5XtqMdubsxh2ken KdgDMu0wVXeY94wVbgBL6R+rE2M/WI+XpxBNhPxT2qCW+GqrrtOWlPQvVW/8bwEuqv6x WnCfZQGbM72vxSk8HEE5U5wELAYi/fu+J1t1CQ+OVPfitoTD+7ZBlZ35s55KMDvmpmTO 1MEw== X-Gm-Message-State: APjAAAVVpzi8qO2exfu0Y+VstZBZx7xsX17I6yAP26BZGTdSxztvLpiE tbn0RQHnKLbt6kwlAG5FbXqTNE4BA8s= X-Google-Smtp-Source: APXvYqxyA8kUMmrFgFrVJAyNLOmVM552ScBdYm7FahHiqqfe8DHFTx4m/MYaW6abgKJpyqAxFMnumQ== X-Received: by 2002:a17:90a:a114:: with SMTP id s20mr2953739pjp.44.1575340214300; Mon, 02 Dec 2019 18:30:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing Date: Mon, 2 Dec 2019 18:29:24 -0800 Message-Id: <20191203022937.1474-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Several of the EL1/0 registers are redirected to the EL2 version when in EL2 and HCR_EL2.E2H is set. Many of these registers have side effects. Link together the two ARMCPRegInfo structures after they have been properly instantiated. Install common dispatch routines to all of the relevant registers. The same set of registers that are redirected also have additional EL12/EL02 aliases created to access the original register that was redirected. Omit the generic timer registers from redirection here, because we'll need multiple kinds of redirection from both EL0 and EL2. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 44 ++++++++---- target/arm/helper.c | 162 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 193 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4bd1bf915c..bb5a72520e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2488,19 +2488,6 @@ struct ARMCPRegInfo { */ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ =20 - /* Offsets of the secure and non-secure fields in CPUARMState for the - * register if it is banked. These fields are only used during the st= atic - * registration of a register. During hashing the bank associated - * with a given security state is copied to fieldoffset which is used = from - * there on out. - * - * It is expected that register definitions use either fieldoffset or - * bank_fieldoffsets in the definition but not both. It is also expec= ted - * that both bank offsets are set when defining a banked register. Th= is - * use indicates that a register is banked. - */ - ptrdiff_t bank_fieldoffsets[2]; - /* Function for making any access checks for this register in addition= to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at @@ -2535,6 +2522,37 @@ struct ARMCPRegInfo { * fieldoffset is 0 then no reset will be done. */ CPResetFn *resetfn; + + union { + /* + * Offsets of the secure and non-secure fields in CPUARMState for + * the register if it is banked. These fields are only used during + * the static registration of a register. During hashing the bank + * associated with a given security state is copied to fieldoffset + * which is used from there on out. + * + * It is expected that register definitions use either fieldoffset + * or bank_fieldoffsets in the definition but not both. It is also + * expected that both bank offsets are set when defining a banked + * register. This use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + struct { + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; + }; + }; }; =20 /* Macros which are lvalues for the field in CPUARMState for the diff --git a/target/arm/helper.c b/target/arm/helper.c index 1812588fa1..0baf188078 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5306,6 +5306,158 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +#ifndef CONFIG_USER_ONLY +/* Test if system register redirection is to occur in the current state. = */ +static bool redirect_for_e2h(CPUARMState *env) +{ + return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); +} + +static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + CPReadFn *readfn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + readfn =3D ri->readfn; + } else { + readfn =3D ri->orig_readfn; + } + if (readfn =3D=3D NULL) { + readfn =3D raw_read; + } + return readfn(env, ri); +} + +static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPWriteFn *writefn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + writefn =3D ri->writefn; + } else { + writefn =3D ri->orig_writefn; + } + if (writefn =3D=3D NULL) { + writefn =3D raw_write; + } + writefn(env, ri, value); +} + +static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) +{ + struct E2HAlias { + uint32_t src_key, dst_key, new_key; + const char *src_name, *dst_name, *new_name; + bool (*feature)(const ARMISARegisters *id); + }; + +#define K(op0, op1, crn, crm, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + + static const struct E2HAlias aliases[] =3D { + { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), + "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), + "CPACR", "CPTR_EL2", "CPACR_EL12" }, + { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), + "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, + { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), + "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, + { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), + "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), + "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, + { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), + "ELR_EL1", "ELR_EL2", "ELR_EL12" }, + { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), + "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, + { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), + "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, + { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), + "ESR_EL1", "ESR_EL2", "ESR_EL12" }, + { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), + "FAR_EL1", "FAR_EL2", "FAR_EL12" }, + { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), + "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, + { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), + "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), + "VBAR", "VBAR_EL2", "VBAR_EL12" }, + { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), + "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, + { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), + "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + + /* + * Note that redirection of ZCR is mentioned in the description + * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but + * not in the summary table. + */ + { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), + "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, + + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ + /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ + }; +#undef K + + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { + const struct E2HAlias *a =3D &aliases[i]; + ARMCPRegInfo *src_reg, *dst_reg; + + if (a->feature && !a->feature(&cpu->isar)) { + continue; + } + + src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); + dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + g_assert(src_reg !=3D NULL); + g_assert(dst_reg !=3D NULL); + + /* Cross-compare names to detect typos in the keys. */ + g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); + g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); + + /* None of the core system registers use opaque; we will. */ + g_assert(src_reg->opaque =3D=3D NULL); + + /* Create alias before redirection so we dup the right data. */ + if (a->new_key) { + ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); + uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); + bool ok; + + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D 0xf0; + + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); + } + + src_reg->opaque =3D dst_reg; + src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; + src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; + if (!src_reg->raw_readfn) { + src_reg->raw_readfn =3D raw_read; + } + if (!src_reg->raw_writefn) { + src_reg->raw_writefn =3D raw_write; + } + src_reg->readfn =3D el2_e2h_read; + src_reg->writefn =3D el2_e2h_write; + } +} +#endif + static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { @@ -7142,6 +7294,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) : cpu_isar_feature(aa32_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } + +#ifndef CONFIG_USER_ONLY + /* + * Register redirections and aliases must be done last, + * after the registers from the other extensions have been defined. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + define_arm_vh_e2h_redirects_aliases(cpu); + } +#endif } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341514; cv=none; d=zohomail.com; s=zohoarc; b=j/qtB2A1/MVdTDWCPo/eqV8qcjuBqA+SaGqPne37kyYfe4MPhD3aPzOY9Teg70StDbRm36PdpJ1d6jXkLuT6qZlCdhMzRIA6U7TIm/CrEoeiRS+tvx1Gs1i3Jw3zhTUI5BNGUhHttFo+bxny95uuC6QYIxdMpSaOdDX6uMvcNvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341514; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CRgvlrlUUYPKRy0Fi2/c+Pxx/S2Xg9uvm303hT3/JXo=; b=JvfODTQVkDi4aSQe1TvmxViIdOG0XAUQ0jLOv3rrfl8CZmkWDRjvwtQJIiYYmk5Kkz HBi/F+3BO8zSsgu96Evz3rCkKnO3MwD0rYqVi7bDckbSt0aKWAuJtwP1kdbvub9kJFnt kzB0gWzUUXVp9q07/e2idwDxqvFbdTn2GltSkFPbwS2vmgcwtMOi9DfDtjp39CzitBoN /6k2BwFJz11n+i4Zi4Pffb26eg/x1y1HY+aT+IoRc4snLEGXJdCTp0EQBDlUXY1N7Fn6 ZcdofPl/qIzj6Zs65aePhBv3/+bNAMnl+fE4ABk49AYA7u8zKXITN/oBFBytzhePa+Ha tA/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CRgvlrlUUYPKRy0Fi2/c+Pxx/S2Xg9uvm303hT3/JXo=; b=hjpvtDr3Jk6/W2HZ5iwfj7le4FfoA/LGjFjBaX3Q9kt3Nqj51RkNDAmTCfuEvsQ8QO 8Iz/JqZhn1lsYR4pI6a/t67cK/7qgjYAihURWRJ+f4TddcEv6GSAL5e2h5eqcxxOjG8p pNxvzCSbgkk89awZngniv9S0ANsXVQkcZTjRACmXeP3PldY5N8vw3fhAMNqugoSelcw1 MJboV3XkxjGB+RPkJVc+LNFA4yakOaW4cmAD5p8gD/bTRspkrh7hQTLZB7tTN37UDzIr N0rVVwaLCuh4SJlWMmispq4C28iW29VOzzpX+LaB9mLzAlQV9d9cjjGysaMblOJNYhrY TSuA== X-Gm-Message-State: APjAAAUIBHL6MbgO0DmPi2R08yFADk0biZ0gkIBoZYlprkwzJm6jJWK5 Qu5Tz3rSTZ6Nxg8nTt81n8WmYAVVWsQ= X-Google-Smtp-Source: APXvYqxElsad0L9BUuASZGgVuhpbabsbN8jgMLH80mIo7wsQszvZGAulGiy8qV0FOOwBo6CrWPgotQ== X-Received: by 2002:a63:b49:: with SMTP id a9mr2843753pgl.386.1575340215205; Mon, 02 Dec 2019 18:30:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/40] target/arm: Add VHE timer register redirection and aliasing Date: Mon, 2 Dec 2019 18:29:25 -0800 Message-Id: <20191203022937.1474-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Apart from the wholesale redirection that HCR_EL2.E2H performs for EL2, there's a separate redirection specific to the timers that happens for EL0 when running in the EL2&0 regime. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 191 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 179 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0baf188078..9df55a8d6b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2655,6 +2655,70 @@ static void gt_phys_ctl_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_PHYS, value); } =20 +static int gt_phys_redir_timeridx(CPUARMState *env) +{ + switch (arm_mmu_idx(env)) { + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: + return GTIMER_HYP; + default: + return GTIMER_PHYS; + } +} + +static int gt_virt_redir_timeridx(CPUARMState *env) +{ + switch (arm_mmu_idx(env)) { + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: + return GTIMER_HYPVIRT; + default: + return GTIMER_VIRT; + } +} + +static uint64_t gt_phys_redir_cval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].cval; +} + +static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_cval_write(env, ri, timeridx, value); +} + +static uint64_t gt_phys_redir_tval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return gt_tval_read(env, ri, timeridx); +} + +static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_tval_write(env, ri, timeridx, value); +} + +static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].ctl; +} + +static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_ctl_write(env, ri, timeridx, value); +} + static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_VIRT); @@ -2693,6 +2757,48 @@ static void gt_cntvoff_write(CPUARMState *env, const= ARMCPRegInfo *ri, gt_recalc_timer(cpu, GTIMER_VIRT); } =20 +static uint64_t gt_virt_redir_cval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].cval; +} + +static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_cval_write(env, ri, timeridx, value); +} + +static uint64_t gt_virt_redir_tval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return gt_tval_read(env, ri, timeridx); +} + +static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_tval_write(env, ri, timeridx, value); +} + +static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].ctl; +} + +static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_ctl_write(env, ri, timeridx, value); +} + static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_HYP); @@ -2842,7 +2948,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, @@ -2859,14 +2966,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .resetvalue =3D 0, - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, @@ -2874,14 +2983,15 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .resetvalue =3D 0, - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, }, /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_NS, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, + .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, }, { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, @@ -2894,18 +3004,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, + .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, }, { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, + .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, }, { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, + .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, }, /* The counter itself */ { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, @@ -2935,7 +3045,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .accessfn =3D gt_ptimer_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, @@ -2951,14 +3062,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .accessfn =3D gt_vtimer_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, @@ -2966,7 +3079,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, /* Secure timer -- this is actually restricted to only EL3 * and configurably Secure-EL1 via the accessfn. @@ -2997,6 +3111,15 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]= =3D { REGINFO_SENTINEL }; =20 +static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + #else =20 /* In user-mode most of the generic timer registers are inaccessible @@ -7257,6 +7380,50 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D= 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), + .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D= 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), + .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D= 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_wri= te, + }, + { .name =3D "CNTV_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D= 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_wri= te, + }, + { .name =3D "CNTP_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D= 2, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), + .access =3D PL2_RW, .accessfn =3D e2h_access, + .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D= 2, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), + .access =3D PL2_RW, .accessfn =3D e2h_access, + .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + }, #endif REGINFO_SENTINEL }; --=20 2.17.1 From nobody Wed Nov 12 23:10:21 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1a8ny/hnKkIfvEvhTYkU192OfcIHoxtAmofS/9eIiaE=; b=eGe0fRnwhgZSuf0WV0QU88VpcK1P4PdFtzrmWibjbTsKWEKeONT1Bv3L3sR+fe9h+D RFtUXAj2UGu9PUrqiYQzXSzXK4wvOCVBXxsKZNeJBVeII1tZ/9aK5+czoTqtmvZhwzDJ rQM1lwk5aCHnaIUpSJXvnIAYbTj1IIuy1j2ia3r8H3Wxz+1kuXF/exxL1tNdwnc3aBbI 0i56Jf1G1pqtQ2IJhMh0GF1gpQgbyh8O2Op3DehhNigI1aazi7X4AOBda64jGSrwHU99 eEowgvYLaqoX1KXUQ3xmkoown5A6aTe+1iQuVTC2YulBZgSi3jFkptqryHAtN9yZbvH8 P38A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1a8ny/hnKkIfvEvhTYkU192OfcIHoxtAmofS/9eIiaE=; b=ir79uA1hW3gERojbcy0gxfJoD5ppWwxgeKkYQ7zJ6QGSQzWvBwcRUOwKRM0DxqECFj CiCkEw/ptzEBWOGpa5p1V4GqXU8e3WP04PidVL0pNr+DyYBzlJVMJN85yaNNqYfieW+5 jmTsd8cHeIwRjKvym/83rDKsJ5NkpFlx4I+Sd7OkQ9OtwcueLmvvAec45Ut06VT07Lw6 gG6o0UltudwgQKq26vKQm3IFnlE+pPfkfQqyAp3SRTtsuF8e6rJLKBrWrSbqDvV5USCK R7/PVDaOWCoOf20XiysgFOV/rIxBeP3EgM0X2zBIJEZVIqIka9EcpO9dgn7AI4BnPCXb QHpg== X-Gm-Message-State: APjAAAXcIVj1q/J5wt+SoZnnqnlUPM7AXoOKto/ctXQsAZvigtNxJSDx WdeIYI83hXYWfWueD9RzUgG+qF9rIqU= X-Google-Smtp-Source: APXvYqw2DikZuTCX44ZK4L+jlmjR4i1ecyu4ydltoQ3GAMS/u/XwIuLZJIf5MtbObwVruoUdpUap2g== X-Received: by 2002:a63:4104:: with SMTP id o4mr2751403pga.169.1575340216561; Mon, 02 Dec 2019 18:30:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Date: Mon, 2 Dec 2019 18:29:26 -0800 Message-Id: <20191203022937.1474-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since we only support a single ASID, flush the tlb when it changes. Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9df55a8d6b..2a4d4c2c0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3740,6 +3740,15 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { + /* + * If we are running with E2&0 regime, then the ASID is active. + * Flush if that changes. + */ + if ((arm_hcr_el2_eff(env) & HCR_E2H) && + extract64(raw_read(env, ri) ^ value, 48, 16)) { + tlb_flush_by_mmuidx(env_cpu(env), + ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0); + } raw_write(env, ri, value); } =20 --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341325; cv=none; d=zohomail.com; s=zohoarc; b=YZIYZHYjrfs+x/kjGMTuEjVXWOZPDyPn2Yfn7ieWwy/P0Br/xNcGkLJX1fmAS34Qmct5pURJWEzkP6VGQpjvBUQruKVbT9hKU4NsChY4JeuE8OO/BzaNNszeTwpW5oPrdkfU1PdzGmw5tgXOpp46GvKVbfIFJkf1OD565FOZX3c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341325; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=sgf9PjMDcr7YkI/Fw1uObi5dAB9s8zvthtA9mINjU3o=; b=VHGnKUiJYKzM5RSvIPkaEg7wzL7qMZYxGPKkVh/kRZzzKxQ0HYBERPpHT4cYnjI24fJckWp545IM1jUSQipwDs2LzGVqf1UvN1xbVMXbv2hvRg7n4S6Y7gdaOzJv7zrdtd59+vC2Yup1KzkChaIM/+X5INFjsdG61Dz9TCNgTMM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341325090808.3524886311782; Mon, 2 Dec 2019 18:48:45 -0800 (PST) Received: from localhost ([::1]:47424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyF1-0007r6-HE for importer@patchew.org; Mon, 02 Dec 2019 21:48:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32802) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxI-0003M9-Tg for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxF-000094-OM for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:23 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:33602) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxD-0008VY-EQ for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:19 -0500 Received: by mail-pl1-x641.google.com with SMTP id ay6so1016845plb.0 for ; Mon, 02 Dec 2019 18:30:18 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sgf9PjMDcr7YkI/Fw1uObi5dAB9s8zvthtA9mINjU3o=; b=GUBiTl0d9K/QvgfTFCt5yHLT4hoEcCy4anS6I8v6lAkd5BdOr5vEC5hCDeI5QNv9+S 2JZYtdqUcnPVm1bCELOZs8qoeh9RJCCsTcV4Mwa6UVXszo3w1kloqf1h/Y0NsYA0BBPZ yrPX4mqtIlHjZK69JDGSA70e4exqI6puK7JuV3w570SEYgq2LYltOhhojViW5es9ScM6 dwR9GTZuuxlBsysrINzuY1Bd2jzVUWagg4gjOW8fd83KQiZPQmLdoviq5OqvtUkspoRr UuTvyz+KpW9avgrBWaibvT6kc+kd/XvVCJeTr22Z8LGFNzMY0pv/ZDr/pIrgi7qeZf7I xhUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sgf9PjMDcr7YkI/Fw1uObi5dAB9s8zvthtA9mINjU3o=; b=mrUAbEjJEgaRe0i3rKTDAgCvoQGyQojU12doPpOxtBm+Bivw9aOgdNfMnTQGQbim1P pGsXmnubr2Jl3EVuo6xkl7nGkvRRp5UAW/FAVrwTFMLLqWLEXvyyx2I1bxAMe4226PGI QwVKJXwF9ZndPQRlx0+oUArqQRr8PD3umru5wHjYaX5fnAUmN62pFTh7kvt5nbI7zoSE YoEcy2nHgtMRh7r2fdtBiMmK6DyQZxtBAL2HsJAh+sVyxyOxnmqlW0xjiHm4VAIvGa2l 7eXtOTVA4A5x3ST1icOc5Mo/ERy+CT+VeEhz6oBzfM4OtJEuH+Gg+vNvTNngPi/GRDcK m4sA== X-Gm-Message-State: APjAAAWF8WJvVvU3x92j90Xti0LqoFjtx9+FNSstdHZEeQaa82pmry3m YXvQNcgdaAO1HzUZk4UtQvjCr6Qz6qA= X-Google-Smtp-Source: APXvYqxqhdsOrHoCMI6js5wteaRS2kgsejeukOFOQOOTq4NI93VDgbbzAKR2a+2J3dzMb2IqbsgSOg== X-Received: by 2002:a17:90a:ae01:: with SMTP id t1mr2959645pjq.32.1575340217654; Mon, 02 Dec 2019 18:30:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/40] target/arm: Flush tlbs for E2&0 translation regime Date: Mon, 2 Dec 2019 18:29:27 -0800 Message-Id: <20191203022937.1474-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2a4d4c2c0d..b059d9f81a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4123,8 +4123,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, =20 static int vae1_tlbmask(CPUARMState *env) { + /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; + } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) + =3D=3D (HCR_E2H | HCR_TGE)) { + return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -4158,9 +4162,14 @@ static int vmalle1_tlbmask(CPUARMState *env) * Note that the 'ALL' scope must invalidate both stage 1 and * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. + * + * Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; + } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) + =3D=3D (HCR_E2H | HCR_TGE)) { + return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; } else { @@ -4177,13 +4186,22 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,= const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 +static int vae2_tlbmask(CPUARMState *env) +{ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + return ARMMMUIdxBit_EL20_0 | ARMMMUIdxBit_EL20_2; + } else { + return ARMMMUIdxBit_E2; + } +} + static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4208,8 +4226,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4227,11 +4246,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, = const ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341878; cv=none; d=zohomail.com; s=zohoarc; b=CEsUyKjUxHSINRGh36Mol0vHs17vPPCRJIMacyPtK/xKn20gykmsZmsJ6Art+yYGy1j38CqC4q7B9wOG4gpToGO7C+PP1//XKQXsvlN8SMTujpiN/2Vf9e5/jSDEbwmG9vgPyAS76yEYsm71cNYkSxn2kQrFLyUyOBdwcaL9z7U= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IK7rSI06S6h9YUMM4pqvJuR/qhJRw6SERUwBa547XN0=; b=QSu/J7steepWES5yflZElUbSs4dYALg07BxZKiUyqwzF8ZRJhwcsSiLhpMBpGtFFjE SFzjvMIyX6dUH6dGG6nLRadIwHxUH4nwjSgSJ4kO7NPV/APNgbFRZLYqkuzfRgV70N8H n50KZeRXtjCQtnPb+i5FfdHt78/jqKbaeX3DSyy1Nc2QEl3H6p6K/fJYVIhzB+2yd6FM CEXaFjodHuDCt+MKs78o8TzSGMQzHo/fAAf4yL18KoQ1w1fsbR4Ukbktwh9zH5sWePie e0J8AZ+uhgBjZK3LKD0EBks/gBCy45Z/PaTBLV6H2X9F6yvPe/ZKbJC/YY+PIq/zzGQI MkTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IK7rSI06S6h9YUMM4pqvJuR/qhJRw6SERUwBa547XN0=; b=DSMBWJjVQwW5lIehdDhmhLYZjCRLPOPf8Mu7P6P0cq96Cj4f6KcvRHs36OsWttjp9L PCM31ihEFKEfz1qSqGC9gPkXzklseGzvLP+RJAYovXJhBiDUpEwq97/de/iN06ox9Wgo bZTmp/q9D1mwiE6sxLiqhU9Q5UWs9KO6KebvFnlRgPj1t3gc/tQ10V1eJea2Da2xzNm2 7tw6UH8xZaSR6Pt1Z7rOiDYIwxxmJpf7d5tfaBQ6xVszYy+CpJGR0Cy8Qar0N8Lwz/PU N71HFjFYnsPQ9sa1dTikLrAgxe/5BpeW2VBPZm+ODOZEgtegNBDfIo0RWqY6ncOgL9Ba HbsA== X-Gm-Message-State: APjAAAWGsu+kMj9WXOEk4crg2NtJmxkPNblsAWRX7MngTl58AI0KTn8k M6SRRdRqbAjoWCvnuCpj8ufZmk81NVQ= X-Google-Smtp-Source: APXvYqxOz+Ih3oil3MtBE6RBbtUrjSr+FGT07F93ko1pnjgEq9cvsgF1EbmWxKQkiTt8xN6nNzlpsw== X-Received: by 2002:a17:902:9a96:: with SMTP id w22mr2679175plp.124.1575340218750; Mon, 02 Dec 2019 18:30:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/40] target/arm: Update arm_phys_excp_target_el for TGE Date: Mon, 2 Dec 2019 18:29:28 -0800 Message-Id: <20191203022937.1474-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The TGE bit routes all asynchronous exceptions to EL2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index b059d9f81a..e0b8c81c5f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8316,6 +8316,12 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint3= 2_t excp_idx, break; }; =20 + /* + * For these purposes, TGE and AMO/IMO/FMO both force the + * interrupt to EL2. Fold TGE into the bit extracted above. + */ + hcr |=3D (hcr_el2 & HCR_TGE) !=3D 0; + /* Perform a table-lookup for the target EL given the current state */ target_el =3D target_el_table[is64][scr][rw][hcr][secure][cur_el]; =20 --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341814; cv=none; d=zohomail.com; s=zohoarc; b=EkzdqP6iydibXCnyMEi2o3J8+nRUPA8RC5yvO/SZG61WTlKJUvEaFw71+7RJ5QN6JBjUfpe8xVvyPleMDgZP45RbiwZPaZSsG+NxzJWgbIKX6BHrmgqkj+lCwRi05+ZM+pEuV6P/IuSnGzN3wj9Lq84o5h2bGl+IWCvlKyzmr6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341814; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=wrciTI1v/mNpw+XObN5cyZ1jMW9FF/u8Ocv1yHt3lTU=; b=mTI4kHXiAkxEoYUGV+WeP25MxH/xBnsIljnp9C/45SpnBCcrEUFjujsVkS2gh+9xeI4OrmhNDN9Su7Jc8i+K4xBOuBlN5Vibqz6OmPoae8kOzMxv+k+OuSiS1csBdPpdefBy3gTY6dxV+2AK2oscWcr4OojEHOTVGvR+CzOl7/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157534181486336.89205420105384; Mon, 2 Dec 2019 18:56:54 -0800 (PST) Received: from localhost ([::1]:47602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyMv-00023d-Cz for importer@patchew.org; Mon, 02 Dec 2019 21:56:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33140) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxL-0003Pi-VM for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxJ-0000Ch-Tr for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:27 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:46177) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxH-00008j-MV for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:24 -0500 Received: by mail-pj1-x1041.google.com with SMTP id z21so799042pjq.13 for ; Mon, 02 Dec 2019 18:30:21 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wrciTI1v/mNpw+XObN5cyZ1jMW9FF/u8Ocv1yHt3lTU=; b=ROljyHfZLuEU7PDLX5pc8bRpKTjz3BSqEn6fOyHa83GBVEttSWWx9z5tvzkEkjvI8h UKRTQkhq6zi+qaE44qNM1eDK1a+gnALoa6zbi5Jel34Kngqm+ulgFwYfSKUXHLLDnd1A Cc6MEdcHCLo7QDD/acEBz4+3mEARCOtkeN/jCp3ozTn2tJPSmDMQjrRWEJgNFm9/8B4T KENKnHcrmg9ScOh1nokDBPdJBsALUgKUTEfIqKzhHp9UIZOwKSV9iv/qThMZvGj3CzdE e9B9eofKxugshmVPgsfzmUP6GrewLR0liAm1cy6A9RM5MFUtNn5FtBd/45prCeE6CbM/ 1aAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wrciTI1v/mNpw+XObN5cyZ1jMW9FF/u8Ocv1yHt3lTU=; b=oy39EynBvYCjKufsDMHGQNnIdAEudnh2ObrxBDfmMqq2fXBdlbysUnJAp1j+6hnLXC iquhm7etA5UXWgJnyfRxqmypR0zySj3rS+qHWgEMTxPSlT2KHZhyusYHBLKe7ra9J1v5 bj92J7386mKTlKBA8ONXyp+CB+/FfHsD0+u99tYTNwuas/vsqFELCgETZDXWR9VMd2uH cE8MTf0W/9zwWcxrzxiHGtguP9gMWvXyJzVF7I7JH/UgjBvzTVg1er8h2X6JBQ9fxXpL lR0Trwg+Qk04OyKOAnuBkG+4W++m6r0/z94WRR6Ywe5L9aD5Poj0TC27S8BHVtHeJ6yM y0VQ== X-Gm-Message-State: APjAAAUZgzRelLPcwZyisRstEWYxqavQOYFyjgOxtuoAGURIqwL1tTeJ VuFcY7kbvD2VajcknfqwUcKwFWThIMQ= X-Google-Smtp-Source: APXvYqzzJ3EurqVqGxJuXn7PuuK8fu1euMl5j1oDXin3Jy2Pd2UxBg14lSlxn2vxEPnr68XfEMIHRA== X-Received: by 2002:a17:902:322:: with SMTP id 31mr2709960pld.244.1575340220163; Mon, 02 Dec 2019 18:30:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/40] target/arm: Update {fp,sve}_exception_el for VHE Date: Mon, 2 Dec 2019 18:29:29 -0800 Message-Id: <20191203022937.1474-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When TGE+E2H are both set, CPACR_EL1 is ignored. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 53 ++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e0b8c81c5f..3e025eb22e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5743,7 +5743,9 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - if (el <=3D 1) { + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { bool disabled =3D false; =20 /* The CPACR.ZEN controls traps to EL1: @@ -5758,8 +5760,7 @@ int sve_exception_el(CPUARMState *env, int el) } if (disabled) { /* route_to_el2 */ - return (arm_feature(env, ARM_FEATURE_EL2) - && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); + return hcr_el2 & HCR_TGE ? 2 : 1; } =20 /* Check CPACR.FPEN. */ @@ -11565,8 +11566,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY - int fpen; - /* CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ @@ -11594,30 +11593,34 @@ int fp_exception_el(CPUARMState *env, int cur_el) * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses + * This register is ignored if E2H+TGE are both set. */ - fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); - switch (fpen) { - case 0: - case 2: - if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + + switch (fpen) { + case 0: + case 2: + if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el =3D=3D 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ return 3; } - return 1; + break; + case 1: + if (cur_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; } - if (cur_el =3D=3D 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el =3D=3D 0) { - return 1; - } - break; - case 3: - break; } =20 /* --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575342290; cv=none; d=zohomail.com; s=zohoarc; b=c4Im8lk6TXPTIHgdEP9oXo9m0EAMwFUGQvmqvlN1J8HlDmxAFGkf5EOfFRNGWIcB6AGnJtSWAG8fwRjl/q/x4vSVjN+4P/xvAp+34cfbkqw9WdlTZBceimkrUwoL+MI3482JWryKqRkqIR+Bz8ZBorWCRVDu8ukyijeYhznoULY= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xGOB5EQSs+V4ihLVGdiYuoWjXTTUG1ZoRZwPeuW4pjQ=; b=yWY8UutOM1aWN3UdwO8zmSuevfvz90bKyIvRBwd3shDuVuWKfjCH2V0HzTxsVjUSM8 3cgLtg2yMmrn/RoQUelFUOeKgnADU5662U7JK00wf9Ta1ayanpGkpOEK+c6a2xjBb5xA vUBzgBl2RPPkBM1gbDD+dTpi2tm8ZPurkiawJB9V5K+7D9pQ5/gTIn/F3ZECby+C6mgN NUgzrrFUc9iURDGOVKYqMbyWaGrW92Kg8/8YVB+Qt/mjVF3Mkl2+tJf+AeHCXAaFq8jQ OgD44PIb2G6ebwWfrWdm/XyJRTYQ0yaIdbuwzlrqGeufjxwFKTD7ppvfJlFcy+2JvpJb OV6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xGOB5EQSs+V4ihLVGdiYuoWjXTTUG1ZoRZwPeuW4pjQ=; b=koDpkUcTXFTEy0zkMJsZiS6y3eExhDU6YdJ+5D039KbFMhYrWOpATID1UsKARVk0sD q1lcia42tyNvA5RdGRcb3/XL7BikDKGXT9v0euJWhpTGC45OLVWUgBpFUtDjhvdicJoF UsxuiGexijnGuD+oVvVYaysx+v554oxzmmLDtnqwnKi8d+fEUss8Z8ni3Nrtjq+chTXd pDkx6rcF7QIj8AIdtdqo1Lu70cOqeRh4av1kz+X1R8lwRhmjc9qAfnakbRwATuoL/4Bp XtqNUA1cbyCsDbsF7yXkAoauLuzzKIGmm9wHZrNtY45eVJ6Q3FFDOQrsIYveojPzS+UM Pmrg== X-Gm-Message-State: APjAAAXns7g6GzBXYUjGqPlEYLBjztLx+ny8gmSgQoNcehOqGDNhtCiz jCHcLYuok2opQmRrscq4VeqSzg1wm30= X-Google-Smtp-Source: APXvYqzjRnTMEQQPxOnOWcId9GNa20E/wvrg4sePmR50nyWqgGKkUZIatCUPJVIZZ8IOJX3VJ1w24g== X-Received: by 2002:a17:902:8508:: with SMTP id bj8mr2625098plb.178.1575340221229; Mon, 02 Dec 2019 18:30:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 33/40] target/arm: check TGE and E2H flags for EL0 pauth traps Date: Mon, 2 Dec 2019 18:29:30 -0800 Message-Id: <20191203022937.1474-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e According to ARM ARM we should only trap from the EL1&0 regime. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 42c9141bb7..c3cb7c8d52 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -371,7 +371,10 @@ static void pauth_check_trap(CPUARMState *env, int el,= uintptr_t ra) if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { uint64_t hcr =3D arm_hcr_el2_eff(env); bool trap =3D !(hcr & HCR_API); - /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + if (el =3D=3D 0) { + /* Trap only applies to EL1&0 regime. */ + trap &=3D (hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE); + } /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. = */ if (trap) { pauth_trap(env, 2, ra); --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341872; cv=none; d=zohomail.com; s=zohoarc; b=e/J2C9DDgIKZGVxqUeHCv4o7KFh0EXAbSla6GgaQNrcRv1SaFRW3SqHjS6LkZ5HOPV1yjJwA0ucH2nRZz9rox66EW1AW+YKmL+eZxRzg+PC/HaB9Hc66QM4H3ItjRZEcYHQY/kZytXKy2fv+WJpEFoGEy8NO2P1XBp8QfN9lahQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341872; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=qXyjILkTo9G8IoURRqIlskTheKQH1snr+t1caGFMi3I=; b=cMUSeiEbSUseou6N1VQoBaBoIDfpypVWb+qSWAwB1b+RitVjiPua2xFPfBBT5abvzMSlO5cLAo8rAV2I/k/wk1YrSI2IdKv/IdhrfvSkdU4gRwa77hBJ9Y3RIaJtjdlNU0U93iwsVtrNIzTtkYs77RC/HgWtcK1pDmWPvXyfk4A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341872246341.1372135593788; Mon, 2 Dec 2019 18:57:52 -0800 (PST) Received: from localhost ([::1]:47606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyNq-0003LX-Jc for importer@patchew.org; Mon, 02 Dec 2019 21:57:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33248) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxM-0003Qr-Em for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxK-0000Dc-5N for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:28 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:42467) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxJ-0000Am-OT for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:25 -0500 Received: by mail-pf1-x444.google.com with SMTP id l22so974617pff.9 for ; Mon, 02 Dec 2019 18:30:24 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qXyjILkTo9G8IoURRqIlskTheKQH1snr+t1caGFMi3I=; b=hoOqi4ZaAjuWQP2rbKe+71R8dgSWBpktQM3yYMO818Wb78GuUmpKygWnh/eoiO6WH2 CfYBqXVuVzWBfe8w8N8RM6b1oYnYPa8SPwqBuD9puwcMX4z40doILpIkw/CGHBFMhk5P dPV0mvLgI4qwPX4/JH9OPEjUUQQzS8wGUq8LiCNMszHPGMiIygNTWrMda7pou/5HVOY6 5CObsZWZcXyaf7osWlivP/jWL1SWVjKZQu+1DnMoK4tWyplTG/KOFGsB1FJMRchnzMNL +rsRS+NdmyOGNuh/nJ5icFfEkle2iH/AsJ58CrKIH0sW/eHH/DyWdok8CMI2MQNVUqzg BhKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qXyjILkTo9G8IoURRqIlskTheKQH1snr+t1caGFMi3I=; b=iCwBaHCZ9hAoa2fxM4POKktNxzABjh8hh14fokRmyULRc6vjDkDIdBNy2sib2ZD9ZV Gtjwoasssadhl2zM/kVRRKW3lLVKnAEFWzycdrOP7ZVQ/lXNZ0vJBLN81mQrWYmkiRoy cV3xJjD/k0+NDauVCHdApaq9MGR5SUUTRzQlHC/b1LA9aszCpnhm5ZQIqUpKLtAOf1lp 1xbD4mG0K6AFMz4iFjE1ndv9zouxyQvk9f2yMO98M+vksWeupwhnCxc58Qp8Vua+yIWg oTrcG4X23MI8+lh8sgvQC4fQwO5UBgVuaTzlkhzd4qvArC/i9R22IsgvYUGggzIDGncb mdvA== X-Gm-Message-State: APjAAAV/P224ZkFep7u2SoFS9hXq3wprWaGppCiCD7u0CIalOd0S8tZi Ir1WzeoXZCSBWLVeVOqpdWXvviGk+Ro= X-Google-Smtp-Source: APXvYqwok99+pBXVmYe+kGXg18FuZ5pfHNjcwsv33NcMlgKxdkIVeq83qmjf3OUtr7unf/g5RJfnww== X-Received: by 2002:aa7:8155:: with SMTP id d21mr2267926pfn.26.1575340222938; Mon, 02 Dec 2019 18:30:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 34/40] target/arm: Update get_a64_user_mem_index for VHE Date: Mon, 2 Dec 2019 18:29:31 -0800 Message-Id: <20191203022937.1474-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The EL2&0 translation regime is affected by Load Register (unpriv). The code structure used here will facilitate later changes in this area for implementing UAO and NV. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 22 +++++++++++++++++++ target/arm/translate-a64.c | 44 ++++++++++++++++++++++++-------------- 4 files changed, 53 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bb5a72520e..8e5aaaf415 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3239,6 +3239,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, UNPRIV, 14, 1) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 3760159661..d31d9ad858 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -73,6 +73,8 @@ typedef struct DisasContext { * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. */ bool is_ldex; + /* True if AccType_UNPRIV should be used for LDTR et al */ + bool unpriv; /* True if v8.3-PAuth is active. */ bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3e025eb22e..f2d18bd51a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11879,6 +11879,28 @@ static uint32_t rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, } } =20 + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ + /* TODO: ARMv8.2-UAO */ + switch (mmu_idx) { + case ARMMMUIdx_EL10_1: + case ARMMMUIdx_SE1: + /* TODO: ARMv8.3-NV */ + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_EL20_2: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20_0 is + * gated by HCR_EL2. =3D=3D '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; + } + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0b65c49e2..fe492bea90 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -105,25 +105,36 @@ void a64_translate_init(void) offsetof(CPUARMState, exclusive_high), "exclusive_high"); } =20 -static inline int get_a64_user_mem_index(DisasContext *s) +/* + * Return the core mmu_idx to use for A64 "unprivileged load/store" insns + */ +static int get_a64_user_mem_index(DisasContext *s) { - /* Return the core mmu_idx to use for A64 "unprivileged load/store" in= sns: - * if EL1, access as if EL0; otherwise access at current EL + /* + * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, + * which is the usual mmu_idx for this cpu state. */ - ARMMMUIdx useridx; + ARMMMUIdx useridx =3D s->mmu_idx; =20 - switch (s->mmu_idx) { - case ARMMMUIdx_EL10_1: - useridx =3D ARMMMUIdx_EL10_0; - break; - case ARMMMUIdx_SE1: - useridx =3D ARMMMUIdx_SE0; - break; - case ARMMMUIdx_Stage2: - g_assert_not_reached(); - default: - useridx =3D s->mmu_idx; - break; + if (s->unpriv) { + /* + * We have pre-computed the condition for AccType_UNPRIV. + * Therefore we should never get here with a mmu_idx for + * which we do not know the corresponding user mmu_idx. + */ + switch (useridx) { + case ARMMMUIdx_EL10_1: + useridx =3D ARMMMUIdx_EL10_0; + break; + case ARMMMUIdx_EL20_2: + useridx =3D ARMMMUIdx_EL20_0; + break; + case ARMMMUIdx_SE1: + useridx =3D ARMMMUIdx_SE0; + break; + default: + g_assert_not_reached(); + } } return arm_to_core_mmu_idx(useridx); } @@ -14169,6 +14180,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->unpriv =3D FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aoqGCvUwZ9zHGUr/7mZ7wYeC4xbBuuKrf6uyPIypdjI=; b=Izp9v5MlBqNtp4jro4gtAVYir3ZfPGQ7CqdwA/DVFQh/A9OCBHyhXS/GkWvIZ6rBq7 3iMrAr3L9Kt8WS8hZlNAT9J2ToCIQp0YRpXezQ1jaZUYD10r29jD9eQr9QX8yjP5cCDD 8+vVHESEjAflzEIs1A+0uncLKA/Zp7PY71j6zraqQmUY7GDmc2elmEJn2QfF0+ycRLED px/jkgc8yN8LINZnwqefUTInLs/kd8yRHExadVXzeWj6ind0APPsVyuLZ7aAo7/Ja73E LfMYd7um6YMHFD3t4Im9IfytlejVGqkSrmI0TNgjogWnD+0Fq/8jiRc/21RHpVq5pm8w qCnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aoqGCvUwZ9zHGUr/7mZ7wYeC4xbBuuKrf6uyPIypdjI=; b=kvttemMCigLS3mOToGv36GUM0HjHWXC5RJzmtaom/iVzkISJc4mN8VjEReUeHGG/57 3UOUcOng2rjB231pHgA0KflihI+Rn8zGCi4yiCDZATPAnN/JmSK0Q5pN1xPiLRxEhg8b 5PSOVO+q8fN6xRTyURAwlr8xlR13HJJIF1bX6y3Ktz5TAq2yEi402v2kt4MLHJRsMNc/ S5/ZM6EQomXG1sswiMOJ/+51ZNwxivp7XYQHV+pF1Lnul0Yn4z9mSNUuQgDy/YpTDh2g jgBCGoKS0vm3cTxf0ZeAAw/qCXvFaLA5GnwiYpMle5z/b50sTG8c364YAlyOD1I9Xf6r Y1XQ== X-Gm-Message-State: APjAAAWk4o9sKzQTZa1wuAicMgMdFt5maFuIPxcaXe3hlFoeWu6tFgzp V+0Dg4YyngmmcTC1WiK7uUPFE/2Nnyk= X-Google-Smtp-Source: APXvYqxDv/43y80Y2xLYUJ9y+W9is+dy3GkSYsuaLDDW1yvFQFQ1cQdzf/vKCHB1WxBl+LcMlkHf/Q== X-Received: by 2002:a62:1b4b:: with SMTP id b72mr2330826pfb.96.1575340224106; Mon, 02 Dec 2019 18:30:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 35/40] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE Date: Mon, 2 Dec 2019 18:29:32 -0800 Message-Id: <20191203022937.1474-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When VHE is enabled, we need to take the aa32-ness of EL0 from PSTATE not HCR_EL2, which is controlling EL1. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f2d18bd51a..f3785d5ad6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8887,14 +8887,19 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; + uint64_t hcr; =20 switch (new_el) { case 3: is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; break; case 2: - is_aa64 =3D (env->cp15.hcr_el2 & HCR_RW) !=3D 0; - break; + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { + is_aa64 =3D (hcr & HCR_RW) !=3D 0; + break; + } + /* fall through */ case 1: is_aa64 =3D is_a64(env); break; --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575342157; cv=none; d=zohomail.com; s=zohoarc; b=gVEs/DPFRlUKfBwyacvXV4+ftdROquFvHW5n1RESp4kjLIrZFEBq36Q3uJPb2Kd2SbecSID/rwAcMmg8Z+NJG3sHlCN6R76rew/PnWHYkPXBn1IEn6BV9TdMQ9VzyNxjUEpraJNYy7WeaJ/03YDqgVH1HphuaNuN7M/bWxPc6Tc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575342157; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=3c60ktEl3s3vBDW/ij/gteS+EMK9NFSQnhLEWy6Sa+A=; b=cTJFMg8Aa1xu1+Qv1hh9Xnrt0QOsbsJLBgiGl25R9k/eU5Fr7UTtuJnIijT5He475yMA/FFrx2430gPwGYA042JNumZkFp8lg4MfQ2rRLEBQsrjhJ6RijDHFaPK5WYUp+jIAZnimXjbOT+Wo59hEzVRmp0MtE+YAKxt8uNZTauc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575342157332873.4038793044767; Mon, 2 Dec 2019 19:02:37 -0800 (PST) Received: from localhost ([::1]:47708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibySR-0000ju-Vl for importer@patchew.org; Mon, 02 Dec 2019 22:02:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33253) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxM-0003Qv-Hu for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxL-0000GY-1y for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:28 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:45826) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxK-0000Cv-IA for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:26 -0500 Received: by mail-pl1-x641.google.com with SMTP id w7so992214plz.12 for ; Mon, 02 Dec 2019 18:30:26 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3c60ktEl3s3vBDW/ij/gteS+EMK9NFSQnhLEWy6Sa+A=; b=xwJSYtg7ghWqJkUl99jAmmryJoYfdZDMdlUz/3qeJx0rvBwCJIezVRtf3TAhcE5grw byA75eLZqwV4RJoybbrMHvt0jw4QyjDuFTHnwQxe3yAgJtcvTtImif/vKXrc2bmuldi2 DXJkC1yIvdoA/TmWte8yvREsLr2FoH1F9+Mt8KLKHp36qti8WD3zPhQhxOM6EAQ46tGy gs6S3LCrCyDn8ofw6XP/RixLXmoQS7J09SufysSjYOLei1gm4v2sNvFRmAY31ZfHQTYo V5ZKMKN96KFH/yGcaKEAkL+GWC6xFH5MpFzh5mnY84QNG/jSbtUYeqty6txAPM+K6hqI k4vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3c60ktEl3s3vBDW/ij/gteS+EMK9NFSQnhLEWy6Sa+A=; b=jv5BECKcrYtiuT46FFqwlBR5kNsP7vp6GIQBke5nLR3fn0TGIOPx73atcGE0II5PDs wUqbTpS0WcT07x3pmPb6RwuO7CaxV6pQ3gacy56gPadco+sNUJNVfTjB41TYyxt/uUsI ByQ5ONcYGaVzL3SzQ8igmE37hSjkJG3SDFpaZO8mdCQGxS2hMZMxtnWtNedaCvFs+vjq MMlqQ8VmFWu4+1DANMVJ1ZqZo6yScyNdyw3WFBGP9QfsGXQlrDT45ldaUFcbydPRK9HB glfxmiolDxu6j3BQvulY1yiuzBJVCic+RYv/jLcDAEUtQHRkiOHLrmWdn526GdRZBlf5 KaDA== X-Gm-Message-State: APjAAAUm9ZYvI3b1icMJ/v42qTFK2WkN3BWaIknLz+WrbXAgZSB4wwWq 1r/gsU5Mu5sy6j/wZSwesAiAV2kJYEI= X-Google-Smtp-Source: APXvYqx0LOqQ2MZTM78Jrt45jxrxec+CwkT+OWAs6/Ni1vs+uqHQSV8JcrO537uQnFMbwudkLH08YA== X-Received: by 2002:a17:90a:ff04:: with SMTP id ce4mr2849310pjb.133.1575340225196; Mon, 02 Dec 2019 18:30:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max Date: Mon, 2 Dec 2019 18:29:33 -0800 Message-Id: <20191203022937.1474-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a39d6fcea3..009411813f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -670,6 +670,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr1; t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); cpu->isar.id_aa64mmfr1 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341974; cv=none; d=zohomail.com; s=zohoarc; b=jNdyeQrTOoK1OQmOudy3jc4uCjUGeMsV8YxcVshkW07DtgpbdiVo3ggYCPDVuyLvrroA/JDXEe2xaQFQ+UVaS76Enj/SFHw00I9W3LqNsxUh3g9C6M2IOw9DZ989rU8bFSHPjEQ3OJk0cLjZsi0I1x/BJ59FmC0F3+a35vfkzv0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341974; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=sU0Rb1lweTCsZgkiKPPPp7WxJ75dP/BQ8w48fi8QJ6s=; b=kHcuSYWslVreQuPpgFobux1wJiOKiSR+01UUJshT7jaxZZlZXmbFNXj+wGDxZK9S+sgaVAQAuCSjdsrJUCKLCl8PddrxNG5r4XXoAporuLp3wThdXgL1PTv8Aqt3h3emZeU1YVqJ/utKYVRRIlwYDvKCi+LNDosne+5WEqkcOh8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341974691604.9570312660561; Mon, 2 Dec 2019 18:59:34 -0800 (PST) Received: from localhost ([::1]:47648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyPU-0005hD-VM for importer@patchew.org; Mon, 02 Dec 2019 21:59:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33540) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxO-0003TB-Ep for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxM-0000Jx-6w for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:30 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:33918) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxL-0000Hc-Sy for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:28 -0500 Received: by mail-pj1-x1041.google.com with SMTP id t21so831245pjq.1 for ; Mon, 02 Dec 2019 18:30:27 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sU0Rb1lweTCsZgkiKPPPp7WxJ75dP/BQ8w48fi8QJ6s=; b=VjMegFqGhdkDDr/jf5XYiM6AO3uJlzF/RNLX2MBF9ayrUBfokmOe8PsPvjtXrbNZek KMiXIn5PqeXUUIIfrXu26FY7OdREj9YixejxPkqfeySig29JgOzZFRY2AkCDERstF8Ff vBerH6agj75tGYsNRCmUikGU5iwA4YOh/CUbNvHM18G1NpZ70iizWRaVkWKV18GwkCvN xDo/stGWabLvqCTNVXTLP664PJyX1iw4Efu7sm+XFKo2Yvho1TGRlPEkkMEiqhwgfbae TpdXXu4ozl7w6/5XcAUaaJG0qSq48aeGlgF2SqfserpgiKzPKoIEQf/qEINJq1J451N9 funw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sU0Rb1lweTCsZgkiKPPPp7WxJ75dP/BQ8w48fi8QJ6s=; b=gkxx+SUV18fZc4Yq0EboMwyfnUPsx/k0vc0FjRCHROkuxGu5Uq8cwpfdy7X61buu76 GJt3BhzXyBTbntGm9UuUs4iUjrfQ5eZGbdqJyPvbyLddOXwzyDI85RayJP91bZTrFhRH b1tcjvOagbTaRfEweMlda/dKW0EAeNECS/jvoIHmsGSa16hFkmrI/w1UGHAnkUDrjujW Tpyy93dQAmWB6C8d0kHbxp7SK4P9cNT/Oz+MUVF8sl5N1Otvqhmu1SdMT2M9yaZl1Irt 0q1wb6CC08XDNnWCT0TnFLIWhTorGsnlpyYhn1uXkRT5pJaUxSy1glw8Ff7Rr4x8MtU4 NUCg== X-Gm-Message-State: APjAAAWDHZ8CEFGAFV6Q4KIX6jKgL2fB8VWw9lZPZFC0XnzqQ7sCNSrb LiR3b/D0NtXJWKGM4EefzyNK7ws9sJI= X-Google-Smtp-Source: APXvYqxonvO1uGtm9VZPR2N2CPU4tZR/Om6po8cRD+iMM+CVYbnA1eLMDXWkjrgwi68CAVWYguPdxQ== X-Received: by 2002:a17:902:758a:: with SMTP id j10mr2751609pll.29.1575340226370; Mon, 02 Dec 2019 18:30:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 37/40] target/arm: Move arm_excp_unmasked to cpu.c Date: Mon, 2 Dec 2019 18:29:34 -0800 Message-Id: <20191203022937.1474-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This inline function has one user in cpu.c, and need not be exposed otherwise. Code movement only, with fixups for checkpatch. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 111 ------------------------------------------- target/arm/cpu.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 111 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e5aaaf415..22935e4433 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2673,117 +2673,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 =20 -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el) -{ - CPUARMState *env =3D cs->env_ptr; - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - bool pstate_unmasked; - int8_t unmasked =3D 0; - uint64_t hcr_el2; - - /* Don't take exceptions if they target a lower EL. - * This check should catch any exceptions that would not be taken but = left - * pending. - */ - if (cur_el > target_el) { - return false; - } - - hcr_el2 =3D arm_hcr_el2_eff(env); - - switch (excp_idx) { - case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); - break; - - case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); - break; - - case EXCP_VFIQ: - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized and non-secure. */ - return false; - } - return !(env->daif & PSTATE_F); - case EXCP_VIRQ: - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized and non-secure. */ - return false; - } - return !(env->daif & PSTATE_I); - default: - g_assert_not_reached(); - } - - /* Use the target EL, current execution state and SCR/HCR settings to - * determine whether the corresponding CPSR bit is used to mask the - * interrupt. - */ - if ((target_el > cur_el) && (target_el !=3D 1)) { - /* Exceptions targeting a higher EL may not be maskable */ - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* 64-bit masking rules are simple: exceptions to EL3 - * can't be masked, and exceptions to EL2 can only be - * masked from Secure state. The HCR and SCR settings - * don't affect the masking logic, only the interrupt routing. - */ - if (target_el =3D=3D 3 || !secure) { - unmasked =3D 1; - } - } else { - /* The old 32-bit-only environment has a more complicated - * masking setup. HCR and SCR bits not only affect interrupt - * routing but also change the behaviour of masking. - */ - bool hcr, scr; - - switch (excp_idx) { - case EXCP_FIQ: - /* If FIQs are routed to EL3 or EL2 then there are cases w= here - * we override the CPSR.F in determining if the exception = is - * masked or not. If neither of these are set then we fall= back - * to the CPSR.F setting otherwise we further assess the s= tate - * below. - */ - hcr =3D hcr_el2 & HCR_FMO; - scr =3D (env->cp15.scr_el3 & SCR_FIQ); - - /* When EL3 is 32-bit, the SCR.FW bit controls whether the - * CPSR.F bit masks FIQ interrupts when taken in non-secure - * state. If SCR.FW is set then FIQs can be masked by CPSR= .F - * when non-secure but only when FIQs are only routed to E= L3. - */ - scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); - break; - case EXCP_IRQ: - /* When EL3 execution state is 32-bit, if HCR.IMO is set t= hen - * we may override the CPSR.I masking when in non-secure s= tate. - * The SCR.IRQ setting has already been taken into conside= ration - * when setting the target EL, so it does not have a furth= er - * affect here. - */ - hcr =3D hcr_el2 & HCR_IMO; - scr =3D false; - break; - default: - g_assert_not_reached(); - } - - if ((scr || hcr) && !secure) { - unmasked =3D 1; - } - } - } - - /* The PSTATE bits only mask the interrupt if we have not overriden the - * ability above. - */ - return unmasked || pstate_unmasked; -} - #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 81c33221f7..a36344d4c7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -410,6 +410,125 @@ static void arm_cpu_reset(CPUState *s) arm_rebuild_hflags(env); } =20 +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, + unsigned int target_el) +{ + CPUARMState *env =3D cs->env_ptr; + unsigned int cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + bool pstate_unmasked; + int8_t unmasked =3D 0; + uint64_t hcr_el2; + + /* + * Don't take exceptions if they target a lower EL. + * This check should catch any exceptions that would not be taken + * but left pending. + */ + if (cur_el > target_el) { + return false; + } + + hcr_el2 =3D arm_hcr_el2_eff(env); + + switch (excp_idx) { + case EXCP_FIQ: + pstate_unmasked =3D !(env->daif & PSTATE_F); + break; + + case EXCP_IRQ: + pstate_unmasked =3D !(env->daif & PSTATE_I); + break; + + case EXCP_VFIQ: + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_I); + default: + g_assert_not_reached(); + } + + /* + * Use the target EL, current execution state and SCR/HCR settings to + * determine whether the corresponding CPSR bit is used to mask the + * interrupt. + */ + if ((target_el > cur_el) && (target_el !=3D 1)) { + /* Exceptions targeting a higher EL may not be maskable */ + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * 64-bit masking rules are simple: exceptions to EL3 + * can't be masked, and exceptions to EL2 can only be + * masked from Secure state. The HCR and SCR settings + * don't affect the masking logic, only the interrupt routing. + */ + if (target_el =3D=3D 3 || !secure) { + unmasked =3D 1; + } + } else { + /* + * The old 32-bit-only environment has a more complicated + * masking setup. HCR and SCR bits not only affect interrupt + * routing but also change the behaviour of masking. + */ + bool hcr, scr; + + switch (excp_idx) { + case EXCP_FIQ: + /* + * If FIQs are routed to EL3 or EL2 then there are cases w= here + * we override the CPSR.F in determining if the exception = is + * masked or not. If neither of these are set then we fall= back + * to the CPSR.F setting otherwise we further assess the s= tate + * below. + */ + hcr =3D hcr_el2 & HCR_FMO; + scr =3D (env->cp15.scr_el3 & SCR_FIQ); + + /* + * When EL3 is 32-bit, the SCR.FW bit controls whether the + * CPSR.F bit masks FIQ interrupts when taken in non-secure + * state. If SCR.FW is set then FIQs can be masked by CPSR= .F + * when non-secure but only when FIQs are only routed to E= L3. + */ + scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); + break; + case EXCP_IRQ: + /* + * When EL3 execution state is 32-bit, if HCR.IMO is set t= hen + * we may override the CPSR.I masking when in non-secure s= tate. + * The SCR.IRQ setting has already been taken into conside= ration + * when setting the target EL, so it does not have a furth= er + * affect here. + */ + hcr =3D hcr_el2 & HCR_IMO; + scr =3D false; + break; + default: + g_assert_not_reached(); + } + + if ((scr || hcr) && !secure) { + unmasked =3D 1; + } + } + } + + /* + * The PSTATE bits only mask the interrupt if we have not overriden the + * ability above. + */ + return unmasked || pstate_unmasked; +} + bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575341657; cv=none; d=zohomail.com; s=zohoarc; b=ib7feJcjv7z14GRS1LHWolGGmscMmgmu0SMWhAV0qkNuptvmfF/f8WZmmNLQqyOgkf/8hllRNB+Mf1Igh5l5Fpn2W8126iPO0aUMuOdFT5ldYEADpk75SCbW5Z7G0wANhi4jnYK7jizkKwDFCx5VSkN1+3wfjWk0AolV+nVpV2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575341657; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=k0XWWezVOhFzaYm0qz5tHBxEXRK+lD5naHKLwWqhpHI=; b=XcHSkDJMVbEAFBWbDsjkI8jd4zG4dp9RnVsEF5jRuVGUJQ5uvi9vRxIAFrt7gGChWwddsDwfWwVWtxz3bPpogKrq5GvzHP1bIRZeJrqDk7A7niyPMSMvNaZrKQSnArApirT9QqyadGSfPXomCUtV619QQLLZKBk5lL7lu329isk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575341657204235.88971945714866; Mon, 2 Dec 2019 18:54:17 -0800 (PST) Received: from localhost ([::1]:47538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyKN-0006h9-Ct for importer@patchew.org; Mon, 02 Dec 2019 21:54:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33627) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxO-0003UC-Og for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxN-0000N1-Eq for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:30 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:34584) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxN-0000KX-2K for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:29 -0500 Received: by mail-pl1-x643.google.com with SMTP id h13so1014551plr.1 for ; Mon, 02 Dec 2019 18:30:28 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k0XWWezVOhFzaYm0qz5tHBxEXRK+lD5naHKLwWqhpHI=; b=aiqfWNARXyYW1/8OallmGR59GeT1kMy70QH+mVXvlf6z3mxGUsjV/0NFlv8LehWnGM 60PbnV+bpa23kpyBRPu1apbnhzVsCXluJZXGNE0mdLrI15gP8sJHW+AnECa1ZqfUnU4c kJYjotMwAruV4yacXRCnrnTDLQPj/TQunGi5yaeMwuf/EXleaIXN+SD7e4JgHZEPaTlF 6RK24uwym9UVLGXS2WIAnyb/Kc6vWCsk0ApMGA+a+vkYLBxm5ERzIfbD1jdhp6/POVat kcIwbGrfHV2ZUbI/Jao5JX0/bbvdqobwFvgRBkIJAvsDcwAFK4Yx2K85lW/iYll/wBg0 SjQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k0XWWezVOhFzaYm0qz5tHBxEXRK+lD5naHKLwWqhpHI=; b=YM3M6hhjkl3XfzJRvCr/UUnD28LTdNDIuOvWWUidDBTtPiy//jsjZAazOjpblugQJL L7Nw/JQ3MU5BZuOG7HeLo08WsI2DtJ+Ey1nkOQGZ4ZTF5UjnbCeZA/dGNZnmRnbMmclo EJGF4PqAzPvJmo+AQ06YlTDc5nFzDdgIC82idQInovypbkhfSML91qU9scHYgBePXCo0 pcp4M4rC5yBGxAqiUmq1CbZQMhRzWJ4CKk6XRoXyCWJJvkEivZ0yM2N6en2+HAQKWyPD BIBHwJXfJ1iKhsYRpxELSl75k0FE8Kvt/Mbo3pW1bMzbvupSHBDSXAAV4e3jbY/eNTcW R9CA== X-Gm-Message-State: APjAAAWQyNY+XobMjnTsUoLbxey+MyqeNgmrN/un/iIEups/8ffXORMe fPx5gZOSoJE1RaPtV4lZVDNBDsmI+nQ= X-Google-Smtp-Source: APXvYqxe7OPYGL9jUAmy+H8UzhHfvbqMiUL2MZtjGC1DbPgBF/JOmSHDVWSZ9/F8AJSd3mVGaRBCCA== X-Received: by 2002:a17:902:43:: with SMTP id 61mr2772112pla.88.1575340227615; Mon, 02 Dec 2019 18:30:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 38/40] target/arm: Pass more cpu state to arm_excp_unmasked Date: Mon, 2 Dec 2019 18:29:35 -0800 Message-Id: <20191203022937.1474-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a36344d4c7..7a1177b883 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s) } =20 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el) + unsigned int target_el, + unsigned int cur_el, bool secure, + uint64_t hcr_el2) { CPUARMState *env =3D cs->env_ptr; - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); bool pstate_unmasked; int8_t unmasked =3D 0; - uint64_t hcr_el2; =20 /* * Don't take exceptions if they target a lower EL. @@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return false; } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); - switch (excp_idx) { case EXCP_FIQ: pstate_unmasked =3D !(env->daif & PSTATE_F); @@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) CPUARMState *env =3D cs->env_ptr; uint32_t cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint32_t target_el; uint32_t excp_idx; bool ret =3D false; @@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_HARD) { excp_idx =3D EXCP_IRQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VIRQ) { excp_idx =3D EXCP_VIRQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VFIQ) { excp_idx =3D EXCP_VFIQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u63gqALS75nKLyBBgFxH9YCXnhD2J6j4ZQ6v9GcNUx4=; b=QKRfFCH/7LRf3OLHS7U5cg6JJEOvd1qGoiwEkrkNI6YXjyjGHVfKasmnCbzuPF2/Vl I28BdiB53bjLj2f6vDrPQprcP3zOG8V7kuAkKer/ohY8cZQXgy8kj5jNQsdGnvdueiS1 Y9bF7x+j3uPw+meszc9eNR8/rAJZ/5zlCd9UhnyXvesRs/xrgrl4T6A4zfacCrz9Eexa dFhrm7667UgAfyHZOxY/d7cTRvvSwG1itiSs3HfRkzxaICaNTxuRmI7tt8lbwkucMtGR 2cvom6roIPoq4sLv6P+bTa+mdwN2cFRfdTfMvdxCsB9Kd8CbQwkekqYJ0zZgD3Pl8V5l UKEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u63gqALS75nKLyBBgFxH9YCXnhD2J6j4ZQ6v9GcNUx4=; b=CAQqDWOVCCNcrYxPWbtz0nNWamgpycguqLt6UOsAkyQMTIkiFHujFKcQrTBSFQgwUp ybVQ/Ts6Re94fKCaaIb5SJsavWzDMGkUTTLWCmsMcUtVhoyGqm+CcCtENpKQPntKUAgH tuplujUpQP69n7hI9DV4xakzqd8Or/1Pg/VVedz6t4NdcL4t6C7Re8ksEeyTEroHaglY iRJqCrIAmADTPYctd0so2n/GPi311fJeu1BH9dZPndA41+++xbiaAPjo94ztV/yAW2+h fmYNsyCfyry2uSPFjWuiGRD07OdEJVe9SKMEjCrVxAMuAcFdtL5v5nOUEgjrnSAwJhN1 G9kg== X-Gm-Message-State: APjAAAXAfcPSv6Stvl5ILe4EDLnZTZMWzB99daLcf4Qshb4N+sjb7sWC w9gu3NgmGBLz4WuxgwHIMIA2dcIybvI= X-Google-Smtp-Source: APXvYqyOFHAwJN2L1PYdxXcavKM4QpKVPJ0O8oQ4jqkkKKGvyzdxpRj52dXpSXfIdATSV6OygMJgqQ== X-Received: by 2002:a17:90b:3007:: with SMTP id hg7mr2964339pjb.73.1575340228735; Mon, 02 Dec 2019 18:30:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 39/40] target/arm: Use bool for unmasked in arm_excp_unmasked Date: Mon, 2 Dec 2019 18:29:36 -0800 Message-Id: <20191203022937.1474-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The value computed is fully boolean; using int8_t is odd. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a1177b883..a366448c6d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -417,7 +417,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, { CPUARMState *env =3D cs->env_ptr; bool pstate_unmasked; - int8_t unmasked =3D 0; + bool unmasked =3D false; =20 /* * Don't take exceptions if they target a lower EL. @@ -468,7 +468,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, * don't affect the masking logic, only the interrupt routing. */ if (target_el =3D=3D 3 || !secure) { - unmasked =3D 1; + unmasked =3D true; } } else { /* @@ -514,7 +514,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, } =20 if ((scr || hcr) && !secure) { - unmasked =3D 1; + unmasked =3D true; } } } --=20 2.17.1 From nobody Wed Nov 12 23:10:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1575342113; cv=none; d=zohomail.com; s=zohoarc; b=WCqFqOOdEjnPRK4EjXwFfiKQf82g6oq7FVSNwscP7HI+eqMMQSgVFAoxK0rqFY+TrnCBiWZaes6+kEzXt0i6Fq2nMtN1W714FJFKTa4ldxluTwwN2+lnhB5ihtI+ZWGDXILWAm6igflHAeveSplWDmz7VbF4jG5B94tSN/hfWtw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575342113; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=s9VJVdTUiMlwkcjgw0/3sV/2Ka0DCPLGSdMwx4oTNII=; b=eNgND+z7YCE6D2ooU4+Ru4TJuls3YiDhxX/LGhKZOzp8aO2d3LmX2FPB6QAVpTNAtY9fnKEuvs0voqmkF0oRFYnFT0bxLTIHZlbBXMLB3PMMGkvKx6OEMeCUXou6AfqxBJAHH1JL0doIXaPKWgP712tXmesblR5SfK6tsy8sMHI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575342113362880.3917446615241; Mon, 2 Dec 2019 19:01:53 -0800 (PST) Received: from localhost ([::1]:47700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibyRk-0008Ou-3k for importer@patchew.org; Mon, 02 Dec 2019 22:01:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33955) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxxQ-0003Xi-Og for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxxP-0000Tm-98 for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:32 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:35715) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxxO-0000RW-WB for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:31 -0500 Received: by mail-pj1-x1041.google.com with SMTP id s8so829838pji.2 for ; Mon, 02 Dec 2019 18:30:30 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:30:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s9VJVdTUiMlwkcjgw0/3sV/2Ka0DCPLGSdMwx4oTNII=; b=V0p4GsWs+jcwUzHv4bb8Yz8DP1b1lGHslfoJocTsXr/CU50SNzcn8TLxMED8zLq4f6 NfHYTW2woNYsEBhvG3M8+ORu6M4WHsEANzTO+na5PgxHVxK+J8Ooi9V2FUkar/0bXpGu ePLgeZFcNVmYlzHzS6D5jmB2dpcL2tIDu/CfdWPcVb6t3VgPHxCtAqArpAI0AnqRaVsn hFSvcJDIT4OFCvxi8MccdMN4ggBXA1pGlC9gadXU1AAJi2YXQpWmKKKQxba1qXSNccjq wx+mwSp/SJ11kgkdHYf18amU6pRQHrhMidLmFelF1PZqMfinxDDObaN32daBrHO+KoPm sY8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s9VJVdTUiMlwkcjgw0/3sV/2Ka0DCPLGSdMwx4oTNII=; b=o3YZCCXS6CwEOqlxQlR3pKqPAXgpHR3teKZV1YTirJUBm1vqpgV3a/6aOlu6n9Yp5A Vjhi/DUP0ucFBFcOElE1ODKc/4zAR2c7QB55J0ex4NZYBLOrly0wYawtNKh1TYO7Gn2R PMOa/1H8aJpTlgCf5GVUR3AvdjsH/RIrCZ9K6zKjEQm7ytTIfYQn2qCwzaCLMa3HKD5k sqUzoSoruX69cPQGQihGsD+5zhWDqHjkbeff5mgOO13Rj4MXWTPW0lbhO4Lq1yrF29C/ iKQGkPxw/bf5O5yLY1TUopL4K6ZSncQzjc+aEhiP8+xdckTMaU0PBm+OMuuQj20kgzaz EMrA== X-Gm-Message-State: APjAAAVXshOVe9j/zHNH87fUXFnsE7kIR7BS7+4OZz61X9BUi2DlT07F w4csgUUdk5nBwQpqhdr2TywNW8uGoKI= X-Google-Smtp-Source: APXvYqwxAzSk+ImtzKahchUNa86+ODx4shdMYeOyuP00FOkVu4R7Q/jJIjV0YNof1d8ZzwpGEf3Rnw== X-Received: by 2002:a17:902:142:: with SMTP id 60mr2767564plb.38.1575340229666; Mon, 02 Dec 2019 18:30:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 40/40] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Date: Mon, 2 Dec 2019 18:29:37 -0800 Message-Id: <20191203022937.1474-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The fall through organization of this function meant that we would raise an interrupt, then might overwrite that with another. Since interrupt prioritization is IMPLEMENTATION DEFINED, we can recognize these in any order we choose. Unify the code to raise the interrupt in a block at the end. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a366448c6d..f3360dbb98 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -535,17 +535,15 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint32_t target_el; uint32_t excp_idx; - bool ret =3D false; + + /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ =20 if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -553,10 +551,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } if (interrupt_request & CPU_INTERRUPT_VIRQ) { @@ -564,10 +559,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) target_el =3D 1; if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } if (interrupt_request & CPU_INTERRUPT_VFIQ) { @@ -575,14 +567,16 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) target_el =3D 1; if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } + return false; =20 - return ret; + found: + cs->exception_index =3D excp_idx; + env->exception.target_el =3D target_el; + cc->do_interrupt(cs); + return true; } =20 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) --=20 2.17.1