From nobody Thu Nov 13 00:36:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1575203226; cv=none; d=zohomail.com; s=zohoarc; b=L7uR2/+FNOp9Cbl5KXYYskEOR0a4/ZDkkLOcP62j/BeqSDYGKRjZkjQ1VtOusCmbsCjrghLBj8yhF+Kg9JiS0y04NRgakCTGzMH8tvtQ587znn7IYWKBsDUnU/kN3/yycc5Ot4/2hm7sjWrZAbDsXx+c63JJAqKWUOFWcY5nsME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575203226; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2OfYsmgaVMZiesx+7JXviMirM37Qf6aqyU/OJ0cN/3M=; b=aDeb+HbyJtEZxK1KqZMWaS7HmJfFhjGpK1TgtcYwqzM422O2iz187td6ndpfuazH/zv8ieeEtt35tR4tZbS1nXJt3yggQ+zdFAiSCOC0DzKFNT3irxFZvWqMEYiXcS0DzxFgFlOttAjIxuSQXyC+6IU6ymKEZ+vKH+G9Ue5MShA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575203226320562.5083925806297; Sun, 1 Dec 2019 04:27:06 -0800 (PST) Received: from localhost ([::1]:50888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibOJd-0000VX-9F for importer@patchew.org; Sun, 01 Dec 2019 07:27:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43659) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibODi-0002CK-Ur for qemu-devel@nongnu.org; Sun, 01 Dec 2019 07:21:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibODg-0002yM-3B for qemu-devel@nongnu.org; Sun, 01 Dec 2019 07:20:58 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:40556) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibODf-0002vN-SG for qemu-devel@nongnu.org; Sun, 01 Dec 2019 07:20:56 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1ibODX-0007WK-2B; Sun, 01 Dec 2019 13:20:47 +0100 From: Marc Zyngier To: qemu-devel@nongnu.org Subject: [PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 trapping requirements Date: Sun, 1 Dec 2019 12:20:15 +0000 Message-Id: <20191201122018.25808-3-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191201122018.25808-1-maz@kernel.org> References: <20191201122018.25808-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org, richard.henderson@linaro.org, edgar.iglesias@xilinx.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Peter Maydell , Richard Henderson , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1 (and their 32bit equivalents) as well as TCMTR, TLBTR are trapped to EL2. QEMU ignores it, making it harder for a hypervisor to virtualize the HW (though to be fair, no known hypervisor actually cares). Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set. Reviewed-by: Edgar E. Iglesias Signed-off-by: Marc Zyngier Reviewed-by: Richard Henderson --- target/arm/helper.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e546096b8..93ecab27c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1973,6 +1973,26 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) return ret; } =20 +static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID1))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + return access_aa64_tid1(env, ri, isread); + } + + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, @@ -2136,7 +2156,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { */ { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid1, + .resetvalue =3D 0 }, /* Auxiliary fault status registers: these also are IMPDEF, and we * choose to RAZ/WI for all cores. */ @@ -6732,7 +6754,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { @@ -6748,14 +6772,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ { .name =3D "TCMTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + .access =3D PL1_R, + .accessfn =3D access_aa32_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, REGINFO_SENTINEL }; /* TLBTR is specific to VMSA */ ARMCPRegInfo id_tlbtr_reginfo =3D { .name =3D "TLBTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .access =3D PL1_R, + .accessfn =3D access_aa32_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D 0, }; /* MPUIR is specific to PMSA V6+ */ ARMCPRegInfo id_mpuir_reginfo =3D { --=20 2.20.1