From nobody Thu Nov 13 00:36:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1575202981; cv=none; d=zohomail.com; s=zohoarc; b=gD5eiZJkepXX0IGVp59HNAYbnS/ESUGL2KEhAgX1GBMdjtc/Mv/TcW3kubgiVvCgl6jGLt19/aGSXP0+uYx0lxop2/VFqhlC0qs8YhxhatbWzkuPx2rwUj5gy7kkUxlL+UlBjwoZzx3pp3oD+jIcGjBMYytnOXqKig9gGwY4RwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575202981; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a64rOqRfgMEDjkii8tRLcCNliRrn7b81YSYDrcDb6Jg=; b=G8ugqcUmpuhx0PrNcOEWEQXbKtxYrz3Yv2/B58eJkiOPW4GK0I//lGTIgspP/GGnOjaXBZkTLrV6Wy4WGulghb2vkjumfgf3hZyDBx4nftHDBbG7emm1wv3JpxZaB+lj7HdUbSdI3UI7upBzsoO3NosVTDnLPPWlec6qMIJllR4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575202981464227.55039365075834; Sun, 1 Dec 2019 04:23:01 -0800 (PST) Received: from localhost ([::1]:50838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibOFg-0004A6-0g for importer@patchew.org; Sun, 01 Dec 2019 07:23:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43657) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibODi-0002CJ-UO for qemu-devel@nongnu.org; Sun, 01 Dec 2019 07:21:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibODf-0002y6-VH for qemu-devel@nongnu.org; Sun, 01 Dec 2019 07:20:58 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:49406) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ibODf-0002vO-HE for qemu-devel@nongnu.org; Sun, 01 Dec 2019 07:20:55 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1ibODW-0007WK-JM; Sun, 01 Dec 2019 13:20:46 +0100 From: Marc Zyngier To: qemu-devel@nongnu.org Subject: [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Date: Sun, 1 Dec 2019 12:20:14 +0000 Message-Id: <20191201122018.25808-2-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191201122018.25808-1-maz@kernel.org> References: <20191201122018.25808-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org, richard.henderson@linaro.org, edgar.iglesias@xilinx.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Peter Maydell , Richard Henderson , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU completely ignores it, making it impossible for hypervisors to virtualize the cache hierarchy. Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set. Signed-off-by: Marc Zyngier Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/arm/helper.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b..1e546096b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1910,6 +1910,17 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) raw_write(env, ri, value); } =20 +static CPAccessResult access_aa64_tid2(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID2))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); @@ -2110,10 +2121,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmintenclr_write }, { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, - .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW = }, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid2, + .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D csselr_write, .resetvalue =3D 0, + .access =3D PL1_RW, + .accessfn =3D access_aa64_tid2, + .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now @@ -5204,6 +5219,11 @@ static CPAccessResult ctr_el0_access(CPUARMState *en= v, const ARMCPRegInfo *ri, if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { return CP_ACCESS_TRAP; } + + if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; } =20 @@ -6184,7 +6204,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu= ->clidr + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid2, + .resetvalue =3D cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); @@ -6717,7 +6739,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* These are common to v8 and pre-v8 */ { .name =3D "CTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->ctr }, + .access =3D PL1_R, .accessfn =3D ctr_el0_access, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, .access =3D PL0_R, .accessfn =3D ctr_el0_access, --=20 2.20.1