From nobody Fri Apr 26 13:34:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1574963789; cv=none; d=zohomail.com; s=zohoarc; b=QHuoGoomnfM03FqiFfzSMfY2tAZSS79a79fisH5p5H6fpA+RvuXH3D+L0Z1B2rGhSjLAR3ti8SwhO60aJ0DEjtUPlhox5PUE2eoo475YdUSg7ywqIYgh1lLttI7l/8Z1qJVbC84ZoyHyUSrDuLN5F/AGseouF0RTzqQQ2ivle8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574963789; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M7mrOb0O6x0EnASu+HSYdKhFaU812GJWljrvMXdFfxY=; b=WHdVy8/01SwUus7jY8RhzUkTL6Czl+Paw+087gveD5LXCmeMxZrmraoUngeZC0sPxDx48yN8R8QhdEhtP8520PR+OlYYS6Xsg7akaq64+uXplBk/uBcbpX8fcjK+xNqMN2+Qj+HcsPDprq+cxDxbGZV0pZKn6wNnHOOHHY5Ko1g= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574963789251389.6120760120458; Thu, 28 Nov 2019 09:56:29 -0800 (PST) Received: from localhost ([::1]:51540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iaO1g-0002i4-Do for importer@patchew.org; Thu, 28 Nov 2019 12:56:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57336) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iaMUJ-0000lc-1l for qemu-devel@nongnu.org; Thu, 28 Nov 2019 11:17:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iaMUG-00056n-1N for qemu-devel@nongnu.org; Thu, 28 Nov 2019 11:17:49 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:58025) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iaMUE-0004yY-Ha for qemu-devel@nongnu.org; Thu, 28 Nov 2019 11:17:47 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1iaMU2-0002vd-SP; Thu, 28 Nov 2019 17:17:35 +0100 From: Marc Zyngier To: qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Honor HCR_EL2.TID2 trapping requirements Date: Thu, 28 Nov 2019 16:17:16 +0000 Message-Id: <20191128161718.24361-2-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191128161718.24361-1-maz@kernel.org> References: <20191128161718.24361-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org, richard.henderson@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , richard.henderson@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU completely ignores it, making impossible for hypervisors to virtualize the cache hierarchy. Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set. Signed-off-by: Marc Zyngier --- target/arm/helper.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b..0b6887b100 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1910,6 +1910,17 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) raw_write(env, ri, value); } =20 +static CPAccessResult access_aa64_tid2(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID2))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); @@ -2110,10 +2121,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmintenclr_write }, { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, - .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW = }, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid2, + .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D csselr_write, .resetvalue =3D 0, + .access =3D PL1_RW, + .accessfn =3D access_aa64_tid2, + .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now @@ -5204,6 +5219,11 @@ static CPAccessResult ctr_el0_access(CPUARMState *en= v, const ARMCPRegInfo *ri, if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { return CP_ACCESS_TRAP; } + + if (arm_hcr_el2_eff(env) & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; } =20 @@ -6184,7 +6204,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu= ->clidr + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid2, + .resetvalue =3D cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); --=20 2.20.1 From nobody Fri Apr 26 13:34:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 28 Nov 2019 11:17:47 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1iaMU3-0002vd-9I; Thu, 28 Nov 2019 17:17:35 +0100 From: Marc Zyngier To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: Honor HCR_EL2.TID1 trapping requirements Date: Thu, 28 Nov 2019 16:17:17 +0000 Message-Id: <20191128161718.24361-3-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191128161718.24361-1-maz@kernel.org> References: <20191128161718.24361-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org, richard.henderson@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , richard.henderson@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1 (and their 32bit equivalents) as well as TCMTR, TLBTR are trapped to EL2. QEMU ignores it, naking it harder for a hypervisor to virtualize the HW (though to be fair, no known hypervisor actually cares). Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set. Signed-off-by: Marc Zyngier Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b6887b100..9bff769692 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1973,6 +1973,26 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) return ret; } =20 +static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_hcr_el2_eff(env) & HCR_TID1) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + return access_aa64_tid1(env, ri, isread); + } + + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, @@ -2136,7 +2156,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { */ { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid1, + .resetvalue =3D 0 }, /* Auxiliary fault status registers: these also are IMPDEF, and we * choose to RAZ/WI for all cores. */ @@ -6732,7 +6754,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { @@ -6747,14 +6771,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ { .name =3D "TCMTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + .access =3D PL1_R, + .accessfn =3D access_aa32_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, REGINFO_SENTINEL }; /* TLBTR is specific to VMSA */ ARMCPRegInfo id_tlbtr_reginfo =3D { .name =3D "TLBTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .access =3D PL1_R, + .accessfn =3D access_aa32_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D 0, }; /* MPUIR is specific to PMSA V6+ */ ARMCPRegInfo id_mpuir_reginfo =3D { --=20 2.20.1 From nobody Fri Apr 26 13:34:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 28 Nov 2019 11:17:47 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1iaMU3-0002vd-Lt; Thu, 28 Nov 2019 17:17:35 +0100 From: Marc Zyngier To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Date: Thu, 28 Nov 2019 16:17:18 +0000 Message-Id: <20191128161718.24361-4-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191128161718.24361-1-maz@kernel.org> References: <20191128161718.24361-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org, richard.henderson@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 213.251.177.50 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , richard.henderson@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to EL2, and that HCR_EL2.TID0 does the same for reads of FPSID. In order to handle this, introduce a new TCG helper function that checks for these control bits before executing the VMRC instruction. Tested with a hacked-up version of KVM/arm64 that sets the control bits for 32bit guests. Signed-off-by: Marc Zyngier Reviewed-by: Edgar E. Iglesias --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/translate-vfp.inc.c | 12 +++++++++--- target/arm/vfp_helper.c | 27 +++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..311ced44e6 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_3(check_hcr_el2_trap, void, env, int, int) diff --git a/target/arm/internals.h b/target/arm/internals.h index f5313dd3d4..5a55e960de 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -430,6 +430,14 @@ static inline uint32_t syn_simd_access_trap(int cv, in= t cond, bool is_16bit) | (cv << 24) | (cond << 20) | (1 << 5); } =20 +static inline uint32_t syn_vmrs_trap(int rt, int reg) +{ + return (EC_FPIDTRAP << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (1 << 24) | (0xe << 20) | (7 << 14) + | (reg << 10) | (rt << 5) | 1; +} + static inline uint32_t syn_sve_access_trap(void) { return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 85c5ef897b..4c435b6c35 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -759,15 +759,21 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR= _VMRS *a) } =20 if (a->l) { + TCGv_i32 tcg_rt, tcg_reg; + /* VMRS, move VFP special register to gp register */ switch (a->reg) { + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: case ARM_VFP_FPSID: + tcg_rt =3D tcg_const_i32(a->rt); + tcg_reg =3D tcg_const_i32(a->reg); + gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg); + /* fall through */ case ARM_VFP_FPEXC: case ARM_VFP_FPINST: case ARM_VFP_FPINST2: - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - case ARM_VFP_MVFR2: tmp =3D load_cpu_field(vfp.xregs[a->reg]); break; case ARM_VFP_FPSCR: diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 9710ef1c3e..44e538e51c 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1322,4 +1322,31 @@ float64 HELPER(frint64_d)(float64 f, void *fpst) return frint_d(f, fpst, 64); } =20 +void HELPER(check_hcr_el2_trap)(CPUARMState *env, int rt, int reg) +{ + if (arm_current_el(env) !=3D 1) { + return; + } + + switch (reg) { + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { + return; + } + break; + case ARM_VFP_FPSID: + if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { + return; + } + break; + default: + /* Shouldn't be here... */ + return; + } + + raise_exception(env, EXCP_HYP_TRAP, syn_vmrs_trap(rt, reg), 2); +} + #endif --=20 2.20.1