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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
Date: Tue, 26 Nov 2019 14:12:36 +0000
Message-Id: <20191126141239.8219-2-peter.maydell@linaro.org>
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From: Jean-Hugues Desch=C3=AAnes <Jean-Hugues.Deschenes@ossiaco.com>
According to the PushStack() pseudocode in the armv7m RM,
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
an FPU is present. Current implementation is doing it for
armv8, but not for armv7. This patch makes the existing
logic applicable to both code paths.
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/m_helper.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 4a48b792520..76de317e6af 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2233,19 +2233,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
if (env->v7m.secure) {
lr |=3D R_V7M_EXCRET_S_MASK;
}
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
- lr |=3D R_V7M_EXCRET_FTYPE_MASK;
- }
} else {
lr =3D R_V7M_EXCRET_RES1_MASK |
R_V7M_EXCRET_S_MASK |
R_V7M_EXCRET_DCRS_MASK |
- R_V7M_EXCRET_FTYPE_MASK |
R_V7M_EXCRET_ES_MASK;
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
lr |=3D R_V7M_EXCRET_SPSEL_MASK;
}
}
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
+ lr |=3D R_V7M_EXCRET_FTYPE_MASK;
+ }
if (!arm_v7m_is_handler_mode(env)) {
lr |=3D R_V7M_EXCRET_MODE_MASK;
}
--=20
2.20.1