From nobody Sun May 5 13:05:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574777652; cv=none; d=zohomail.com; s=zohoarc; b=Gd7fzZXLW5P1FWCTrrputtjCEg1x8aASVWpjn5vbMOlql1H0Dd3V2F7CPrM2riB80zG8fNXIcN+DkuriJtgXD7JPd+ovR776BwEX1F705w9mABRNlTgMrwUPqy1gKH40RGrsrayVfamgnyIWocti19RHdJnM0skcuj0x4b9zvIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574777652; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Er5f9rC8C8GOvtgbGPLP84tJvHsrIKrKDE2TS/iWzsk=; b=PXzAzR3Q0JsOd9PbVhTLxJn2GN+OrzNnYV5Go3TGSvM6DvKsppxzhFuWFUN70jn+rKGLXzv6Cz6QkDWCEHYe5TbS5UflYK6uLFnFQdXugG2LKQJHa9sjNN9CVviqBj/3wYz2WWAFgd+2PuBU2oEXDirYHT7bxvh0/puwNbL9SnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15747776528271008.2405758295756; Tue, 26 Nov 2019 06:14:12 -0800 (PST) Received: from localhost ([::1]:55616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbbW-0008Oo-U8 for importer@patchew.org; Tue, 26 Nov 2019 09:14:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47101) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbaA-00078t-7W for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZba9-0005kz-0o for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:45 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51943) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iZba8-0005kO-Qs for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:44 -0500 Received: by mail-wm1-x342.google.com with SMTP id g206so3393114wme.1 for ; Tue, 26 Nov 2019 06:12:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i127sm3364581wma.35.2019.11.26.06.12.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 06:12:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Er5f9rC8C8GOvtgbGPLP84tJvHsrIKrKDE2TS/iWzsk=; b=l4Vw1Mu7s5FmEufBZTSgO2m0KdYjVROitAgPcLcUO19ujTQtQqRc5NGrl/Yl7KNKZd T9LKB+cU5A9g1+af80BZtPTPz+/x3r+LYt7CoGNWolzQMS/KrZiZ2cBXCK2AUNuQjr7m iCkH5P/IGVD7TPd5DqbPaRM9ZJ/T5wP3ukXMj+AJ2SlqU0TiRzxJbH7XmWFF/EhfAmsB ee57Fd5YAH9pe1xGqscJ6yOs//cMNUFr92+XCr16ecct99xyd2LbMdx3eY4pMPaqFIq8 dWWnfZwXw5xAPVvtdDnVsZbi432pz0dmZN797UIt0CV/wa4VgMk48CnfC4gvcJG4VPzA 1WGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Er5f9rC8C8GOvtgbGPLP84tJvHsrIKrKDE2TS/iWzsk=; b=BsEQlxWPGSaVtN4giRmFy+PJ/N0jth4nDHWIcWAAtwyoGKwv2x8UGET7NyG0xyQLu2 FaX+ARx3bRmRdDx9Oa/yCUxpDrAHnP+B9VUHpUchw1f5LrgGGKB5shg6nngRlB/F9P9H UA5Y1peiCr3jsOeHLVgKstsA0wAQi5OlXky+1+Q3igLMtuf+vLBueQB3ta8eAjVG1cAM TH3gSsGni2gWxynaLlyymirSsNUxKdi0xYVRUmY5VSkSR+yRrYZp7p/xLlqoIZzKuSP+ oje98y/Ueiv8Y/wupX6b47CHheRQXe8FKJMXOO3F1x2rbWu2CKHL0dXlHymXP6oB66ju amHA== X-Gm-Message-State: APjAAAVysibkUcAYLnjoU+lKAyY61nwKu2tj6FKTqpDcTt3VXPN0W2W9 /Of/A0xpI4+KmYwRD+icaBGCsyRHEj4= X-Google-Smtp-Source: APXvYqz5wSSeUsoOdGmQmfpLpuwrHBEIqwb38Hwd8nSaM80vIY3fnX1qDixh6aRknK0+zRTt9T3Z6w== X-Received: by 2002:a05:600c:218e:: with SMTP id e14mr4268611wme.22.1574777563506; Tue, 26 Nov 2019 06:12:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET Date: Tue, 26 Nov 2019 14:12:36 +0000 Message-Id: <20191126141239.8219-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191126141239.8219-1-peter.maydell@linaro.org> References: <20191126141239.8219-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Jean-Hugues Desch=C3=AAnes According to the PushStack() pseudocode in the armv7m RM, bit 4 of the LR should be set to NOT(CONTROL.PFCA) when an FPU is present. Current implementation is doing it for armv8, but not for armv7. This patch makes the existing logic applicable to both code paths. Signed-off-by: Jean-Hugues Deschenes Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 4a48b792520..76de317e6af 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2233,19 +2233,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (env->v7m.secure) { lr |=3D R_V7M_EXCRET_S_MASK; } - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { - lr |=3D R_V7M_EXCRET_FTYPE_MASK; - } } else { lr =3D R_V7M_EXCRET_RES1_MASK | R_V7M_EXCRET_S_MASK | R_V7M_EXCRET_DCRS_MASK | - R_V7M_EXCRET_FTYPE_MASK | R_V7M_EXCRET_ES_MASK; if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { lr |=3D R_V7M_EXCRET_SPSEL_MASK; } } + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { + lr |=3D R_V7M_EXCRET_FTYPE_MASK; + } if (!arm_v7m_is_handler_mode(env)) { lr |=3D R_V7M_EXCRET_MODE_MASK; } --=20 2.20.1 From nobody Sun May 5 13:05:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574777654; cv=none; d=zohomail.com; s=zohoarc; b=IWS8YSFdvtk/AAxtf48F7sutSEGUcK9Ijv/yk78VK9aaIHBLJNe6Sxele1jRKGRd4e2CgqRQMMptQD7UaA0Ol14kUm1AODsIVibO8OQOkvX/tO9kTfQwGG0G/ZNEQ0Emf5IHUcpLc1bwd21RHa03YV8763iMqXBeYHoAH14VZP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574777654; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MI8rgCF2zRK6V6XHR4h853R4A2OJBzAcqupbIenPjRs=; b=j3yodltr/g1SdxeAvL/JladPf5kF1pEqXjTizL1V3X42IMIyJ0V3zOfGs9PlJHR7V65Z93CX7RB9DiZHug/5pZieLXLwHNkKow7WCqZk0vOghvg0neJuRuzjv/WAdReFUvKcwKbAZkiEi3Otj4um5TzK6Tuv3eytOm09ybUQt/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574777654074952.1519740757002; Tue, 26 Nov 2019 06:14:14 -0800 (PST) Received: from localhost ([::1]:55620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbbY-0008RU-1j for importer@patchew.org; Tue, 26 Nov 2019 09:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47121) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbaB-00078z-Of for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZbaA-0005lh-BA for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:47 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:38315) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iZbaA-0005lD-5M for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:46 -0500 Received: by mail-wm1-x32e.google.com with SMTP id z19so3494017wmk.3 for ; Tue, 26 Nov 2019 06:12:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i127sm3364581wma.35.2019.11.26.06.12.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 06:12:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MI8rgCF2zRK6V6XHR4h853R4A2OJBzAcqupbIenPjRs=; b=KLs7laL0I+25LPU9dOr7wyMZRU0PxmdkHEJA0wN4PEzwn4FPb960EtFGi0RTlOcIxW BUrQRTtgE4//88FrR1JjUey98PFaXxPXplZDxYpWqrai6xQMGhv1A4CoXfs7Xlx2ShMh 9Txh9M5KE3EcQwp0/qR77wE1mhnmXbMrr3ggm6voB3VOyfZWK/Ba/eVlygLMmr36Y54B GonteMGBRsz3Yxn0mX3y4rhMeV5bG2w+yEx1CJDjzIg3ow7B//4TDMo2neaZvbehVvNz DyBcKJDMJmqgEqU2vRY4PuxaHsDjrxk5/bAxSKykLsw42zAm/FzpC5TVaWQhICtIXHa8 WHeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MI8rgCF2zRK6V6XHR4h853R4A2OJBzAcqupbIenPjRs=; b=qeX+7PX9c4RC06lSg4F5A6q2GPcwgs9iMC3/bqNVFWeOuBzfqwAZ0jNWyzhXkZfPi+ udMByi1oGASguLHiV3AvnOEohjDbsGanSVQAu7vFT88XpTtCE0smQr26aM9Jpn9CLVwf MFdtPDZBFTVLAH9w+QNQP+CGeLCklk4wfqIPUHGytimJ5wuuCkpZoKJGVtnP1tlyAmcF 6RQiC9hW5RxeauuTpxAHXqPBIswIBE46V83xIJduZelMDIifo0vad8bI7gXdqxV0Moqd dKEmqACEevenBGKMRI+KusweAc7ohbSiVOMYhNGH5SPRQAkzImTXB7hxIOAu1hIlFzrO vIFw== X-Gm-Message-State: APjAAAV139NUdSQJ1hFk3TVehyhc3kxjIznhtf0OZ4F+qwcYzOwA7/vE GF/jdr7loBTz2GBzEmCm/7cNOkl4CFs= X-Google-Smtp-Source: APXvYqyb7bGiS9bbKZUYZyQ+KdQlzqC989ybsinI6Wt6WVyKY9zgH7fQxVCAgN4Un/0J7Ij9mwT46A== X-Received: by 2002:a1c:7e82:: with SMTP id z124mr4157000wmc.136.1574777564714; Tue, 26 Nov 2019 06:12:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/4] hw/arm: versal: Add the CRP as unimplemented Date: Tue, 26 Nov 2019 14:12:37 +0000 Message-Id: <20191126141239.8219-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191126141239.8219-1-peter.maydell@linaro.org> References: <20191126141239.8219-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add the CRP as unimplemented thus avoiding bus errors when guests access these registers. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 3 +++ hw/arm/xlnx-versal.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 14405c1465d..d844c4ffe47 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -119,4 +119,7 @@ typedef struct Versal { #define MM_IOU_SCNTRS_SIZE 0x10000 #define MM_FPD_CRF 0xfd1a0000U #define MM_FPD_CRF_SIZE 0x140000 + +#define MM_PMC_CRP 0xf1260000U +#define MM_PMC_CRP_SIZE 0x10000 #endif diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 98163eb1aad..8b3d8d85b86 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -257,6 +257,8 @@ static void versal_unimp(Versal *s) MM_CRL, MM_CRL_SIZE); versal_unimp_area(s, "crf", &s->mr_ps, MM_FPD_CRF, MM_FPD_CRF_SIZE); + versal_unimp_area(s, "crp", &s->mr_ps, + MM_PMC_CRP, MM_PMC_CRP_SIZE); versal_unimp_area(s, "iou-scntr", &s->mr_ps, MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, --=20 2.20.1 From nobody Sun May 5 13:05:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574777775; cv=none; d=zohomail.com; s=zohoarc; b=Aa1VASCEqYP57Yf0vpurstVZEiPk6avbjEKdA2D9kWNAfQFGZbfnDkwkMjVu1pF8ryLOA4MDW0yYPeuXltkXlX2y89G5fUQPWu3sXAjHsvBqjK68NzQfBAiQGzr5LhOzJYGMeK0ZD9Iv7ci7g879mspQ0ot4CNJDwfkDsfIXp4Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574777775; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aKXqfhFcjwTNQfz6gmtXLCCK1LadnZMXJ8QP8IawtYU=; b=aCVDRuzpZ7bX95XVeNfZ6XkxuKCx7+AfYNRbagUjjN5+bgCSO/WVdo5CkXOuJUBMfTEvsp0TzjqH4gIvipDQwihOlMhecYFMYLcdhJcRqb9KX6XwqEIRU3k/ReYEi7BiyT3Rd3ZDQBe2yBhLn20XRe9h1+DRd5PlWo8JbxDk5p0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574777775127560.6727629237481; Tue, 26 Nov 2019 06:16:15 -0800 (PST) Received: from localhost ([::1]:55656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbdV-0002EU-VT for importer@patchew.org; Tue, 26 Nov 2019 09:16:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47131) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbaC-00079g-D9 for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZbaB-0005mH-Av for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:48 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:35882) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iZbaB-0005lr-4d for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:47 -0500 Received: by mail-wm1-x341.google.com with SMTP id n188so3505912wme.1 for ; Tue, 26 Nov 2019 06:12:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i127sm3364581wma.35.2019.11.26.06.12.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 06:12:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aKXqfhFcjwTNQfz6gmtXLCCK1LadnZMXJ8QP8IawtYU=; b=DXbDcWYmL5p4FFOEabOQtqYztMUQU48iIGjBQAROPqWvor3wfVX4BCtPFtINxBudPJ tYGSmErbbmqubVeFEJiQvZJIQf7NBk/t64uH4NwDPpAYz2VB/+qlbu/1w2vy6T4CiKvt pXOY6Hm99zb5cK3YdM4vrmsGYJJA7pxzr8cALO36EwIQx+IUqg13tQkvCybn6cePEIQM pQc3mSFA5mSpNn9NPVLrmM9L9+DU6rNALJP7i7vYqzwiaZXQRNS/6PlOc8l79t3ekwr8 pVVL3j+ip5s8evOfVQ1HSVpWcJca/yKnJI462SPAM21S3t9sXOqqMBvKACg1ORBpf50C dzVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aKXqfhFcjwTNQfz6gmtXLCCK1LadnZMXJ8QP8IawtYU=; b=YE+nsmc1El25YgI0OjM0kc5ef+KKEzc2iXuBAuvJVK5MkxM6GTuFXy9fXD+oKo5V6v jGmAQjajnzT/dwmhT9mE9npQ9dd9M7hiQ3At8qoqtpXmhJJewe1LJVmRoAzmY5gBtIPP 5jchzOg6cqMvAd7Fpu0Nia2yzcDOSP9DuFBq136rPIX9OBuauTHe5k/zPUfMCSfLpBXf b/mP47AibgR8OZIzm3SOE/NaxxCFT/q08/BBe5I/OdXMUYljB7++Y4uylNOQZEuhZDXj tXtFNXcfoK7Q8whNMLCobR8GQkDimJhZySUTDhHBcIMHg4vAXHT/RczHgodO5n3Ns+Ei 5Viw== X-Gm-Message-State: APjAAAXfmSM7mdqd24R+YvNbbIIxUhAvcacz9QxItp35Zw/4VQLXPZg3 mkdo3SWvwOxFA0sFUa4nwyfpeXn59V0= X-Google-Smtp-Source: APXvYqydkbHGSC8yF+ABBGHC1r5HXf50WiP5iU/QHn+9CB7WIWvagJIH893JH2DCy8gXbPP4ybg+xA== X-Received: by 2002:a1c:99cb:: with SMTP id b194mr4725581wme.100.1574777565929; Tue, 26 Nov 2019 06:12:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2 Date: Tue, 26 Nov 2019 14:12:38 +0000 Message-Id: <20191126141239.8219-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191126141239.8219-1-peter.maydell@linaro.org> References: <20191126141239.8219-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Marc Zyngier The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1, ISR_EL1 shows the pending status of the physical IRQ, FIQ, or SError interrupts. Unfortunately, QEMU's implementation only considers the HCR_EL2 bits, and ignores the current exception level. This means a hypervisor trying to look at its own interrupt state actually sees the guest state, which is unexpected and breaks KVM as of Linux 5.3. Instead, check for the running EL and return the physical bits if not running in a virtualized context. Fixes: 636540e9c40b Cc: qemu-stable@nongnu.org Reported-by: Quentin Perret Signed-off-by: Marc Zyngier Message-id: 20191122135833.28953-1-maz@kernel.org Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a089fb5a690..027fffbff69 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1934,8 +1934,11 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) CPUState *cs =3D env_cpu(env); uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint64_t ret =3D 0; + bool allow_virt =3D (arm_current_el(env) =3D=3D 1 && + (!arm_is_secure_below_el3(env) || + (env->cp15.scr_el3 & SCR_EEL2))); =20 - if (hcr_el2 & HCR_IMO) { + if (allow_virt && (hcr_el2 & HCR_IMO)) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |=3D CPSR_I; } @@ -1945,7 +1948,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMC= PRegInfo *ri) } } =20 - if (hcr_el2 & HCR_FMO) { + if (allow_virt && (hcr_el2 & HCR_FMO)) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |=3D CPSR_F; } --=20 2.20.1 From nobody Sun May 5 13:05:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574777974; cv=none; d=zohomail.com; s=zohoarc; b=STI+lijNRkYTo0Q9ZG55CosFjU8WJj0p1Y5AUd4hAfaD8Hh9ZC/XlWON8GO8zNjZNChsD84p10wf9A9neb7nJgIf8JyvgHrY0gZ5+G25gdydxSdWSjmVg6RuzBzfJcXQhhiEiMPKwh/U/eNa7o7XMu69crwPl565P7ea+FO5BTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574777974; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1yHl23JxBbbJm19d4IXd4etGFcAifQ1EcDoDvSYqoKE=; b=jNS6HMGj0BOL01FEYY3Pptd2lzEAGTCvOYrm1mDk/IAf/LPfHor23o7AhNM0N/ASdkD7GLx9gOHZlFfTb8aurWma8LRazWC0t4v36PHZ+PF+6pqpHkDZ9+lLFyvc6QNNfR+SbtpsfNWEj//6bhIz32MDBdel+I0IKsx6RNKZc5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157477797430685.72828855824082; Tue, 26 Nov 2019 06:19:34 -0800 (PST) Received: from localhost ([::1]:55718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbgi-0003St-M9 for importer@patchew.org; Tue, 26 Nov 2019 09:19:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47152) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZbaF-0007HD-Bj for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZbaD-0005nR-5o for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:51 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:39457) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iZbaC-0005mv-SQ for qemu-devel@nongnu.org; Tue, 26 Nov 2019 09:12:49 -0500 Received: by mail-wm1-x341.google.com with SMTP id t26so3481555wmi.4 for ; Tue, 26 Nov 2019 06:12:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i127sm3364581wma.35.2019.11.26.06.12.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 06:12:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1yHl23JxBbbJm19d4IXd4etGFcAifQ1EcDoDvSYqoKE=; b=lG0M2nibZy2dfayRX6mvmWsQsmsVBzX+6bgYBwL7YKJKopoOK7JlfUi8He6PymXoJG B86k9kb1RSGetsP4CH0gXJ3nda3o+I03eCp62GfUjuwfRV48KN/+Ulm/sDn1WOw5gQKE zsmgpyWqJkW4MnkgNL9kg1uSyVWgcGwD9M6RSH0ubmrirukyUw9OgjisUZUnTK2zRUwt auU6liXMRFv7h5CkotlSsGatLBOUVQzmrgkIFUMF5w49TG79pQPo0iIDqW9MRNYSrkkb TVoW8gRqF/KbaKYr760nmxY1Dey6m63MA9gP3kJd9bJSSSzgTh8M8nmnlBpDJOarnYOf EA9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1yHl23JxBbbJm19d4IXd4etGFcAifQ1EcDoDvSYqoKE=; b=oG/Nej6KMwF8lgaw2RTClCfimZ1HYHQoN/l6kKKv5C1JttSpdedzkv0MdVJItKL0I6 nk+aclpABixj0h1d9Qc3jXashUdiBogXq/CDTa6tOvLxquqgnpOTrO8OmbE+ATiDn8P5 VtyDxLUZ+4mahkTmCSqj0YrgH2csV+vtsKhrQTN6Utio92ss969SrlQ2I4DTCxSxsH8S EQwU0Zsziqb5nd9ZJcFn1OEOo3i4CU+xQ/LzpeDh+/IVOsz79EJtz1PjIVmKsN95O+aW j0n3FX12Da/1SpsGr38wlpcCHO0Sb98829Dfw6dGpsvcjvDOwx3gGtt37N47VkASiPZN RBCw== X-Gm-Message-State: APjAAAUBoyR2GdG47vCz5mYsfYomqVblnJA7i+SgzWucKl4aHil15Di1 xyMgljfExAboL94Pry8IjP699EXYE8s= X-Google-Smtp-Source: APXvYqyFCOhw/BXjJX7lOoWQ2GorCpR59OMVGyjyvY7A07aDCzUDCO5QlsC9Z/nPBUTFuPy7ShRFig== X-Received: by 2002:a1c:f70a:: with SMTP id v10mr4146002wmh.159.1574777567147; Tue, 26 Nov 2019 06:12:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements Date: Tue, 26 Nov 2019 14:12:39 +0000 Message-Id: <20191126141239.8219-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191126141239.8219-1-peter.maydell@linaro.org> References: <20191126141239.8219-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Marc Zyngier HCR_EL2.TID3 mandates that access from EL1 to a long list of id registers traps to EL2, and QEMU has so far ignored this requirement. This breaks (among other things) KVM guests that have PtrAuth enabled, while the hypervisor doesn't want to expose the feature to its guest. To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this case), and masks out the unsupported feature. QEMU not honoring the trap request means that the guest observes that the feature is present in the HW, starts using it, and dies a horrible death when KVM injects an UNDEF, because the feature *really* isn't supported. Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set. Note that this change does not include trapping of the MVFR registers from AArch32 (they are accessed via the VMRS instruction and need to be handled in a different way). Reported-by: Will Deacon Signed-off-by: Marc Zyngier Tested-by: Will Deacon Message-id: 20191123115618.29230-1-maz@kernel.org [PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED; changed names of access functions to include _tid3] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 027fffbff69..0bf8f53d4b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5978,6 +5978,26 @@ static const ARMCPRegInfo predinv_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + return access_aa64_tid3(env, ri, isread); + } + + return CP_ACCESS_OK; +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6001,6 +6021,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_PFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_pfr0 }, /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. @@ -6008,63 +6029,78 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_aa32_tid3, .readfn =3D id_pfr1_read, .writefn =3D arm_cp_write_ignore }, { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_dfr0 }, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_afr0 }, { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_mmfr0 }, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_mmfr1 }, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_mmfr2 }, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_mmfr3 }, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar0 }, { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar1 }, { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar2 }, { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar3 }, { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar4 }, { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar5 }, { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->id_mmfr4 }, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar6 }, REGINFO_SENTINEL }; @@ -6185,164 +6221,204 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_aa64_tid3, .readfn =3D id_aa64pfr0_read, .writefn =3D arm_cp_write_ignore }, { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64pfr1}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ZFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, /* At present, only SVEver =3D=3D 0 is defined anyway. */ .resetvalue =3D 0 }, { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64PFR7_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->id_aa64dfr0 }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->id_aa64dfr1 }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64AFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->id_aa64afr0 }, { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->id_aa64afr1 }, { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64AFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64isar0 }, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64isar1 }, { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64mmfr0 }, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64mmfr1 }, { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "MVFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.mvfr0 }, { .name =3D "MVFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.mvfr1 }, { .name =3D "MVFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.mvfr2 }, { .name =3D "MVFR3_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "MVFR4_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "MVFR6_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "MVFR7_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, --=20 2.20.1