From nobody Wed Nov 12 21:53:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1574649715; cv=none; d=zohomail.com; s=zohoarc; b=Nulg1vgr+yOFQF+aleQbLJSnxmqkv5xBVRfxdCOykLSS6yPP4AXoq5i5YhrtFT7tA+ajp8SR8aeNIml5SWGmGIdjOV2MR12IS2ZIuwH8+3yinYMh1xAUvQd9kNK0Qws0MVnFPHtBar4IMOSF8W3FZMN1wmFH/sjqnKmFIHz9Dck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574649715; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=zsERLokbkXfCI0Px+SA4aTdan+j1yc/TlWebu5hjfps=; b=BqgXKCqxEdPt2jqtgIU8A3fKlt96vbPGL7zXoJwJ5eg8on+ZThaspawOjHLsqX0+GMGG7BewBk3CDW3P8DCsKBYNmtNUcx1UGOs/HkJHz9by97eAnz/biiP7IHHVQN2siwnwmuiE8P5dd+x5PT59iUFqdfXWAoTPHabd+uZ6vuo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574649714934336.5972442430311; Sun, 24 Nov 2019 18:41:54 -0800 (PST) Received: from localhost ([::1]:39808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZ4K0-0007Tx-Hl for importer@patchew.org; Sun, 24 Nov 2019 21:41:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46405) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZ4IY-0006It-RH for qemu-devel@nongnu.org; Sun, 24 Nov 2019 21:40:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZ4IW-0005p6-KO for qemu-devel@nongnu.org; Sun, 24 Nov 2019 21:40:22 -0500 Received: from mga17.intel.com ([192.55.52.151]:43957) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iZ4IV-0005of-30 for qemu-devel@nongnu.org; Sun, 24 Nov 2019 21:40:20 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Nov 2019 18:40:17 -0800 Received: from caas-nuc7i7dnhe.sh.intel.com ([10.239.158.159]) by orsmga002.jf.intel.com with ESMTP; 24 Nov 2019 18:40:15 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,239,1571727600"; d="scan'208";a="220127219" From: yadong.qi@intel.com To: qemu-devel@nongnu.org Subject: [PATCH v3 1/2] intel_iommu: refine SL-PEs reserved fields checking Date: Mon, 25 Nov 2019 08:33:20 +0800 Message-Id: <20191125003321.5669-2-yadong.qi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191125003321.5669-1-yadong.qi@intel.com> References: <20191125003321.5669-1-yadong.qi@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com, peterx@redhat.com, pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Qi, Yadong" 1. split the resevred fields arrays into two ones, 2. large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page. Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong Reviewed-by: Peter Xu --- hw/i386/intel_iommu.c | 37 ++++++++++++++++++---------------- hw/i386/intel_iommu_internal.h | 5 +---- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 14e4e6ad62..feb9e55f87 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -910,19 +910,23 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, =20 /* * Rsvd field masks for spte: - * Index [1] to [4] 4k pages - * Index [5] to [8] large pages + * vtd_spte_rsvd 4k pages + * vtd_spte_rsvd_large large pages */ -static uint64_t vtd_paging_entry_rsvd_field[9]; +static uint64_t vtd_spte_rsvd[5]; +static uint64_t vtd_spte_rsvd_large[5]; =20 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) { - if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) { - /* Maybe large page */ - return slpte & vtd_paging_entry_rsvd_field[level + 4]; - } else { - return slpte & vtd_paging_entry_rsvd_field[level]; + uint64_t rsvd_mask =3D vtd_spte_rsvd[level]; + + if ((level =3D=3D VTD_SL_PD_LEVEL || level =3D=3D VTD_SL_PDP_LEVEL) && + (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { + /* large page */ + rsvd_mask =3D vtd_spte_rsvd_large[level]; } + + return slpte & rsvd_mask; } =20 /* Find the VTD address space associated with a given bus number */ @@ -3549,15 +3553,14 @@ static void vtd_init(IntelIOMMUState *s) /* * Rsvd field masks for spte */ - vtd_paging_entry_rsvd_field[0] =3D ~0ULL; - vtd_paging_entry_rsvd_field[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[5] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[6] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[7] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[8] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_b= its); + vtd_spte_rsvd[0] =3D ~0ULL; + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); =20 if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c1235a7063..1654f746bc 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -395,14 +395,11 @@ typedef union VTDInvDesc VTDInvDesc; (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \ - (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + #define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \ - (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { --=20 2.17.1 From nobody Wed Nov 12 21:53:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1574649719; cv=none; d=zohomail.com; s=zohoarc; b=cAmnra9tQE3Mns5+YdtfNuDa0LDwtbTN91XxSNxXIpaZZe9UYePM5YyOJPc9BjWUeqjxox2e/oSLy/b19R716/1vqOx05/Ab3H2MGyr2sGsZDm3sibGznRQLdrAeIT7O+KfsBfvrGNwVHH4m0XqbIe7ytWarKBlaSRjdAy47fvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574649719; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=sLz4GJzkGTfoDFmIvNgtJUqnQrokxtntT8yr7ECCLTM=; b=a4ftgmMrZJZVq/2Pk2YLhV24ihev7dxDCInYC3V10bt4P8sAncI8Gibh8esJPC9hFBV7xD2Xj6jCRFZtyB/W/PPEDid5ihzIgn+feTVVzeiW69/ielrgW5W+Bc30B1KC4xwIY5o1CKd6VM7J/rrIks7pGeFpGmzsgHaS7A7xOng= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574649719884865.3923140073605; Sun, 24 Nov 2019 18:41:59 -0800 (PST) Received: from localhost ([::1]:39810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZ4K6-0007Xh-BH for importer@patchew.org; Sun, 24 Nov 2019 21:41:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46422) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iZ4Ia-0006J5-FP for qemu-devel@nongnu.org; Sun, 24 Nov 2019 21:40:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iZ4IY-0005pQ-GO for qemu-devel@nongnu.org; Sun, 24 Nov 2019 21:40:24 -0500 Received: from mga17.intel.com ([192.55.52.151]:43960) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iZ4IW-0005ot-Km for qemu-devel@nongnu.org; Sun, 24 Nov 2019 21:40:22 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Nov 2019 18:40:19 -0800 Received: from caas-nuc7i7dnhe.sh.intel.com ([10.239.158.159]) by orsmga002.jf.intel.com with ESMTP; 24 Nov 2019 18:40:17 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,239,1571727600"; d="scan'208";a="220127228" From: yadong.qi@intel.com To: qemu-devel@nongnu.org Subject: [PATCH v3 2/2] intel_iommu: TM field should not be in reserved bits Date: Mon, 25 Nov 2019 08:33:21 +0800 Message-Id: <20191125003321.5669-3-yadong.qi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191125003321.5669-1-yadong.qi@intel.com> References: <20191125003321.5669-1-yadong.qi@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com, peterx@redhat.com, pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Qi, Yadong" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong Reviewed-by: Peter Xu --- hw/i386/intel_iommu.c | 9 ++++++--- hw/i386/intel_iommu_internal.h | 13 ++++++++++--- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index feb9e55f87..43c94b993b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3554,13 +3554,16 @@ static void vtd_init(IntelIOMMUState *s) * Rsvd field masks for spte */ vtd_spte_rsvd[0] =3D ~0ULL; - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); =20 - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); =20 if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 1654f746bc..edcf9fc9bb 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 =20 /* Rsvd field masks for spte */ -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) @@ -396,9 +398,13 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) := \ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 /* Information about page-selective IOTLB invalidate */ @@ -503,5 +509,6 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SL_W (1ULL << 1) #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(= aw)) #define VTD_SL_IGN_COM 0xbff0000000000000ULL +#define VTD_SL_TM (1ULL << 62) =20 #endif --=20 2.17.1