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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RUy3/jS4gGvA/21v++FuloKSRPT5gl3lim3IGVoqAk0=; b=iNTTqbjTDV2rliOXYgQ5d8VYGvFqB56R24OD01Z/xwfdp+BS+DO8SfkxNjsPrgrSvD a16N1JV5PycCUJeEBv5eiqXz8idURzYxUH8Su2WLs5Wxao7Eczve6NjZ+vtj/cALirEi k/8voQu+zGOKGjcNJFy+XS0m56m6GQwY7p04SZdxVwTnH0F3o5ahS4lby1a08QdH5cf+ 8IHevVYXzXRH24ubnTNUvCxEX4HCVGwdt5KTy+AbZAoBYDo08FHps+0P2aMpVUYqrYOV 8hqDHqg0x0QIfi7gbY6noHGibiHGowRkF/7EFlO41Gxd2zwmh46mbVNhKFw2ChlkGd75 XwVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RUy3/jS4gGvA/21v++FuloKSRPT5gl3lim3IGVoqAk0=; b=SVnFyJslSpfj0fbfBHoDmM0eHau2uV1RG36uVh+ZwBbYjr39OIKSc6oTWXlxqLdnEV 8MrGgPMUs2ntVFeHrNFfA9qProlzJfYNA2vibniLC6hWbpgtT7iPHR70aSopTUf6TmpN UZFAR4uzMg+36CB7Mgegwu0aoC0RwmmCx1EaC8S1IPuQHuSzDXqnsBKnrkcfqHqCTlYl rhiinFUhCkuwc9gX+rT2Rxe+kzAxAxAfi1jxPTu1JpL4mxHfLAQ9cP6Lp7+wff/kT9vw teFQixk04plQsonj4QL0RkZXE+GrBydlAg1QYTeAbxrhmdi1Do/EYgORYAKVP8o0N+cZ rDDA== X-Gm-Message-State: APjAAAWzQTOUqF0oPqTuqLQulSlOBl5A0zVqmzxIioBLyhso35O8Uk/z STZIYoSsx5RcqxEKvIdhMhCS44jS+7mdOw== X-Google-Smtp-Source: APXvYqwajMwh5hvVfo2dtijfk3XgyKWe9Vtk8ztxPWWr4aRHlScwXX7uIUS3PGXaZMRCSuHWE+uRDw== X-Received: by 2002:a7b:cf0e:: with SMTP id l14mr5877718wmg.149.1574170317880; Tue, 19 Nov 2019 05:31:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY Date: Tue, 19 Nov 2019 13:31:45 +0000 Message-Id: <20191119133145.31466-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Simply moving the non-stub helper_v7m_mrs/msr outside of !CONFIG_USER_ONLY is not an option, because of all of the other system-mode helpers that are called. But we can split out a few subroutines to handle the few EL0 accessible registers without duplicating code. Reported-by: Christophe Lyon Signed-off-by: Richard Henderson Message-id: 20191118194916.3670-1-richard.henderson@linaro.org [PMM: deleted now-redundant comment; added a default case to switch in v7m_msr helper] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 + target/arm/m_helper.c | 114 ++++++++++++++++++++++++++---------------- 2 files changed, 73 insertions(+), 43 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47d24a53758..83a809d4bac 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1314,6 +1314,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) if (mask & XPSR_GE) { env->GE =3D (val & XPSR_GE) >> 16; } +#ifndef CONFIG_USER_ONLY if (mask & XPSR_T) { env->thumb =3D ((val & XPSR_T) !=3D 0); } @@ -1329,6 +1330,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) /* Note that this only happens on exception exit */ write_v7m_exception(env, val & XPSR_EXCP); } +#endif } =20 #define HCR_VM (1ULL << 0) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index f2512e448e2..4a48b792520 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -33,22 +33,82 @@ #include "exec/cpu_ldst.h" #endif =20 +static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, + uint32_t reg, uint32_t val) +{ + /* Only APSR is actually writable */ + if (!(reg & 4)) { + uint32_t apsrmask =3D 0; + + if (mask & 8) { + apsrmask |=3D XPSR_NZCV | XPSR_Q; + } + if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + apsrmask |=3D XPSR_GE; + } + xpsr_write(env, val, apsrmask); + } +} + +static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) +{ + uint32_t mask =3D 0; + + if ((reg & 1) && el) { + mask |=3D XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ + } + if (!(reg & 4)) { + mask |=3D XPSR_NZCV | XPSR_Q; /* APSR */ + if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + mask |=3D XPSR_GE; + } + } + /* EPSR reads as zero */ + return xpsr_read(env) & mask; +} + +static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +{ + uint32_t value =3D env->v7m.control[secure]; + + if (!secure) { + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ + value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; + } + return value; +} + #ifdef CONFIG_USER_ONLY =20 -/* These should probably raise undefined insn exceptions. */ -void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) { - ARMCPU *cpu =3D env_archcpu(env); + uint32_t mask =3D extract32(maskreg, 8, 4); + uint32_t reg =3D extract32(maskreg, 0, 8); =20 - cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + v7m_msr_xpsr(env, mask, reg, val); + break; + case 20: /* CONTROL */ + /* There are no sub-fields that are actually writable from EL0. */ + break; + default: + /* Unprivileged writes to other registers are ignored */ + break; + } } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu =3D env_archcpu(env); - - cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); - return 0; + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + return v7m_mrs_xpsr(env, reg, 0); + case 20: /* CONTROL */ + return v7m_mrs_control(env, 0); + default: + /* Unprivileged reads others as zero. */ + return 0; + } } =20 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) @@ -2196,35 +2256,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - uint32_t mask; unsigned el =3D arm_current_el(env); =20 /* First handle registers which unprivileged can read */ - switch (reg) { case 0 ... 7: /* xPSR sub-fields */ - mask =3D 0; - if ((reg & 1) && el) { - mask |=3D XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ - } - if (!(reg & 4)) { - mask |=3D XPSR_NZCV | XPSR_Q; /* APSR */ - if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - mask |=3D XPSR_GE; - } - } - /* EPSR reads as zero */ - return xpsr_read(env) & mask; - break; + return v7m_mrs_xpsr(env, reg, el); case 20: /* CONTROL */ - { - uint32_t value =3D env->v7m.control[env->v7m.secure]; - if (!env->v7m.secure) { - /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank = */ - value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; - } - return value; - } + return v7m_mrs_control(env, env->v7m.secure); case 0x94: /* CONTROL_NS */ /* * We have to handle this here because unprivileged Secure code @@ -2454,18 +2493,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mask= reg, uint32_t val) =20 switch (reg) { case 0 ... 7: /* xPSR sub-fields */ - /* only APSR is actually writable */ - if (!(reg & 4)) { - uint32_t apsrmask =3D 0; - - if (mask & 8) { - apsrmask |=3D XPSR_NZCV | XPSR_Q; - } - if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - apsrmask |=3D XPSR_GE; - } - xpsr_write(env, val, apsrmask); - } + v7m_msr_xpsr(env, mask, reg, val); break; case 8: /* MSP */ if (v7m_using_psp(env)) { --=20 2.20.1