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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8XC9VRBYxoao7D5gAki2M8EB8ioO9WQynWtrDET/dPw=; b=W5E3SN/WiKih3KXsrg6VDeKWOGgAKXPzuWZZspBGFDZYLFnVt8kyoR1sXcL7NE7uvS aS4vA9D8JCkyOdQd2nLb40qbBhwDgXMiwTcnCk5sVJo++Uu1g3VGzde2Mf1f0tjfntEx rmAcwGa6Ujyu2dcTwtcHNYiAXqvBSa2NUcEhU1D0Divo/acQkGLJHzIeVlhbUZqn+fI4 vRM+cWOjIOwBhNkl1gGDv5643Zflqo0BSywax/Tn9wFDo/61V5edGG0uuVDuPEncB2WD 9H1mUjqf5NtjIoDbAuYUNOTsQodaWf8TjdpKTusmnhZpQBC1fhxrQIYRp9hKHD8nSlt4 ur4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XC9VRBYxoao7D5gAki2M8EB8ioO9WQynWtrDET/dPw=; b=n99z3RpVOEPACq5NnIfN0Ay9plklfLT5J4UXs4zjoCZIZhgoVUTrCAxXZUOtvPZ+sa GxAKGY9QL3pKmpOA85M5o58WUDikufS41DVLqSdT38ciJV5kna13WghzfUTnWhJZPDw3 bpkbq0v3oBUPFhf1OmdvVT89sf4znLzm9CuX3IfB0ayrCiv3bXPlTGbZgG+mRILkZQPk P+1hmfC8kJS7uwX7ZL4kW1hXKodIOygLnzzUh+Xq52o1R2MOy+jTL8XUxE6zmg4iKVcI GI+CnJn9WhPrg1HhmP06aEKXLzsR0+ZzG1O1ovXjRJ0S1WUft6ai4SLboboyzvKAIIE/ TeBQ== X-Gm-Message-State: APjAAAX9PQaBiTggUHY+hwyB6QyGclJtS/rT5sin7pUet03hE4vhRnEN lCp/jUUFN4+5+sDzeHAzlE2Gh9ew/GCs4g== X-Google-Smtp-Source: APXvYqxLcDGuFsrPwZ71N5GxzYJVz5CrIMjD+ZM8fLBHkhGFOXKiB46cyIiXx2hfG+ttmPM5bZpvxw== X-Received: by 2002:adf:b686:: with SMTP id j6mr26170818wre.186.1574170313060; Tue, 19 Nov 2019 05:31:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes Date: Tue, 19 Nov 2019 13:31:41 +0000 Message-Id: <20191119133145.31466-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu A few configuration register writes need not update the spi bus state, so j= ust return after the register write. Signed-off-by: Sai Pavan Boddu Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Tested-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a309c712ca8..0d6c2e1a61d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ #define R_GPIO (0x30 / 4) #define R_LPBK_DLY_ADJ (0x38 / 4) #define R_LPBK_DLY_ADJ_RESET (0x33) +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) #define R_TXD1 (0x80 / 4) #define R_TXD2 (0x84 / 4) #define R_TXD3 (0x88 / 4) @@ -139,6 +140,8 @@ #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 +#define R_DUMMY_CYCLE_EN (0xC8 / 4) +#define R_ECO (0xF8 / 4) #define R_MOD_ID (0xFC / 4) =20 #define R_GQSPI_SELECT (0x144 / 4) @@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, { int mask =3D ~0; XilinxSPIPS *s =3D opaque; + bool try_flush =3D true; =20 DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr, (unsigned)va= lue); addr >>=3D 2; @@ -1019,13 +1023,23 @@ static void xilinx_spips_write(void *opaque, hwaddr= addr, tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; + /* Skip SPI bus update for below registers writes */ + case R_GPIO: + case R_LPBK_DLY_ADJ: + case R_IOU_TAPDLY_BYPASS: + case R_DUMMY_CYCLE_EN: + case R_ECO: + try_flush =3D false; + break; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); no_reg_update: - xilinx_spips_update_cs_lines(s); - xilinx_spips_check_flush(s); - xilinx_spips_update_cs_lines(s); - xilinx_spips_update_ixr(s); + if (try_flush) { + xilinx_spips_update_cs_lines(s); + xilinx_spips_check_flush(s); + xilinx_spips_update_cs_lines(s); + xilinx_spips_update_ixr(s); + } } =20 static const MemoryRegionOps spips_ops =3D { --=20 2.20.1