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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TuuysipQCj49mLVP6qzC24BBiVXuGGfeJLuCpI9AXuw=; b=YD5cGgEC/OkOSVmkZ1yo0OuIvaOwk+Pp8QliQXnLEi8EI+f7DDACuqSehWNZ3ccUDM nFEoyDBH9R0EmWtiHm6LrpFZNGtT8Bp8Cxl8PPl6Xvin047n+DL24DcZGFbhInwPigQ6 2Rwgt1GiqQWX35GPHbcewMLcicihyBpJPQBsPYJEhxJg5UQe4kk09yrjDcULfu3H0vOo PqVj+veBeWLtUZ7Bm4A8VCjCdGdenwUEozEH4a5cuATem/spcD3+X4zowNptAI4w5FZT 2LoTMGgxpmDjDeDClhwOM2puW8kUl9cJG30BDP973RP1uA/Gb8gDzV9wBm5DHigxKFhr Q98Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TuuysipQCj49mLVP6qzC24BBiVXuGGfeJLuCpI9AXuw=; b=HNNULutLRsoLZTVA+eLJuheDxOhdVvMRBvrSB6UwsNp3/QXzxj+qRiztmHKA3f2qgL KBGHvsy3cwVc+EgmedKXP5jb/kfITNKnZoPyRAFMMFVm0cvkTs/ulzNgMD4z/jSj9wk1 f03F9SlBtSS+TmD7fJsfR96ssdT+FpxfweqN0FgIXIJaIxuuhfwlFiRLpa6p6/12wDZw bvzC3GnsPyKKNbBTw2K3dNLwZoqHirEETDrzrMcNFd59Q5UaeINrWe3zoH9xv0GuBZ0k c+jnzDpYrCuRJmCVyhZ27KkAuAr17Y9NBZ5t49FfTjSHJPC/RLWccKy2esm0N8lz2nSL FmBw== X-Gm-Message-State: APjAAAUC5ra7j8QycRE9KQV1GOGIdryhUXo/q6s9wF1oNXHP2JbvphCV J/FTq7lfNNzKL8qa2+BqSCQNB+/I9b1kfA== X-Google-Smtp-Source: APXvYqyWU9/XGM8wQr/ueYcig80RIt3MNw/lDI+LXnQI5slm2sQol+v5A/Y3dgY04uv38uuYQ9NkOw== X-Received: by 2002:adf:fe81:: with SMTP id l1mr27430510wrr.207.1574170309642; Tue, 19 Nov 2019 05:31:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/7] pl031: Expose RTCICR as proper WC register Date: Tue, 19 Nov 2019 13:31:39 +0000 Message-Id: <20191119133145.31466-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf The current PL031 RTCICR register implementation always clears the IRQ pending status on a register write, regardless of the value the guest writes. To justify that behavior, it references the ARM926EJ-S Development Chip Reference Manual (DDI0287B) and indicates that said document states that any write clears the internal IRQ state. It is indeed true that in section 11.1 this document says: "The interrupt is cleared by writing any data value to the interrupt clear register RTCICR". However, later in section 11.2.2 it contradicts itself by saying: "Writing 1 to bit 0 of RTCICR clears the RTCINTR flag." The latter statement matches the PL031 TRM (DDI0224C), which says: "Writing 1 to bit position 0 clears the corresponding interrupt. Writing 0 has no effect." Let's assume that the self-contradictory DDI0287B is in error, and follow the reference manual for the device itself, by making the register write-one-to-clear. Reported-by: Hendrik Borghorst Signed-off-by: Alexander Graf Message-id: 20191104115228.30745-1-graf@amazon.com [PMM: updated commit message to note that DDI0287B says two conflicting things] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/rtc/pl031.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c index 3a982752a2a..c57cf83165d 100644 --- a/hw/rtc/pl031.c +++ b/hw/rtc/pl031.c @@ -149,11 +149,7 @@ static void pl031_write(void * opaque, hwaddr offset, pl031_update(s); break; case RTC_ICR: - /* The PL031 documentation (DDI0224B) states that the interrupt is - cleared when bit 0 of the written value is set. However the - arm926e documentation (DDI0287B) states that the interrupt is - cleared when any value is written. */ - s->is =3D 0; + s->is &=3D ~value; pl031_update(s); break; case RTC_CR: --=20 2.20.1 From nobody Mon May 6 14:06:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574170667; cv=none; d=zoho.com; s=zohoarc; b=fOFhc9TuIr1cTEf8W0kxNoTZDpcS86chVQ7ajvmFoFM+/q7W/AJY7QrcJ694lyBY2j6MeFdQiKg2JW6s+HZWcdoDkdKD6EoRN3urlR1ymV2VHzNFEBWa687tukuQ9oynx4uhE+nYeTH/2ubEgmp0meHBaNhqK2gBrxz2GCk6nXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574170667; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iGWZ0PfY5IUQy4sucaflr8QXzQ3jHm0HWAjCaALUXUg=; b=UKblumIO9ItEUFxaEl3kZwbdwtx8/YaQgw4lTEBlwmucNuHqhXupyMk2ymeScl3Ip2XaPHyzT7zm+a3lhcC+sEsAg2foBRPczvQB3qF8wWeR0fN+yYzvdU1UblS80HHoJM+I7SsvnQ2GljOzeKG+flSoiep+ogJztE+GzfnV4sA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574170667068984.6776578551521; Tue, 19 Nov 2019 05:37:47 -0800 (PST) Received: from localhost ([::1]:45474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3hR-0000Bo-Og for importer@patchew.org; Tue, 19 Nov 2019 08:37:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36157) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3bo-0003NT-6H for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX3bm-0004BI-EW for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:56 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iX3bk-0004AL-OE for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:53 -0500 Received: by mail-wr1-x442.google.com with SMTP id z10so23823614wrs.12 for ; Tue, 19 Nov 2019 05:31:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iGWZ0PfY5IUQy4sucaflr8QXzQ3jHm0HWAjCaALUXUg=; b=m/s1IrfnWSgxOa2W2pTFCz+P34ugtLjXN5FRoCI8ef5mZM6tVaGkxaM7DbqUxkWtva i4dMsUr3IvQpKSvO7sPI/oTzrVFMxLR2LPpbIfNBfusFQXXyj2myFiWKY1d/F/KpTFzv Uk72r61nP7iJ4uvWgH2dG0zAVtru0l6klkEYXEuwzZWaa3ASGYnlZwVXWdsKz3GGvbpN IRGqjqiE03KSMauBHRxiOcu4FEFbB3wrp/M5MSFk8ddU6uTNXKcnfVh/lWbrtQ3AVN46 xKZ7qmtjmnLsxnW2Xa+1h/LzIAXCC1wwhuijL+uiihPe5j1XB9ESTI2dfETveaH8UaO4 2h2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iGWZ0PfY5IUQy4sucaflr8QXzQ3jHm0HWAjCaALUXUg=; b=IhKvEBpBb/oubeTLOPECvTvZ46Uy0gw4aWYdBnye7V1OouCCJhTl8v1JGo5n5wViWs KOf+nVllVwfvetiCgOcIAgYdPz1Vh68+TfAVuALpQbbLkiE4fp0XRakvJlESVI65VLjk yWBbRPdUyWrexhY+ddaP8YbBhDOd9+ZQMisOocJ6adxqJap7V0dOADuOgVVNuuy6YxT8 +Cvrp06hsG/JluXH5qzBrRtOpm1G1cCZLjiE4YuPjZ5AEDoKXahlv8LzBieoKAtS9Ej8 zWGE2ksE1cnUZVNlr5WbZo6hMlERDsygV3BGIS6xnfudGsJuxiajby96Xjs9Aoqlp0jn uYJQ== X-Gm-Message-State: APjAAAU1wN3AotZl/7+n6Zz7tSnP5AKFpUIY2rfDTGD3hEWNLGbeLSTG swlknRzEnaQjQmNFdBVj+1QgdOm7ii4Jzg== X-Google-Smtp-Source: APXvYqw3NDE8CGMQPl/FMQ0jMbEqhV0lUVxnkAWBcA77FnwLF8rjPJ26TwKoVMJZ00ehk8SUkKNHJw== X-Received: by 2002:adf:ffd0:: with SMTP id x16mr35292359wrs.86.1574170311008; Tue, 19 Nov 2019 05:31:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller Date: Tue, 19 Nov 2019 13:31:40 +0000 Message-Id: <20191119133145.31466-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Coverity reports, in sve_zcr_get_valid_len, "Subtract operation overflows on operands arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U" First, the aarch32 stub version of arm_cpu_vq_map_next_smaller, returning 0, does exactly what Coverity reports. Remove it. Second, the aarch64 version of arm_cpu_vq_map_next_smaller has a set of asserts, but they don't cover the case in question. Further, there is a fair amount of extra arithmetic needed to convert from the 0-based zcr register, to the 1-base vq form, to the 0-based bitmap, and back again. This can be simplified by leaving the value in the 0-based form. Finally, use test_bit to simplify the common case, where the length in the zcr registers is in fact a supported length. Reported-by: Coverity (CID 1407217) Signed-off-by: Richard Henderson Reviewed-by: Andrew Jones Message-id: 20191118091414.19440-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 --- target/arm/cpu64.c | 15 --------------- target/arm/helper.c | 9 +++++++-- 3 files changed, 7 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e1a66a2d1cc..47d24a53758 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -185,12 +185,9 @@ typedef struct { #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq); #else # define ARM_MAX_VQ 1 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } -static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t v= q) -{ return 0; } #endif =20 typedef struct ARMVectorReg { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 68baf0482ff..a39d6fcea34 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -458,21 +458,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) cpu->sve_max_vq =3D max_vq; } =20 -uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq) -{ - uint32_t bitnum; - - /* - * We allow vq =3D=3D ARM_MAX_VQ + 1 to be input because the caller ma= y want - * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this - * function always returns the next smaller than the input. - */ - assert(vq && vq <=3D ARM_MAX_VQ + 1); - - bitnum =3D find_last_bit(cpu->sve_vq_map, vq - 1); - return bitnum =3D=3D vq - 1 ? 0 : bitnum + 1; -} - static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, void *opaque, Error **errp) { diff --git a/target/arm/helper.c b/target/arm/helper.c index be67e2c66d6..a089fb5a690 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5363,9 +5363,14 @@ int sve_exception_el(CPUARMState *env, int el) =20 static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) { - uint32_t start_vq =3D (start_len & 0xf) + 1; + uint32_t end_len; =20 - return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1; + end_len =3D start_len &=3D 0xf; + if (!test_bit(start_len, cpu->sve_vq_map)) { + end_len =3D find_last_bit(cpu->sve_vq_map, start_len); + assert(end_len < start_len); + } + return end_len; } =20 /* --=20 2.20.1 From nobody Mon May 6 14:06:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574170665; cv=none; d=zoho.com; s=zohoarc; b=TT17zjHV0Qt7+MYZ6PD8jiMzeEdfEBu30W9jbeSFKvnfGqYlOVSmcntvK5MNn/F1fcRFFjw8nYEsybhyMEA0ItvUJAh9H9phZ2duSpIzb+WozSKfzcW/EFxH9as0O9WLq3amU7kYe954IUit4xub05i5+lKdAqbl7Ofam7lL6TU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574170665; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8XC9VRBYxoao7D5gAki2M8EB8ioO9WQynWtrDET/dPw=; b=EaX9qpMpZtkHey04eRWHB9N03IqGNF3Y9BM6HzRXI1Q0ipT49IW03M2Ss6vW1nxz06451gPUyAp9HocnPLqKWVZ6ezSI2wmpfyte4HziHPPLiQ0XDdbgB6/oLeAUcAIkjTLWRJsZeddEanJ9gmWAOF/k1uwoOJmiyKrU2TUDvFA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574170665452724.8953652434758; Tue, 19 Nov 2019 05:37:45 -0800 (PST) Received: from localhost ([::1]:45470 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3hO-00008j-Tk for importer@patchew.org; Tue, 19 Nov 2019 08:37:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36160) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3bo-0003NX-7f for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX3bn-0004Bh-3A for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:56 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:43412) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iX3bm-0004BB-Eu for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:54 -0500 Received: by mail-wr1-x433.google.com with SMTP id n1so23814672wra.10 for ; Tue, 19 Nov 2019 05:31:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8XC9VRBYxoao7D5gAki2M8EB8ioO9WQynWtrDET/dPw=; b=W5E3SN/WiKih3KXsrg6VDeKWOGgAKXPzuWZZspBGFDZYLFnVt8kyoR1sXcL7NE7uvS aS4vA9D8JCkyOdQd2nLb40qbBhwDgXMiwTcnCk5sVJo++Uu1g3VGzde2Mf1f0tjfntEx rmAcwGa6Ujyu2dcTwtcHNYiAXqvBSa2NUcEhU1D0Divo/acQkGLJHzIeVlhbUZqn+fI4 vRM+cWOjIOwBhNkl1gGDv5643Zflqo0BSywax/Tn9wFDo/61V5edGG0uuVDuPEncB2WD 9H1mUjqf5NtjIoDbAuYUNOTsQodaWf8TjdpKTusmnhZpQBC1fhxrQIYRp9hKHD8nSlt4 ur4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XC9VRBYxoao7D5gAki2M8EB8ioO9WQynWtrDET/dPw=; b=n99z3RpVOEPACq5NnIfN0Ay9plklfLT5J4UXs4zjoCZIZhgoVUTrCAxXZUOtvPZ+sa GxAKGY9QL3pKmpOA85M5o58WUDikufS41DVLqSdT38ciJV5kna13WghzfUTnWhJZPDw3 bpkbq0v3oBUPFhf1OmdvVT89sf4znLzm9CuX3IfB0ayrCiv3bXPlTGbZgG+mRILkZQPk P+1hmfC8kJS7uwX7ZL4kW1hXKodIOygLnzzUh+Xq52o1R2MOy+jTL8XUxE6zmg4iKVcI GI+CnJn9WhPrg1HhmP06aEKXLzsR0+ZzG1O1ovXjRJ0S1WUft6ai4SLboboyzvKAIIE/ TeBQ== X-Gm-Message-State: APjAAAX9PQaBiTggUHY+hwyB6QyGclJtS/rT5sin7pUet03hE4vhRnEN lCp/jUUFN4+5+sDzeHAzlE2Gh9ew/GCs4g== X-Google-Smtp-Source: APXvYqxLcDGuFsrPwZ71N5GxzYJVz5CrIMjD+ZM8fLBHkhGFOXKiB46cyIiXx2hfG+ttmPM5bZpvxw== X-Received: by 2002:adf:b686:: with SMTP id j6mr26170818wre.186.1574170313060; Tue, 19 Nov 2019 05:31:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes Date: Tue, 19 Nov 2019 13:31:41 +0000 Message-Id: <20191119133145.31466-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu A few configuration register writes need not update the spi bus state, so j= ust return after the register write. Signed-off-by: Sai Pavan Boddu Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Tested-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a309c712ca8..0d6c2e1a61d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ #define R_GPIO (0x30 / 4) #define R_LPBK_DLY_ADJ (0x38 / 4) #define R_LPBK_DLY_ADJ_RESET (0x33) +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) #define R_TXD1 (0x80 / 4) #define R_TXD2 (0x84 / 4) #define R_TXD3 (0x88 / 4) @@ -139,6 +140,8 @@ #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 +#define R_DUMMY_CYCLE_EN (0xC8 / 4) +#define R_ECO (0xF8 / 4) #define R_MOD_ID (0xFC / 4) =20 #define R_GQSPI_SELECT (0x144 / 4) @@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, { int mask =3D ~0; XilinxSPIPS *s =3D opaque; + bool try_flush =3D true; =20 DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr, (unsigned)va= lue); addr >>=3D 2; @@ -1019,13 +1023,23 @@ static void xilinx_spips_write(void *opaque, hwaddr= addr, tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; + /* Skip SPI bus update for below registers writes */ + case R_GPIO: + case R_LPBK_DLY_ADJ: + case R_IOU_TAPDLY_BYPASS: + case R_DUMMY_CYCLE_EN: + case R_ECO: + try_flush =3D false; + break; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); no_reg_update: - xilinx_spips_update_cs_lines(s); - xilinx_spips_check_flush(s); - xilinx_spips_update_cs_lines(s); - xilinx_spips_update_ixr(s); + if (try_flush) { + xilinx_spips_update_cs_lines(s); + xilinx_spips_check_flush(s); + xilinx_spips_update_cs_lines(s); + xilinx_spips_update_ixr(s); + } } =20 static const MemoryRegionOps spips_ops =3D { --=20 2.20.1 From nobody Mon May 6 14:06:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574170508; cv=none; d=zoho.com; s=zohoarc; b=NwtxvMydxU3lBxd4I2jhzfdszVo7oxqhooF7NQnEjUA4cjJjxnRw7tTPvEuM0lqSPMmBhXoY+sOd0INuFBgwpxBHbDoKZXvLyOGJGDhqVAvBC5Fg6/Dq2A1gCQPgmJp8L6rren0ryy8RVHoSc7lwPrWaw545br7Hk8TXCfx6yuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574170508; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6sVtcsXVTj567xQbM+Cap2mzh1eDz0KNX+fPLM9xQRI=; b=YZcTTyFRbBoOLfYct8bpMOxa+R+uf9PW0wGE6I0qOaAec927h+1wZq3S4cLSJcGi3IKAFdvHCyHL/5va1oQdV+1QByIxd3VBTDDTv5G4RsbjwqdnHgOVKntihoQE2yqNw+enCK6iA9YVDZC7DuVCE0eWGgBSKFcrYdPDVjNZAxo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574170508682166.26487333927162; Tue, 19 Nov 2019 05:35:08 -0800 (PST) Received: from localhost ([::1]:45436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3er-0005Bh-5G for importer@patchew.org; Tue, 19 Nov 2019 08:35:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36164) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3bo-0003Nf-Ny for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX3bn-0004Bt-HU for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:56 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45871) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iX3bn-0004Ba-BM for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:55 -0500 Received: by mail-wr1-x442.google.com with SMTP id z10so23823812wrs.12 for ; Tue, 19 Nov 2019 05:31:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6sVtcsXVTj567xQbM+Cap2mzh1eDz0KNX+fPLM9xQRI=; b=y2EjhJopOcbgtfvuPu48S/Zf26HmoYAqvOmEswb6rYbtYx0Uq8nBU4Eg3HWICB91wN nRQeiIUYXf9Hl/VMOegvwQdGUnD8NNC7a5Spi2cVMDwhotXBZigsdtJYSoNY0fKqJMov fTO+yNLJyzJqi7adS6+1xhq9sHeOpaMtSXF0P+KvYoWf0qW0hRsSHKU2iF6yc8x43xUH gKX+XdXQHR/7bA/X6LTTQz3dfGSOva2hjkKfAFk8gnDytMKGGBTPNRVdtG1BNTJTx2N8 tx+d7OIeBQ3EKcfjRvLRw0FGRvSeoxIVSH5M/FDi8sCuvz7Yjmxhpqrjv2McFv7XyHqD gkYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6sVtcsXVTj567xQbM+Cap2mzh1eDz0KNX+fPLM9xQRI=; b=X1iW24FUc1GIVblLDJkRMXSx7ZmArcimED9L68DFXXb2fJH7ZvFfHsD/0qC6PZzW9M 0iI4GlamSm2N5ltuIv+OtmgZ00qMU24euGasahjaMKvi40g46hRAXi2bTcgGA9g1uPIn 5w4q/R3uDw93+OkrCt+HceacDOZl7mUSdCWs3SA6PIjftgdldGP2GgnNMAkcMaoifWON ioYew1jKUeU7b119DthC2vkK73RbKZALPexua2l0N2U52194Di6CBwbX0ZKH1aCOLKbe RWvit0qxzyHUfogXCWJvSrlWDd/Goe87o3gxbEIO1eVbiaGZL8+QSsdlJyhg6iEqzgLF mIFA== X-Gm-Message-State: APjAAAVloMsBMDXJn0A7DNHvSojRKZmcm+YwEkpF1MW2wvjemW7FYMDq 0d3S/sUT9UQRSC+K8Waq7L/OpZosv2lEwQ== X-Google-Smtp-Source: APXvYqxz5mQwfKps79YUHPI8G+qIold8yDqfTyPbMQ7pCMvduWA4w6wU3uF0wvFwIboOCQ+k9Q1/ZA== X-Received: by 2002:a5d:460b:: with SMTP id t11mr38750489wrq.185.1574170314125; Tue, 19 Nov 2019 05:31:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status Date: Tue, 19 Nov 2019 13:31:42 +0000 Message-Id: <20191119133145.31466-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Linus Ziegert The Linux kernel PHY driver sets AN_RESTART in the BMCR of the PHY when autonegotiation is started. Recently the kernel started to read back the PHY's AN_RESTART bit and now checks whether the autonegotiation is complete and the bit was cleared [1]. Otherwise the link status is down. The emulated PHY needs to clear AN_RESTART immediately to inform the kernel driver about the completion of autonegotiation phase. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/comm= it/?id=3Dc36757eb9dee Signed-off-by: Linus Ziegert Reviewed-by: Alistair Francis Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 7f9cb5ab955..b8be73dc558 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -271,9 +271,10 @@ #define PHY_REG_EXT_PHYSPCFC_ST 27 #define PHY_REG_CABLE_DIAG 28 =20 -#define PHY_REG_CONTROL_RST 0x8000 -#define PHY_REG_CONTROL_LOOP 0x4000 -#define PHY_REG_CONTROL_ANEG 0x1000 +#define PHY_REG_CONTROL_RST 0x8000 +#define PHY_REG_CONTROL_LOOP 0x4000 +#define PHY_REG_CONTROL_ANEG 0x1000 +#define PHY_REG_CONTROL_ANRESTART 0x0200 =20 #define PHY_REG_STATUS_LINK 0x0004 #define PHY_REG_STATUS_ANEGCMPL 0x0020 @@ -1345,7 +1346,7 @@ static void gem_phy_write(CadenceGEMState *s, unsigne= d reg_num, uint16_t val) } if (val & PHY_REG_CONTROL_ANEG) { /* Complete autonegotiation immediately */ - val &=3D ~PHY_REG_CONTROL_ANEG; + val &=3D ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); s->phy_regs[PHY_REG_STATUS] |=3D PHY_REG_STATUS_ANEGCMPL; } if (val & PHY_REG_CONTROL_LOOP) { --=20 2.20.1 From nobody Mon May 6 14:06:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574170669; cv=none; d=zoho.com; s=zohoarc; b=Y8t6anXQ4WYy8i7Nlov+55QtRFN0sUN1cLnQazbb8MLUCalBr2VvmpG5Yno2cWT6Ugj6k9IUG08CdR8o6sTZ/2szWvrP0gNqvFUicSVXTBv3pypGSRpJ666QOpQ5Nn+Kgnktt5DmXYDaKjv1pNBO6InCFIl6HxyRvV9pZ3blYfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574170669; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y2M3WHGY+Q1Ah8M4tb/j4vEz9JAnBUgll0Pz7NMzIJ8=; b=MIHlrJbDUsfecCEjltV3CsOiuK62P6gz3fkufb3QUV+bTfAjPI1khsXzYS2PXtQjG3pmNQfZ72LfXOMZNrWz2/m7eKBDTbbice+0oxf33mLX5Qja6XRBh01tENahW6wfFZGrI6oF01PhSsLo6RqLQq145MEH+wSjcE0q7lctjsU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574170669540317.6268659789887; Tue, 19 Nov 2019 05:37:49 -0800 (PST) Received: from localhost ([::1]:45478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3hU-0000Hv-CV for importer@patchew.org; Tue, 19 Nov 2019 08:37:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36183) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3bq-0003Nm-AW for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX3bo-0004Ck-Qs for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:58 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:43405) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iX3bo-0004C8-L5 for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:56 -0500 Received: by mail-wr1-x42b.google.com with SMTP id n1so23814796wra.10 for ; Tue, 19 Nov 2019 05:31:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y2M3WHGY+Q1Ah8M4tb/j4vEz9JAnBUgll0Pz7NMzIJ8=; b=ZA1tm6+tl4AfOzzUBuCyJSnvBPnYK6u8D36c3B0nTMk7/9Oadnxvde6jkrS3EJqHKV UPLx8mVgeGO3AYle6pXpVj+F7Jbp9PV2NR5YTH4wMOX+tr3MbeE9QbiCsokuz3V7Yv2n vLk3nOJ9BLUXAf7s6RGe/FJKVHnl3Rf2SCa44ebaLBMNAJwOpG7ybvvZuF6HmA8YXD0R E9xybEWSkHAI4vouhYsNpADY11CoyLwmd7/9fOW3ZknyMkZyTIrwaVjtqVVe1Uhzp6M7 TxVnUJSXvhtNPWqwWb7pKxBr4PrcdvLgIayhuIRoQ8G6Vp3zxSI2xDe6ra7A8/laa5/t W1Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y2M3WHGY+Q1Ah8M4tb/j4vEz9JAnBUgll0Pz7NMzIJ8=; b=AOtEIdgQYA0Ja7qohPjtkbRmBqpjXonDJ1uKsHjTZ4k5jiblAcJ8LVD1B2oNEOvADr ffxYSRER06LWkg73MY72TKrFKeNsNHadmPM6fhliiyheqA7oDHY4pdjFMvGCRetAvYZ/ zDGHDAO7sbSpIJst+te9SJlZ2RHDgjV0dct4Yh346x4iNYbhkllG1K+nrttTJXZE+ZKy 0qXCvYVj1AXZFkFRi2qzuhsA2qCievTnZ+89d+w9S6GWAwQVYN2ArCtDhwAhTsUPv/7b 2Jd1BIC4Rh/EvX0+k729xsmbFw2gleyHn2L0t2kxrKU0fXGXzRrXtDjmGlG7kVgXpRJu wkWA== X-Gm-Message-State: APjAAAV4cCG5eILntgPcjAVH+DuU6ib4WKcc92SWLG8IC+JMW13pZOic mQsLRmRNy5cT0ezRWqE9+5tqfGmjttxTIw== X-Google-Smtp-Source: APXvYqzv3hwCaHqUzsTaAjZp+ZDvCX7AlDpjKXMxUiRh3nPVhsfcrOClSi0Je/S/RQQwLuGB5HcZ6w== X-Received: by 2002:a05:6000:18c:: with SMTP id p12mr9329155wrx.154.1574170315356; Tue, 19 Nov 2019 05:31:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/7] target/arm: Do not reject rt == rt2 for strexd Date: Tue, 19 Nov 2019 13:31:43 +0000 Message-Id: <20191119133145.31466-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson There was too much cut and paste between ldrexd and strexd, as ldrexd does prohibit two output registers the same. Fixes: af288228995 Reported-by: Michael Goffioul Signed-off-by: Richard Henderson Message-id: 20191117090621.32425-2-richard.henderson@linaro.org Reviewed-by: Robert Foley Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2ea9da7637b..b285b23858e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8934,7 +8934,7 @@ static bool op_strex(DisasContext *s, arg_STREX *a, M= emOp mop, bool rel) || (s->thumb && (a->rd =3D=3D 13 || a->rt =3D=3D 13)) || (mop =3D=3D MO_64 && (a->rt2 =3D=3D 15 - || a->rd =3D=3D a->rt2 || a->rt =3D=3D a->rt2 + || a->rd =3D=3D a->rt2 || (s->thumb && a->rt2 =3D=3D 13)))) { unallocated_encoding(s); return true; --=20 2.20.1 From nobody Mon May 6 14:06:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574170862; cv=none; d=zoho.com; s=zohoarc; b=YLqfNv0HFSVYGShR+ISynCyCD+OGKyJBuqr1NvY0hXH+i6XcfpBjTC26F0qJI/q76E0DvNpUVKTx0ukKFEu5ds3Wy5xTg5kiExLpFj/KoeEs4qwsuRsOj5MrwnXPq8qNyRkkR8sEhkAInaPCS0uDrFXnxr0GCxIwtG/XHlgwMMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574170862; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J0hxGY0jJpmZh7ivi67CDnclur1WCNLzFEVxxDUt0Cs=; b=bygLUa4KRdF8VX1r7OFSkrT0qRt0aSSZL1hH6TkAqUDyn0s4czDLqWyZKnCGJqEpgobUDWkVF8LbGZcpYvUtCuaiNnbEvF5Nip3lmAWFtxHfNrMIUDF/QlKCpxb41V51pFHaKIq9Z2qYozqSUcmcbZm5yNI46YUjpoi1XUTSRfs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574170862754547.6744328795941; Tue, 19 Nov 2019 05:41:02 -0800 (PST) Received: from localhost ([::1]:45520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3kW-0002kF-Tt for importer@patchew.org; Tue, 19 Nov 2019 08:40:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36197) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3br-0003Q2-Hf for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:32:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX3bq-0004DJ-ED for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:59 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:52299) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iX3bq-0004Cr-8Q for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:58 -0500 Received: by mail-wm1-x335.google.com with SMTP id l1so3196648wme.2 for ; Tue, 19 Nov 2019 05:31:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=J0hxGY0jJpmZh7ivi67CDnclur1WCNLzFEVxxDUt0Cs=; b=QH23rFMl7ZvgnihMkOVrb9+Ow/Qi+5ZSRh25JcAxcspRV1O2pf6agofJtlYkAb3NEK +UWYfFwkOC7LFcHMf/iAKTaAcJb8Yd3J2AgAZKEqcFSJ6i76xdpLdZFmWK2S7ibfbsFF 3nrQbezpRkO92HfMDyWlNiO6gVfPfsgs6otFkR+TK1nRZko0qoDUSbegep3uTy8cU5gj /u2sPpvcQtKxsE63gisHNF71LC6/OpXG9rxwWNGb3+3Vctj14EbJaEg/6kB8689TxiJ/ oRqp15FiPCx1yDW3XsrTXrTy7AXMJDN7tP6ADJayZ5Tqx2pT87VBtmoKfAjLTf0wG1vK Wu/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J0hxGY0jJpmZh7ivi67CDnclur1WCNLzFEVxxDUt0Cs=; b=nXSGiXtQmAO/XDNJZsSAeDSJ2LIaPLsumbrvUegDEuBiEQAWsKFiWYJ9yjNkkkDRO4 QMul1rFX451NtQJzkqpMKyeoJIAKEnN/vnaytNYaB3nQknYUKamOUV7O4d14C6LZkZ/V 0sARbPP4hfOx7jsitZ3EUEhCRVNnLvUguoJHuvh1GrsMXue3J6/QOjsfN1EkRwAFi6pR 6SWAOO/C/wfV6Wrp16tyQuN4MsBf5Rhtdfh7WrUA3tPKYNUMU83X+lnXOV5nmNuF2Rhk 6/NtfaDzqsADDi5hTf7Gy/EdDyzO1nZIX5V8Pa4TO1RGM1Wn5u6FAVDOFeFeV0zV7Y6a BOcA== X-Gm-Message-State: APjAAAXgiHHI4wnFa2xNGp7jleELprfxgU0zLPx5b4P8XY1GHiDLPDr7 6yWfNAPPOYcVvpT8i8l0linjCJ8WkL94Cw== X-Google-Smtp-Source: APXvYqx2GQ6P+EskR2qc3OyhjBsICf0qmz5X67me2UmtALIsTzx9NVf1buEbLlgoT14dLKJscHbxFQ== X-Received: by 2002:a1c:ed09:: with SMTP id l9mr5801398wmh.101.1574170316567; Tue, 19 Nov 2019 05:31:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0 Date: Tue, 19 Nov 2019 13:31:44 +0000 Message-Id: <20191119133145.31466-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Armv8-A removes UNPREDICTABLE for R13 for these cases. Signed-off-by: Richard Henderson Message-id: 20191117090621.32425-3-richard.henderson@linaro.org [PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a', since these cases are still UNPREDICTABLE for v8M] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b285b23858e..4d5d4bd8886 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8927,15 +8927,17 @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a) static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) { TCGv_i32 addr; + /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */ + bool v8a =3D ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M); =20 /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rd =3D=3D 15 || a->rn =3D=3D 15 || a->rt =3D=3D 15 || a->rd =3D=3D a->rn || a->rd =3D=3D a->rt - || (s->thumb && (a->rd =3D=3D 13 || a->rt =3D=3D 13)) + || (!v8a && s->thumb && (a->rd =3D=3D 13 || a->rt =3D=3D 13)) || (mop =3D=3D MO_64 && (a->rt2 =3D=3D 15 || a->rd =3D=3D a->rt2 - || (s->thumb && a->rt2 =3D=3D 13)))) { + || (!v8a && s->thumb && a->rt2 =3D=3D 13)))) { unallocated_encoding(s); return true; } @@ -9084,13 +9086,15 @@ static bool trans_STLH(DisasContext *s, arg_STL *a) static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) { TCGv_i32 addr; + /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */ + bool v8a =3D ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M); =20 /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rn =3D=3D 15 || a->rt =3D=3D 15 - || (s->thumb && a->rt =3D=3D 13) + || (!v8a && s->thumb && a->rt =3D=3D 13) || (mop =3D=3D MO_64 && (a->rt2 =3D=3D 15 || a->rt =3D=3D a->rt2 - || (s->thumb && a->rt2 =3D=3D 13)))) { + || (!v8a && s->thumb && a->rt2 =3D=3D 13)))) { unallocated_encoding(s); return true; } --=20 2.20.1 From nobody Mon May 6 14:06:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574170869; cv=none; d=zoho.com; s=zohoarc; b=GShREhxnvPU7+HMxVkz5WqHuZO48fk5Zi9EqKfAQBd81OIJCAHNgPQaiWhkYLqG0pMEwWiQ65jaokRfa3GeAzYU2yaPEu5nQdpgj1HQIdiSMKQRAUIhKZVWZ8Twn3dBWjaCv9FkFZrHzJ/5q6ZlU1FsJw0dxKscbiipARH2nxeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574170869; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RUy3/jS4gGvA/21v++FuloKSRPT5gl3lim3IGVoqAk0=; b=DnbwrndZ7k5RNmrbsmphEiPA5vVCuZs1G0Yk+Algj9EVqm9f7fbJFmr7nuH1BRt/KYSPpkAI2MZq5e6gcmtBGuTdxpXgy6NYYS5rgccitqxyb+ojUip6tmnl7VUkDH43/zqbB9jqqXvjiZ4/5i83hayT/4KHSD+OXlLk+Xt/D4k= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574170869759245.94968464694455; Tue, 19 Nov 2019 05:41:09 -0800 (PST) Received: from localhost ([::1]:45524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3kh-0002pz-9l for importer@patchew.org; Tue, 19 Nov 2019 08:41:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36207) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX3bs-0003S5-Vo for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:32:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX3br-0004Dh-ET for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:32:00 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:36462) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iX3br-0004DP-7n for qemu-devel@nongnu.org; Tue, 19 Nov 2019 08:31:59 -0500 Received: by mail-wm1-x342.google.com with SMTP id c22so3642273wmd.1 for ; Tue, 19 Nov 2019 05:31:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm3094905wmk.23.2019.11.19.05.31.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 05:31:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RUy3/jS4gGvA/21v++FuloKSRPT5gl3lim3IGVoqAk0=; b=iNTTqbjTDV2rliOXYgQ5d8VYGvFqB56R24OD01Z/xwfdp+BS+DO8SfkxNjsPrgrSvD a16N1JV5PycCUJeEBv5eiqXz8idURzYxUH8Su2WLs5Wxao7Eczve6NjZ+vtj/cALirEi k/8voQu+zGOKGjcNJFy+XS0m56m6GQwY7p04SZdxVwTnH0F3o5ahS4lby1a08QdH5cf+ 8IHevVYXzXRH24ubnTNUvCxEX4HCVGwdt5KTy+AbZAoBYDo08FHps+0P2aMpVUYqrYOV 8hqDHqg0x0QIfi7gbY6noHGibiHGowRkF/7EFlO41Gxd2zwmh46mbVNhKFw2ChlkGd75 XwVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RUy3/jS4gGvA/21v++FuloKSRPT5gl3lim3IGVoqAk0=; b=SVnFyJslSpfj0fbfBHoDmM0eHau2uV1RG36uVh+ZwBbYjr39OIKSc6oTWXlxqLdnEV 8MrGgPMUs2ntVFeHrNFfA9qProlzJfYNA2vibniLC6hWbpgtT7iPHR70aSopTUf6TmpN UZFAR4uzMg+36CB7Mgegwu0aoC0RwmmCx1EaC8S1IPuQHuSzDXqnsBKnrkcfqHqCTlYl rhiinFUhCkuwc9gX+rT2Rxe+kzAxAxAfi1jxPTu1JpL4mxHfLAQ9cP6Lp7+wff/kT9vw teFQixk04plQsonj4QL0RkZXE+GrBydlAg1QYTeAbxrhmdi1Do/EYgORYAKVP8o0N+cZ rDDA== X-Gm-Message-State: APjAAAWzQTOUqF0oPqTuqLQulSlOBl5A0zVqmzxIioBLyhso35O8Uk/z STZIYoSsx5RcqxEKvIdhMhCS44jS+7mdOw== X-Google-Smtp-Source: APXvYqwajMwh5hvVfo2dtijfk3XgyKWe9Vtk8ztxPWWr4aRHlScwXX7uIUS3PGXaZMRCSuHWE+uRDw== X-Received: by 2002:a7b:cf0e:: with SMTP id l14mr5877718wmg.149.1574170317880; Tue, 19 Nov 2019 05:31:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY Date: Tue, 19 Nov 2019 13:31:45 +0000 Message-Id: <20191119133145.31466-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org> References: <20191119133145.31466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Simply moving the non-stub helper_v7m_mrs/msr outside of !CONFIG_USER_ONLY is not an option, because of all of the other system-mode helpers that are called. But we can split out a few subroutines to handle the few EL0 accessible registers without duplicating code. Reported-by: Christophe Lyon Signed-off-by: Richard Henderson Message-id: 20191118194916.3670-1-richard.henderson@linaro.org [PMM: deleted now-redundant comment; added a default case to switch in v7m_msr helper] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 + target/arm/m_helper.c | 114 ++++++++++++++++++++++++++---------------- 2 files changed, 73 insertions(+), 43 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47d24a53758..83a809d4bac 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1314,6 +1314,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) if (mask & XPSR_GE) { env->GE =3D (val & XPSR_GE) >> 16; } +#ifndef CONFIG_USER_ONLY if (mask & XPSR_T) { env->thumb =3D ((val & XPSR_T) !=3D 0); } @@ -1329,6 +1330,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) /* Note that this only happens on exception exit */ write_v7m_exception(env, val & XPSR_EXCP); } +#endif } =20 #define HCR_VM (1ULL << 0) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index f2512e448e2..4a48b792520 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -33,22 +33,82 @@ #include "exec/cpu_ldst.h" #endif =20 +static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, + uint32_t reg, uint32_t val) +{ + /* Only APSR is actually writable */ + if (!(reg & 4)) { + uint32_t apsrmask =3D 0; + + if (mask & 8) { + apsrmask |=3D XPSR_NZCV | XPSR_Q; + } + if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + apsrmask |=3D XPSR_GE; + } + xpsr_write(env, val, apsrmask); + } +} + +static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) +{ + uint32_t mask =3D 0; + + if ((reg & 1) && el) { + mask |=3D XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ + } + if (!(reg & 4)) { + mask |=3D XPSR_NZCV | XPSR_Q; /* APSR */ + if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + mask |=3D XPSR_GE; + } + } + /* EPSR reads as zero */ + return xpsr_read(env) & mask; +} + +static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +{ + uint32_t value =3D env->v7m.control[secure]; + + if (!secure) { + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ + value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; + } + return value; +} + #ifdef CONFIG_USER_ONLY =20 -/* These should probably raise undefined insn exceptions. */ -void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) { - ARMCPU *cpu =3D env_archcpu(env); + uint32_t mask =3D extract32(maskreg, 8, 4); + uint32_t reg =3D extract32(maskreg, 0, 8); =20 - cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + v7m_msr_xpsr(env, mask, reg, val); + break; + case 20: /* CONTROL */ + /* There are no sub-fields that are actually writable from EL0. */ + break; + default: + /* Unprivileged writes to other registers are ignored */ + break; + } } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu =3D env_archcpu(env); - - cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); - return 0; + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + return v7m_mrs_xpsr(env, reg, 0); + case 20: /* CONTROL */ + return v7m_mrs_control(env, 0); + default: + /* Unprivileged reads others as zero. */ + return 0; + } } =20 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) @@ -2196,35 +2256,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - uint32_t mask; unsigned el =3D arm_current_el(env); =20 /* First handle registers which unprivileged can read */ - switch (reg) { case 0 ... 7: /* xPSR sub-fields */ - mask =3D 0; - if ((reg & 1) && el) { - mask |=3D XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ - } - if (!(reg & 4)) { - mask |=3D XPSR_NZCV | XPSR_Q; /* APSR */ - if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - mask |=3D XPSR_GE; - } - } - /* EPSR reads as zero */ - return xpsr_read(env) & mask; - break; + return v7m_mrs_xpsr(env, reg, el); case 20: /* CONTROL */ - { - uint32_t value =3D env->v7m.control[env->v7m.secure]; - if (!env->v7m.secure) { - /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank = */ - value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; - } - return value; - } + return v7m_mrs_control(env, env->v7m.secure); case 0x94: /* CONTROL_NS */ /* * We have to handle this here because unprivileged Secure code @@ -2454,18 +2493,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mask= reg, uint32_t val) =20 switch (reg) { case 0 ... 7: /* xPSR sub-fields */ - /* only APSR is actually writable */ - if (!(reg & 4)) { - uint32_t apsrmask =3D 0; - - if (mask & 8) { - apsrmask |=3D XPSR_NZCV | XPSR_Q; - } - if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - apsrmask |=3D XPSR_GE; - } - xpsr_write(env, val, apsrmask); - } + v7m_msr_xpsr(env, mask, reg, val); break; case 8: /* MSP */ if (v7m_using_psp(env)) { --=20 2.20.1