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Mon, 18 Nov 2019 22:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574116094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s3cor6biQmpqn+tnJ2B55PoWtsVtFws5bfkkg9apAew=; b=PBhkQEmc1IV0DDh4fP0g4uXEfjvPQLB2aSwWzeTLbVZJpAHAQUOC+n7UWt+1HPav7GiSON T4eXjd+j3O1FNJb4ROOg7zfETLXcONJnwkGtM4z7COD6YLNYR2Z9OTzmZn7RDIUId/Lx7/ XtdlbwhnImHW18KB3yikux6rnjw7jpM= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eric Blake , qemu-devel@nongnu.org Subject: [PATCH v4 2/2] hw/mips/gt64xxx: Remove dynamic field width from trace events Date: Mon, 18 Nov 2019 23:27:46 +0100 Message-Id: <20191118222746.31467-3-philmd@redhat.com> In-Reply-To: <20191118222746.31467-1-philmd@redhat.com> References: <20191118222746.31467-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: FFQvbAFaNp2tf0DGhSjv0Q-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stefan Hajnoczi , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Aleksandar Markovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. We previously passed to the trace API 'width << 1' as the number of hex characters to display (the dynamic field width). We don't need this anymore. Instead, display the size of bytes accessed. Fixes: ab6bff424f (gt64xxx_pci: Convert debug printf to trace events) Reported-by: Eric Blake Reviewed-by: Eric Blake Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Do not update qemu_log_mask() v3: display size (in byte) v4: added Fixes/Reviewed-by --- hw/mips/gt64xxx_pci.c | 16 ++++++++-------- hw/mips/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 5cab9c1ee1..f1af840d8e 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] =3D ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |=3D !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size << 1, val); + trace_gt64120_write("INTRCAUSE", size, val); break; case GT_INTRMASK: s->regs[saddr] =3D val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size << 1, val); + trace_gt64120_write("INTRMASK", size, val); break; case GT_PCI0_ICMASK: s->regs[saddr] =3D val & 0x03fffffe; - trace_gt64120_write("ICMASK", size << 1, val); + trace_gt64120_write("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] =3D val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size << 1, val); + trace_gt64120_write("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ @@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val =3D s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size << 1, val); + trace_gt64120_read("INTRCAUSE", size, val); break; case GT_INTRMASK: val =3D s->regs[saddr]; - trace_gt64120_read("INTRMASK", size << 1, val); + trace_gt64120_read("INTRMASK", size, val); break; case GT_PCI0_ICMASK: val =3D s->regs[saddr]; - trace_gt64120_read("ICMASK", size << 1, val); + trace_gt64120_read("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: val =3D s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size << 1, val); + trace_gt64120_read("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 75d4c73f2e..321933283f 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx.c -gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read= %s value:0x%0*" PRIx64 -gt64120_write(const char *regname, int width, uint64_t value) "gt64120 wri= te %s value:0x%0*" PRIx64 +gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 = read %s size:%u value:0x%08" PRIx64 +gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120= write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_le= ngth, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRI= x64 "@0x%08" PRIx64 --=20 2.21.0