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Mon, 18 Nov 2019 22:28:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574116087; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4itkHR8Go/BDN6vF/27uI1YXhWrNkloPForQl9ZQ3s4=; b=OfIlGPTetdRhCYPYzN3U49WhLJSlBwnhEx17O/CDFpF2Rkbc8A/cwg8Yup0fhtX3mbNhHn HoDXb4/MenGwpW/Ikg+0liHD/QZvOMLjeQQJU5L0Z7LlLCwYj+06W5/56c6kT22+eWPVmf EVocyKxYtoHYMi46GAUJPvk2rRB2hWg= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eric Blake , qemu-devel@nongnu.org Subject: [PATCH v4 1/2] hw/block/pflash: Remove dynamic field width from trace events Date: Mon, 18 Nov 2019 23:27:45 +0100 Message-Id: <20191118222746.31467-2-philmd@redhat.com> In-Reply-To: <20191118222746.31467-1-philmd@redhat.com> References: <20191118222746.31467-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: 1jTba2gPOlu2KfInRZzodQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stefan Hajnoczi , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Aleksandar Markovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. We previously passed to the trace API 'width << 1' as the number of hex characters to display (the dynamic field width). We don't need this anymore. Instead, display the size of bytes accessed. Fixes: e8aa2d95ea (pflash: Simplify trace_pflash_io_read/write) Fixes: c1474acd5d (pflash: Simplify trace_pflash_data_read/write) Reported-by: Eric Blake Reviewed-by: Eric Blake Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v3: display size (in byte) v4: added Fixes/Reviewed-by --- hw/block/pflash_cfi01.c | 8 ++++---- hw/block/pflash_cfi02.c | 8 ++++---- hw/block/trace-events | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 566c0acb77..54e6ebd385 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -276,7 +276,7 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwad= dr offset, DPRINTF("BUG in %s\n", __func__); abort(); } - trace_pflash_data_read(offset, width << 1, ret); + trace_pflash_data_read(offset, width, ret); return ret; } =20 @@ -389,7 +389,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr of= fset, =20 break; } - trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wc= ycle); + trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle); =20 return ret; } @@ -414,7 +414,7 @@ static inline void pflash_data_write(PFlashCFI01 *pfl, = hwaddr offset, { uint8_t *p =3D pfl->storage; =20 - trace_pflash_data_write(offset, width << 1, value, pfl->counter); + trace_pflash_data_write(offset, width, value, pfl->counter); switch (width) { case 1: p[offset] =3D value; @@ -453,7 +453,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offse= t, =20 cmd =3D value; =20 - trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); + trace_pflash_io_write(offset, width, value, pfl->wcycle); if (!pfl->wcycle) { /* Set the device in I/O access mode */ memory_region_rom_device_set_romd(&pfl->mem, false); diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 4baca701b7..c7d92c3e79 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -260,7 +260,7 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwad= dr offset, { uint8_t *p =3D (uint8_t *)pfl->storage + offset; uint64_t ret =3D pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); - trace_pflash_data_read(offset, width << 1, ret); + trace_pflash_data_read(offset, width, ret); return ret; } =20 @@ -385,7 +385,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset= , unsigned int width) } break; } - trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wc= ycle); + trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle); =20 return ret; } @@ -432,7 +432,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, uint8_t *p; uint8_t cmd; =20 - trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); + trace_pflash_io_write(offset, width, value, pfl->wcycle); cmd =3D value; if (pfl->cmd !=3D 0xA0) { /* Reset does nothing during chip erase and sector erase. */ @@ -542,7 +542,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, } goto reset_flash; } - trace_pflash_data_write(offset, width << 1, value, 0); + trace_pflash_data_write(offset, width, value, 0); if (!pfl->ro) { p =3D (uint8_t *)pfl->storage + offset; if (pfl->be) { diff --git a/hw/block/trace-events b/hw/block/trace-events index 13d1b21dd4..c03e80c2c9 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -8,10 +8,10 @@ fdc_ioport_write(uint8_t reg, uint8_t value) "write reg 0= x%02x val 0x%02x" # pflash_cfi01.c pflash_reset(void) "reset" pflash_timer_expired(uint8_t cmd) "command 0x%02x done" -pflash_io_read(uint64_t offset, int width, int fmt_width, uint32_t value, = uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x cm= d:0x%02x wcycle:%u" -pflash_io_write(uint64_t offset, int width, int fmt_width, uint32_t value,= uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x wcycle:%u" -pflash_data_read(uint64_t offset, int width, uint32_t value) "data offset:= 0x%04"PRIx64" value:0x%0*x" -pflash_data_write(uint64_t offset, int width, uint32_t value, uint64_t cou= nter) "data offset:0x%04"PRIx64" value:0x%0*x counter:0x%016"PRIx64 +pflash_io_read(uint64_t offset, unsigned size, uint32_t value, uint8_t cmd= , uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x cmd:0x%02x wcy= cle:%u" +pflash_io_write(uint64_t offset, unsigned size, uint32_t value, uint8_t wc= ycle) "offset:0x%04"PRIx64" size:%u value:0x%04x wcycle:%u" +pflash_data_read(uint64_t offset, unsigned size, uint32_t value) "data off= set:0x%04"PRIx64" size:%u value:0x%04x" +pflash_data_write(uint64_t offset, unsigned size, uint32_t value, uint64_t= counter) "data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PR= Ix64 pflash_manufacturer_id(uint16_t id) "Read Manufacturer ID: 0x%04x" pflash_device_id(uint16_t id) "Read Device ID: 0x%04x" pflash_device_info(uint64_t offset) "Read Device Information offset:0x%04"= PRIx64 --=20 2.21.0 From nobody Fri May 3 16:25:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 18 Nov 2019 17:28:16 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-146-FFQvbAFaNp2tf0DGhSjv0Q-1; Mon, 18 Nov 2019 17:28:10 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9DBAA107ACC7; Mon, 18 Nov 2019 22:28:09 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.206.9]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AB58A27067; Mon, 18 Nov 2019 22:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574116094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s3cor6biQmpqn+tnJ2B55PoWtsVtFws5bfkkg9apAew=; b=PBhkQEmc1IV0DDh4fP0g4uXEfjvPQLB2aSwWzeTLbVZJpAHAQUOC+n7UWt+1HPav7GiSON T4eXjd+j3O1FNJb4ROOg7zfETLXcONJnwkGtM4z7COD6YLNYR2Z9OTzmZn7RDIUId/Lx7/ XtdlbwhnImHW18KB3yikux6rnjw7jpM= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Eric Blake , qemu-devel@nongnu.org Subject: [PATCH v4 2/2] hw/mips/gt64xxx: Remove dynamic field width from trace events Date: Mon, 18 Nov 2019 23:27:46 +0100 Message-Id: <20191118222746.31467-3-philmd@redhat.com> In-Reply-To: <20191118222746.31467-1-philmd@redhat.com> References: <20191118222746.31467-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: FFQvbAFaNp2tf0DGhSjv0Q-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stefan Hajnoczi , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Aleksandar Markovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. We previously passed to the trace API 'width << 1' as the number of hex characters to display (the dynamic field width). We don't need this anymore. Instead, display the size of bytes accessed. Fixes: ab6bff424f (gt64xxx_pci: Convert debug printf to trace events) Reported-by: Eric Blake Reviewed-by: Eric Blake Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Do not update qemu_log_mask() v3: display size (in byte) v4: added Fixes/Reviewed-by --- hw/mips/gt64xxx_pci.c | 16 ++++++++-------- hw/mips/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 5cab9c1ee1..f1af840d8e 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] =3D ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |=3D !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size << 1, val); + trace_gt64120_write("INTRCAUSE", size, val); break; case GT_INTRMASK: s->regs[saddr] =3D val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size << 1, val); + trace_gt64120_write("INTRMASK", size, val); break; case GT_PCI0_ICMASK: s->regs[saddr] =3D val & 0x03fffffe; - trace_gt64120_write("ICMASK", size << 1, val); + trace_gt64120_write("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] =3D val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size << 1, val); + trace_gt64120_write("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ @@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val =3D s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size << 1, val); + trace_gt64120_read("INTRCAUSE", size, val); break; case GT_INTRMASK: val =3D s->regs[saddr]; - trace_gt64120_read("INTRMASK", size << 1, val); + trace_gt64120_read("INTRMASK", size, val); break; case GT_PCI0_ICMASK: val =3D s->regs[saddr]; - trace_gt64120_read("ICMASK", size << 1, val); + trace_gt64120_read("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: val =3D s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size << 1, val); + trace_gt64120_read("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 75d4c73f2e..321933283f 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx.c -gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read= %s value:0x%0*" PRIx64 -gt64120_write(const char *regname, int width, uint64_t value) "gt64120 wri= te %s value:0x%0*" PRIx64 +gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 = read %s size:%u value:0x%08" PRIx64 +gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120= write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_le= ngth, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRI= x64 "@0x%08" PRIx64 --=20 2.21.0