From nobody Mon Apr 29 12:26:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1574106633; cv=none; d=zoho.com; s=zohoarc; b=XpsgZOQ8t4oPpbufVVEfiMEs7cvzrYPR/n3m1LI+d4+fRFWJt7pOLB8KW3HV4J/niG1x0/b36d2uwS/YexBONaTj/f7qBuilWP+n2U+aBLywE2kRwfNwWrxmLA4JLco05R0jfIuTpOFv+JiHLuniddEevAvl9bbdunG6ZHwV7VE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574106633; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To; bh=hy8AwwwRhcrOoH/uMIh484CtIC6iFhWhD40R46HV2o0=; b=LWgQkB1KRl0ZoK7aG7UskkizEZnEZLXftfgq+osjvI4oOMGCMC7oam6onfRSpAhYIOKy/KkaVUr+yfdWlvZgfsOddUkUf2r12BLJmjZgx9sgAm8HP6uSLW4SWTZj7bNTPA+mZxWUH9UOfwFGIaZ4PtQM7keKgr5Tuy0Qq28xabQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574106633242214.11384060227135; Mon, 18 Nov 2019 11:50:33 -0800 (PST) Received: from localhost ([::1]:38598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iWn2d-0006oO-DG for importer@patchew.org; Mon, 18 Nov 2019 14:50:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50434) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iWn1o-00069d-U3 for qemu-devel@nongnu.org; Mon, 18 Nov 2019 14:49:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iWn1l-0001Qm-BL for qemu-devel@nongnu.org; Mon, 18 Nov 2019 14:49:39 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42421) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iWn1l-0001Ps-0L for qemu-devel@nongnu.org; Mon, 18 Nov 2019 14:49:37 -0500 Received: by mail-wr1-x443.google.com with SMTP id a15so20979034wrf.9 for ; Mon, 18 Nov 2019 11:49:36 -0800 (PST) Received: from localhost.localdomain (65.red-79-149-41.dynamicip.rima-tde.net. [79.149.41.65]) by smtp.gmail.com with ESMTPSA id h205sm468305wmf.35.2019.11.18.11.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 11:49:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=hy8AwwwRhcrOoH/uMIh484CtIC6iFhWhD40R46HV2o0=; b=vNb874vrVy4qrqGytpsNoMu1YStU8ZbVlsm8sQKr0Hl3lr4rrl+lR2tP7b8kJfBNu0 IuNPmgIvcfRwTfnlfTenKaoBg4+BqHUWyIcnA20gUv/dVVp+HkL+8RaBomHQV0Qqt93B 6LaOHwmL7Bcv5siaTkfHsVYjqGccDbQ5hp6iw+XMD+zsbhgdZ1bgxa7GyQTaqfdAyrKS NelDm5aqR3fcNxF63cEzjbhRZsLAfuhOEN22fiN85Avj8vsXjaMpi7j8kmfjPsxCxL2S WmpTMDl0ZBW7vOz0W1we7bYeCsQ4jliH5z6CEYvRjeke7uo2iC8rtVp2dBsfzxbG9M7r T6hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=hy8AwwwRhcrOoH/uMIh484CtIC6iFhWhD40R46HV2o0=; b=J9riGzanrrdBMppsqIYWRsDIX4ZHS861Gc6Gggj1RJiYOOzBifdTUqO2+fPGwVu5ZN ZzmqfKDAk0+37yhSWjXTyeKG57l+DNwYnL0escLQRkq+3wwdXtl2QZ5KywJpVGHpO78r w4XNT2zxykCHNL92Cgz5EdV6BEzqpHyOqYZha0825GpCO0GUCxFj9lchAaEAitlmYXmH cab900vDEN6C8rwq/Xj/YlqBWUY/qjJv7y/7uCXmvnVSouwR1y2RJPmnzVDkU59MBgrI 53fPzrGz08OIM+OxwEy2vO2UwSfdYYAK5iNkbzXnhs+1suIcLAzHBnaiNBdoi0aJ3kt+ jEag== X-Gm-Message-State: APjAAAUV3/ToIFZROddR5rzHoHg/m+1ptG50nBkKNEqd2HRWakdMGlQ6 fqI+9ZCBtmBcmODO05IduTkjQqYtbBLOTg== X-Google-Smtp-Source: APXvYqxYpft5v7ph+TbXwp88Y7mjzoBVdqvQ9HHS4p7Ej+03XbbISBo24W+J5wru0WNlAo8H41PfUg== X-Received: by 2002:a5d:4445:: with SMTP id x5mr34510879wrr.341.1574106573135; Mon, 18 Nov 2019 11:49:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-4.2] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY Date: Mon, 18 Nov 2019 20:49:16 +0100 Message-Id: <20191118194916.3670-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, christophe.lyon@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Simply moving the non-stub helper_v7m_mrs/msr outside of !CONFIG_USER_ONLY is not an option, because of all of the other system-mode helpers that are called. But we can split out a few subroutines to handle the few EL0 accessible registers without duplicating code. Reported-by: Christophe Lyon Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 + target/arm/m_helper.c | 110 ++++++++++++++++++++++++++---------------- 2 files changed, 70 insertions(+), 42 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e1a66a2d1c..81f5b5b75f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1317,6 +1317,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) if (mask & XPSR_GE) { env->GE =3D (val & XPSR_GE) >> 16; } +#ifndef CONFIG_USER_ONLY if (mask & XPSR_T) { env->thumb =3D ((val & XPSR_T) !=3D 0); } @@ -1332,6 +1333,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) /* Note that this only happens on exception exit */ write_v7m_exception(env, val & XPSR_EXCP); } +#endif } =20 #define HCR_VM (1ULL << 0) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index f2512e448e..7c7e8eb62c 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -33,22 +33,80 @@ #include "exec/cpu_ldst.h" #endif =20 +static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, + uint32_t reg, uint32_t val) +{ + /* Only APSR is actually writable */ + if (!(reg & 4)) { + uint32_t apsrmask =3D 0; + + if (mask & 8) { + apsrmask |=3D XPSR_NZCV | XPSR_Q; + } + if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + apsrmask |=3D XPSR_GE; + } + xpsr_write(env, val, apsrmask); + } +} + +static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) +{ + uint32_t mask =3D 0; + + if ((reg & 1) && el) { + mask |=3D XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ + } + if (!(reg & 4)) { + mask |=3D XPSR_NZCV | XPSR_Q; /* APSR */ + if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + mask |=3D XPSR_GE; + } + } + /* EPSR reads as zero */ + return xpsr_read(env) & mask; +} + +static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +{ + uint32_t value =3D env->v7m.control[secure]; + + if (!secure) { + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ + value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; + } + return value; +} + #ifdef CONFIG_USER_ONLY =20 /* These should probably raise undefined insn exceptions. */ -void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) { - ARMCPU *cpu =3D env_archcpu(env); + uint32_t mask =3D extract32(maskreg, 8, 4); + uint32_t reg =3D extract32(maskreg, 0, 8); =20 - cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + v7m_msr_xpsr(env, mask, reg, val); + break; + case 20: /* CONTROL */ + /* There are no sub-fields that are actually writable from EL0. */ + break; + } } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu =3D env_archcpu(env); - - cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); - return 0; + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + return v7m_mrs_xpsr(env, reg, 0); + case 20: /* CONTROL */ + return v7m_mrs_control(env, 0); + default: + /* Unprivileged reads others as zero. */ + return 0; + } } =20 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) @@ -2196,35 +2254,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - uint32_t mask; unsigned el =3D arm_current_el(env); =20 /* First handle registers which unprivileged can read */ - switch (reg) { case 0 ... 7: /* xPSR sub-fields */ - mask =3D 0; - if ((reg & 1) && el) { - mask |=3D XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ - } - if (!(reg & 4)) { - mask |=3D XPSR_NZCV | XPSR_Q; /* APSR */ - if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - mask |=3D XPSR_GE; - } - } - /* EPSR reads as zero */ - return xpsr_read(env) & mask; - break; + return v7m_mrs_xpsr(env, reg, el); case 20: /* CONTROL */ - { - uint32_t value =3D env->v7m.control[env->v7m.secure]; - if (!env->v7m.secure) { - /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank = */ - value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; - } - return value; - } + return v7m_mrs_control(env, env->v7m.secure); case 0x94: /* CONTROL_NS */ /* * We have to handle this here because unprivileged Secure code @@ -2454,18 +2491,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mask= reg, uint32_t val) =20 switch (reg) { case 0 ... 7: /* xPSR sub-fields */ - /* only APSR is actually writable */ - if (!(reg & 4)) { - uint32_t apsrmask =3D 0; - - if (mask & 8) { - apsrmask |=3D XPSR_NZCV | XPSR_Q; - } - if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - apsrmask |=3D XPSR_GE; - } - xpsr_write(env, val, apsrmask); - } + v7m_msr_xpsr(env, mask, reg, val); break; case 8: /* MSP */ if (v7m_using_psp(env)) { --=20 2.17.1