[PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests

Cédric Le Goater posted 23 patches 4 years, 4 months ago
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include/hw/ppc/pnv.h       |  15 ++
include/hw/ppc/pnv_xive.h  |   3 -
include/hw/ppc/xive.h      |  72 ++++++--
include/hw/ppc/xive_regs.h |  24 +++
hw/intc/pnv_xive.c         | 360 ++++++++++++++++++++++++-------------
hw/intc/spapr_xive.c       |  88 ++++++++-
hw/intc/xive.c             | 350 ++++++++++++++++++++----------------
hw/ppc/pnv.c               |  37 +++-
hw/ppc/spapr.c             |  36 ++++
9 files changed, 691 insertions(+), 294 deletions(-)
[PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests
Posted by Cédric Le Goater 4 years, 4 months ago
Hello,

The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
acts as an hypervisor (L0). Supporting emulation of KVM to run guests
(L1) requires a few more extensions, among which guest support for the
XIVE interrupt controller on POWER9 processor.

The following changes extend the XIVE models with the new XiveFabric
and XivePresenter interfaces to provide support for XIVE escalations
and interrupt resend. This mechanism is used by XIVE to notify the
hypervisor that a vCPU is not dispatched on a HW thread. Tested on a
QEMU PowerNV machine and a simple QEMU pseries guest doing network on
a local bridge.

The XIVE interrupt controller offers a way to increase the XIVE
resources per chip by configuring multiple XIVE blocks on a chip. This
is not currently supported by the model. However, some configurations,
such as OPAL/skiboot, use one block-per-chip configuration with some
optimizations. One of them is to override the hardwired chip ID by the
block id in the PowerBUS operations and for CAM line compares. This
patchset improves the support for this setup. Tested with 4 chips.

A series from Suraj adding guest support in the Radix MMU model of the
QEMU PowerNV machine is still required and will be send later. The
whole patchset can be found under :

  https://github.com/legoater/qemu/tree/powernv-4.2

Based on top of Greg's patchset "ppc: Consolidate QOM links and
pointers to the same object".

Thanks,

C.

Changes since v4:

 - rebased on QEMU 4.2-rc1
 - better commit logs
 - moved fixes at the beginning of the patchset
 - reworked pnv_xive_match_nvt() handler to loop on the all threads of
   a PnvChip

Changes since v3:

 - reworked the patches introducing the XiveFabric and XivePresenter
   interfaces
 - moved the get_block_id() handler to the XiveRouter
 - new small addons related to the format of the trigger data
 
Changes since v2:

 - introduced the XiveFabric and XivePresenter interfaces
 - removed the need of a XiveRouter pointer under XiveTCTX

Changes since v1:

 - minor extra fixes 
 - split the escalation support in different patches
 - kept the XiveRouter type for XiveTCTX back pointer (will address
   this in P10)
 - removed pnv_xive_vst_size(). Really broken on indirect tables.
 - improved the dump of the NVT table
 - introduce pnv_xive_get_block_id()

Cédric Le Goater (23):
  ppc/xive: Record the IPB in the associated NVT
  ppc/xive: Introduce helpers for the NVT id
  ppc/pnv: Remove pnv_xive_vst_size() routine
  ppc/pnv: Dump the XIVE NVT table
  ppc/pnv: Quiesce some XIVE errors
  ppc/xive: Introduce OS CAM line helpers
  ppc/xive: Check V bit in TM_PULL_POOL_CTX
  ppc/xive: Introduce a XivePresenter interface
  ppc/xive: Implement the XivePresenter interface
  ppc/pnv: Loop on the threads of the chip to find a matching NVT
  ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
  ppc/xive: Introduce a XiveFabric interface
  ppc/pnv: Implement the XiveFabric interface
  ppc/spapr: Implement the XiveFabric interface
  ppc/xive: Use the XiveFabric and XivePresenter interfaces
  ppc/xive: Extend the TIMA operation with a XivePresenter parameter
  ppc/pnv: Clarify how the TIMA is accessed on a multichip system
  ppc/xive: Move the TIMA operations to the controller model
  ppc/xive: Remove the get_tctx() XiveRouter handler
  ppc/xive: Introduce a xive_tctx_ipb_update() helper
  ppc/xive: Synthesize interrupt from the saved IPB in the NVT
  ppc/pnv: Introduce a pnv_xive_block_id() helper
  ppc/pnv: Extend XiveRouter with a get_block_id() handler

 include/hw/ppc/pnv.h       |  15 ++
 include/hw/ppc/pnv_xive.h  |   3 -
 include/hw/ppc/xive.h      |  72 ++++++--
 include/hw/ppc/xive_regs.h |  24 +++
 hw/intc/pnv_xive.c         | 360 ++++++++++++++++++++++++-------------
 hw/intc/spapr_xive.c       |  88 ++++++++-
 hw/intc/xive.c             | 350 ++++++++++++++++++++----------------
 hw/ppc/pnv.c               |  37 +++-
 hw/ppc/spapr.c             |  36 ++++
 9 files changed, 691 insertions(+), 294 deletions(-)

-- 
2.21.0


Re: [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests
Posted by Cédric Le Goater 4 years, 4 months ago
On 15/11/2019 17:24, Cédric Le Goater wrote:
> Hello,
> 
> The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
> acts as an hypervisor (L0). Supporting emulation of KVM to run guests
> (L1) requires a few more extensions, among which guest support for the
> XIVE interrupt controller on POWER9 processor.
> 
> The following changes extend the XIVE models with the new XiveFabric
> and XivePresenter interfaces to provide support for XIVE escalations
> and interrupt resend. This mechanism is used by XIVE to notify the
> hypervisor that a vCPU is not dispatched on a HW thread. Tested on a
> QEMU PowerNV machine and a simple QEMU pseries guest doing network on
> a local bridge.
> 
> The XIVE interrupt controller offers a way to increase the XIVE
> resources per chip by configuring multiple XIVE blocks on a chip. This
> is not currently supported by the model. However, some configurations,
> such as OPAL/skiboot, use one block-per-chip configuration with some
> optimizations. One of them is to override the hardwired chip ID by the
> block id in the PowerBUS operations and for CAM line compares. This
> patchset improves the support for this setup. Tested with 4 chips.
> 
> A series from Suraj adding guest support in the Radix MMU model of the
> QEMU PowerNV machine is still required and will be send later. The
> whole patchset can be found under :
> 
>   https://github.com/legoater/qemu/tree/powernv-4.2


 [ ... ]

> Cédric Le Goater (23):
>   ppc/xive: Record the IPB in the associated NVT
>   ppc/xive: Introduce helpers for the NVT id
>   ppc/pnv: Remove pnv_xive_vst_size() routine
>   ppc/pnv: Dump the XIVE NVT table
>   ppc/pnv: Quiesce some XIVE errors
>   ppc/xive: Introduce OS CAM line helpers
>   ppc/xive: Check V bit in TM_PULL_POOL_CTX
>   ppc/xive: Introduce a XivePresenter interface
>   ppc/xive: Implement the XivePresenter interface

David,

I have reworked the following patches to address Greg's comments 
and your comment on "ppc/pnv: Dump the XIVE NVT table". 

Shall I wait for some feedback from you or just resend ? 

Thanks,

C.

>   ppc/pnv: Loop on the threads of the chip to find a matching NVT
>   ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
>   ppc/xive: Introduce a XiveFabric interface
>   ppc/pnv: Implement the XiveFabric interface
>   ppc/spapr: Implement the XiveFabric interface
>   ppc/xive: Use the XiveFabric and XivePresenter interfaces
>   ppc/xive: Extend the TIMA operation with a XivePresenter parameter
>   ppc/pnv: Clarify how the TIMA is accessed on a multichip system
>   ppc/xive: Move the TIMA operations to the controller model
>   ppc/xive: Remove the get_tctx() XiveRouter handler
>   ppc/xive: Introduce a xive_tctx_ipb_update() helper
>   ppc/xive: Synthesize interrupt from the saved IPB in the NVT
>   ppc/pnv: Introduce a pnv_xive_block_id() helper
>   ppc/pnv: Extend XiveRouter with a get_block_id() handler
> 
>  include/hw/ppc/pnv.h       |  15 ++
>  include/hw/ppc/pnv_xive.h  |   3 -
>  include/hw/ppc/xive.h      |  72 ++++++--
>  include/hw/ppc/xive_regs.h |  24 +++
>  hw/intc/pnv_xive.c         | 360 ++++++++++++++++++++++++-------------
>  hw/intc/spapr_xive.c       |  88 ++++++++-
>  hw/intc/xive.c             | 350 ++++++++++++++++++++----------------
>  hw/ppc/pnv.c               |  37 +++-
>  hw/ppc/spapr.c             |  36 ++++
>  9 files changed, 691 insertions(+), 294 deletions(-)
> 


Re: [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests
Posted by David Gibson 4 years, 4 months ago
On Fri, Nov 22, 2019 at 07:17:05PM +0100, Cédric Le Goater wrote:
> On 15/11/2019 17:24, Cédric Le Goater wrote:
> > Hello,
> > 
> > The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
> > acts as an hypervisor (L0). Supporting emulation of KVM to run guests
> > (L1) requires a few more extensions, among which guest support for the
> > XIVE interrupt controller on POWER9 processor.
> > 
> > The following changes extend the XIVE models with the new XiveFabric
> > and XivePresenter interfaces to provide support for XIVE escalations
> > and interrupt resend. This mechanism is used by XIVE to notify the
> > hypervisor that a vCPU is not dispatched on a HW thread. Tested on a
> > QEMU PowerNV machine and a simple QEMU pseries guest doing network on
> > a local bridge.
> > 
> > The XIVE interrupt controller offers a way to increase the XIVE
> > resources per chip by configuring multiple XIVE blocks on a chip. This
> > is not currently supported by the model. However, some configurations,
> > such as OPAL/skiboot, use one block-per-chip configuration with some
> > optimizations. One of them is to override the hardwired chip ID by the
> > block id in the PowerBUS operations and for CAM line compares. This
> > patchset improves the support for this setup. Tested with 4 chips.
> > 
> > A series from Suraj adding guest support in the Radix MMU model of the
> > QEMU PowerNV machine is still required and will be send later. The
> > whole patchset can be found under :
> > 
> >   https://github.com/legoater/qemu/tree/powernv-4.2
> 
> 
>  [ ... ]
> 
> > Cédric Le Goater (23):
> >   ppc/xive: Record the IPB in the associated NVT
> >   ppc/xive: Introduce helpers for the NVT id
> >   ppc/pnv: Remove pnv_xive_vst_size() routine
> >   ppc/pnv: Dump the XIVE NVT table
> >   ppc/pnv: Quiesce some XIVE errors
> >   ppc/xive: Introduce OS CAM line helpers
> >   ppc/xive: Check V bit in TM_PULL_POOL_CTX
> >   ppc/xive: Introduce a XivePresenter interface
> >   ppc/xive: Implement the XivePresenter interface
> 
> David,
> 
> I have reworked the following patches to address Greg's comments 
> and your comment on "ppc/pnv: Dump the XIVE NVT table". 
> 
> Shall I wait for some feedback from you or just resend ?

Just resend, thanks.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson