From nobody Tue Feb 10 01:58:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1573805107; cv=none; d=zoho.com; s=zohoarc; b=mVru1ChANQeMLL6EVlQ9Jkb5yXDp6xXWd8s1cchxYHnY1TpAuN88qh1YF7PGbRT+Qdd5gbx+G0ICfzKR42fQAG0AumV5wb/Hvlp2EGsbc+LWi8oIfnzJOduo+a+O9gsccaxV5uAXwnq9ZD6JJMtMMwVYCplhRinWo4JTYMgdzYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1573805107; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aZerloXXnN7mzZjg0lFVVDHdcuIXVUU0Wjpta75T27s=; b=YEkSaLmPtkw0K4R3//jXXSRD76Yh3GkVuf1j5YLKMoC9Y+783khezSGEIKwh2qUvKeAco9OKn9RZvKCa+csnRnQE16srQdt2FQIucAggtHLkMU3e8yRozwmI/gs/o40TOZKZbb75ysfFbyV+oEmHCaXmAii9d3a7ssv7pd7DeKE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1573805107374396.2746991672707; Fri, 15 Nov 2019 00:05:07 -0800 (PST) Received: from localhost ([::1]:36432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iVWbG-00079O-Ib for importer@patchew.org; Fri, 15 Nov 2019 03:05:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iVWQu-0005ws-T5 for qemu-devel@nongnu.org; Fri, 15 Nov 2019 02:54:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iVWQs-0002oK-BL for qemu-devel@nongnu.org; Fri, 15 Nov 2019 02:54:20 -0500 Received: from mga07.intel.com ([134.134.136.100]:48001) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iVWQq-0002Zs-OO for qemu-devel@nongnu.org; Fri, 15 Nov 2019 02:54:17 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Nov 2019 23:54:15 -0800 Received: from tao-optiplex-7060.sh.intel.com ([10.239.159.36]) by fmsmga002.fm.intel.com with ESMTP; 14 Nov 2019 23:54:13 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,307,1569308400"; d="scan'208";a="235987258" From: Tao Xu To: mst@redhat.com, imammedo@redhat.com, eblake@redhat.com, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, armbru@redhat.com, mdroth@linux.vnet.ibm.com, thuth@redhat.com, lvivier@redhat.com Subject: [PATCH v16 08/14] numa: Extend CLI to provide memory latency and bandwidth information Date: Fri, 15 Nov 2019 15:53:46 +0800 Message-Id: <20191115075352.17734-9-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191115075352.17734-1-tao3.xu@intel.com> References: <20191115075352.17734-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, jonathan.cameron@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Liu Jingqi Add -numa hmat-lb option to provide System Locality Latency and Bandwidth Information. These memory attributes help to build System Locality Latency and Bandwidth Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu Reviewed-by: Igor Mammedov --- Changes in v16: - Initialize HMAT_LB_Data lb_data (Igor) - Remove punctuation from error_setg (Igor) - Correct some description (Igor) - Drop statement about max value (Igor) - Simplify struct HMAT_LB_Info and related code, unify latency and bandwidth (Igor) Changes in v15: - Change the QAPI version tag to 5.0 (Eric) Changes in v14: - Use qemu ctz64 and clz64 instead of builtin function - Improve help message in qemu-options.hx --- hw/core/numa.c | 174 ++++++++++++++++++++++++++++++++++++++++++ include/sysemu/numa.h | 53 +++++++++++++ qapi/machine.json | 94 ++++++++++++++++++++++- qemu-options.hx | 49 +++++++++++- 4 files changed, 367 insertions(+), 3 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index e60da99293..47c7a96863 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -23,6 +23,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" #include "sysemu/hostmem.h" #include "sysemu/numa.h" #include "sysemu/sysemu.h" @@ -198,6 +199,166 @@ void parse_numa_distance(MachineState *ms, NumaDistOp= tions *dist, Error **errp) ms->numa_state->have_numa_distance =3D true; } =20 +void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node, + Error **errp) +{ + int i, first_bit, last_bit; + uint64_t max_entry, temp_base_la; + NodeInfo *numa_info =3D numa_state->nodes; + HMAT_LB_Info *hmat_lb =3D + numa_state->hmat_lb[node->hierarchy][node->data_type]; + HMAT_LB_Data lb_data =3D {}; + HMAT_LB_Data *lb_temp; + + /* Error checking */ + if (node->initiator > numa_state->num_nodes) { + error_setg(errp, "Invalid initiator=3D%d, it should be less than %= d", + node->initiator, numa_state->num_nodes); + return; + } + if (node->target > numa_state->num_nodes) { + error_setg(errp, "Invalid target=3D%d, it should be less than %d", + node->target, numa_state->num_nodes); + return; + } + if (!numa_info[node->initiator].has_cpu) { + error_setg(errp, "Invalid initiator=3D%d, it isn't an " + "initiator proximity domain", node->initiator); + return; + } + if (!numa_info[node->target].present) { + error_setg(errp, "The target=3D%d should point to an existing node= ", + node->target); + return; + } + + if (!hmat_lb) { + hmat_lb =3D g_malloc0(sizeof(*hmat_lb)); + numa_state->hmat_lb[node->hierarchy][node->data_type] =3D hmat_lb; + hmat_lb->list =3D g_array_new(false, true, sizeof(HMAT_LB_Data)); + } + hmat_lb->hierarchy =3D node->hierarchy; + hmat_lb->data_type =3D node->data_type; + lb_data.initiator =3D node->initiator; + lb_data.target =3D node->target; + + if (node->data_type <=3D HMATLB_DATA_TYPE_WRITE_LATENCY) { + /* Input latency data */ + + if (!node->has_latency) { + error_setg(errp, "Missing 'latency' option"); + return; + } + if (node->has_bandwidth) { + error_setg(errp, "Invalid option 'bandwidth' since " + "the data type is latency"); + return; + } + + /* Detect duplicate configuration */ + for (i =3D 0; i < hmat_lb->list->len; i++) { + lb_temp =3D &g_array_index(hmat_lb->list, HMAT_LB_Data, i); + + if (node->initiator =3D=3D lb_temp->initiator && + node->target =3D=3D lb_temp->target) { + error_setg(errp, "Duplicate configuration of the latency f= or " + "initiator=3D%d and target=3D%d", node->initiator, + node->target); + return; + } + } + + hmat_lb->base =3D hmat_lb->base ? hmat_lb->base : UINT64_MAX; + + /* Calculate the temporary base and compressed latency */ + max_entry =3D node->latency; + temp_base_la =3D 1; + while (QEMU_IS_ALIGNED(max_entry, 10)) { + max_entry /=3D 10; + temp_base_la *=3D 10; + } + + /* Calculate the max compressed latency */ + hmat_lb->base =3D MIN(hmat_lb->base, temp_base_la); + max_entry =3D node->latency / hmat_lb->base; + hmat_lb->range_bitmap =3D MAX(hmat_lb->range_bitmap, max_entry); + + /* + * For latency hmat_lb->range_bitmap record the max compressed lat= ency + * which should be less than 0xFFFF (UINT16_MAX) + */ + if (hmat_lb->range_bitmap >=3D UINT16_MAX) { + error_setg(errp, "Latency %" PRIu64 " between initiator=3D%d a= nd " + "target=3D%d should not differ from previously ente= red " + "min or max values on more than %d", node->latency, + node->initiator, node->target, UINT16_MAX - 1); + return; + } + + /* Set lb_info_provided bit 0 as 1, latency information is provide= d */ + numa_info[node->target].lb_info_provided |=3D BIT(0); + lb_data.data =3D node->latency; + } else if (node->data_type >=3D HMATLB_DATA_TYPE_ACCESS_BANDWIDTH) { + /* Input bandwidth data */ + + if (!node->has_bandwidth) { + error_setg(errp, "Missing 'bandwidth' option"); + return; + } + if (node->has_latency) { + error_setg(errp, "Invalid option 'latency' since " + "the data type is bandwidth"); + return; + } + if (!QEMU_IS_ALIGNED(node->bandwidth, MiB)) { + error_setg(errp, "Bandwidth %" PRIu64 " between initiator=3D%d= and " + "target=3D%d should be 1MB aligned", node->bandwidt= h, + node->initiator, node->target); + return; + } + + /* Detect duplicate configuration */ + for (i =3D 0; i < hmat_lb->list->len; i++) { + lb_temp =3D &g_array_index(hmat_lb->list, HMAT_LB_Data, i); + + if (node->initiator =3D=3D lb_temp->initiator && + node->target =3D=3D lb_temp->target) { + error_setg(errp, "Duplicate configuration of the bandwidth= for " + "initiator=3D%d and target=3D%d", node->initiator, + node->target); + return; + } + } + + hmat_lb->range_bitmap |=3D node->bandwidth; + first_bit =3D ctz64(hmat_lb->range_bitmap); + hmat_lb->base =3D UINT64_C(1) << first_bit; + max_entry =3D node->bandwidth / hmat_lb->base; + last_bit =3D 64 - clz64(hmat_lb->range_bitmap); + + /* + * For bandwidth, first_bit record the base unit of bandwidth bits, + * last_bit record the last bit of the max bandwidth. The max comp= ressed + * bandwidth should be less than 0xFFFF (UINT16_MAX) + */ + if ((last_bit - first_bit) > UINT16_BITS || max_entry >=3D UINT16_= MAX) { + error_setg(errp, "Bandwidth %" PRIu64 " between initiator=3D%d= and " + "target=3D%d should not differ from previously ente= red " + "values on more than %d", node->bandwidth, + node->initiator, node->target, UINT16_MAX - 1); + return; + } + + /* Set lb_info_provided bit 1 as 1, bandwidth information is provi= ded */ + numa_info[node->target].lb_info_provided |=3D BIT(1); + lb_data.data =3D node->bandwidth; + } else { + assert(0); + } + + g_array_append_val(hmat_lb->list, lb_data); +} + void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) { Error *err =3D NULL; @@ -236,6 +397,19 @@ void set_numa_options(MachineState *ms, NumaOptions *o= bject, Error **errp) machine_set_cpu_numa_node(ms, qapi_NumaCpuOptions_base(&object->u.= cpu), &err); break; + case NUMA_OPTIONS_TYPE_HMAT_LB: + if (!ms->numa_state->hmat_enabled) { + error_setg(errp, "ACPI Heterogeneous Memory Attribute Table " + "(HMAT) is disabled, enable it with -machine hmat= =3Don " + "before using any of hmat specific options"); + return; + } + + parse_numa_hmat_lb(ms->numa_state, &object->u.hmat_lb, &err); + if (err) { + goto end; + } + break; default: abort(); } diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index 788cbec7a2..70f93c83d7 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -14,11 +14,34 @@ struct CPUArchId; #define NUMA_DISTANCE_MAX 254 #define NUMA_DISTANCE_UNREACHABLE 255 =20 +/* the value of AcpiHmatLBInfo flags */ +enum { + HMAT_LB_MEM_MEMORY =3D 0, + HMAT_LB_MEM_CACHE_1ST_LEVEL =3D 1, + HMAT_LB_MEM_CACHE_2ND_LEVEL =3D 2, + HMAT_LB_MEM_CACHE_3RD_LEVEL =3D 3, + HMAT_LB_LEVELS /* must be the last entry */ +}; + +/* the value of AcpiHmatLBInfo data type */ +enum { + HMAT_LB_DATA_ACCESS_LATENCY =3D 0, + HMAT_LB_DATA_READ_LATENCY =3D 1, + HMAT_LB_DATA_WRITE_LATENCY =3D 2, + HMAT_LB_DATA_ACCESS_BANDWIDTH =3D 3, + HMAT_LB_DATA_READ_BANDWIDTH =3D 4, + HMAT_LB_DATA_WRITE_BANDWIDTH =3D 5, + HMAT_LB_TYPES /* must be the last entry */ +}; + +#define UINT16_BITS 16 + struct NodeInfo { uint64_t node_mem; struct HostMemoryBackend *node_memdev; bool present; bool has_cpu; + uint8_t lb_info_provided; uint16_t initiator; uint8_t distance[MAX_NODES]; }; @@ -28,6 +51,31 @@ struct NumaNodeMem { uint64_t node_plugged_mem; }; =20 +struct HMAT_LB_Data { + uint8_t initiator; + uint8_t target; + uint64_t data; +}; +typedef struct HMAT_LB_Data HMAT_LB_Data; + +struct HMAT_LB_Info { + /* Indicates it's memory or the specified level memory side cache. */ + uint8_t hierarchy; + + /* Present the type of data, access/read/write latency or bandwidth. */ + uint8_t data_type; + + /* The range bitmap of bandwidth for calculating common base */ + uint64_t range_bitmap; + + /* The common base unit for latencies or bandwidths */ + uint64_t base; + + /* Array to store the latencies or bandwidths */ + GArray *list; +}; +typedef struct HMAT_LB_Info HMAT_LB_Info; + struct NumaState { /* Number of NUMA nodes */ int num_nodes; @@ -40,11 +88,16 @@ struct NumaState { =20 /* NUMA nodes information */ NodeInfo nodes[MAX_NODES]; + + /* NUMA nodes HMAT Locality Latency and Bandwidth Information */ + HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES]; }; typedef struct NumaState NumaState; =20 void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp); void parse_numa_opts(MachineState *ms); +void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node, + Error **errp); void numa_complete_configuration(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); extern QemuOptsList qemu_numa_opts; diff --git a/qapi/machine.json b/qapi/machine.json index 27d0e37534..67f5910400 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -426,10 +426,12 @@ # # @cpu: property based CPU(s) to node mapping (Since: 2.10) # +# @hmat-lb: memory latency and bandwidth information (Since: 5.0) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } =20 ## # @NumaOptions: @@ -444,7 +446,8 @@ 'data': { 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', - 'cpu': 'NumaCpuOptions' }} + 'cpu': 'NumaCpuOptions', + 'hmat-lb': 'NumaHmatLBOptions' }} =20 ## # @NumaNodeOptions: @@ -557,6 +560,93 @@ 'base': 'CpuInstanceProperties', 'data' : {} } =20 +## +# @HmatLBMemoryHierarchy: +# +# The memory hierarchy in the System Locality Latency +# and Bandwidth Information Structure of HMAT (Heterogeneous +# Memory Attribute Table) +# +# For more information about @HmatLBMemoryHierarchy see +# the chapter 5.2.27.4: Table 5-146: Field "Flags" of ACPI 6.3 spec. +# +# @memory: the structure represents the memory performance +# +# @first-level: first level of memory side cache +# +# @second-level: second level of memory side cache +# +# @third-level: third level of memory side cache +# +# Since: 5.0 +## +{ 'enum': 'HmatLBMemoryHierarchy', + 'data': [ 'memory', 'first-level', 'second-level', 'third-level' ] } + +## +# @HmatLBDataType: +# +# Data type in the System Locality Latency +# and Bandwidth Information Structure of HMAT (Heterogeneous +# Memory Attribute Table) +# +# For more information about @HmatLBDataType see +# the chapter 5.2.27.4: Table 5-146: Field "Data Type" of ACPI 6.3 spec. +# +# @access-latency: access latency (nanoseconds) +# +# @read-latency: read latency (nanoseconds) +# +# @write-latency: write latency (nanoseconds) +# +# @access-bandwidth: access bandwidth (B/s) +# +# @read-bandwidth: read bandwidth (B/s) +# +# @write-bandwidth: write bandwidth (B/s) +# +# Since: 5.0 +## +{ 'enum': 'HmatLBDataType', + 'data': [ 'access-latency', 'read-latency', 'write-latency', + 'access-bandwidth', 'read-bandwidth', 'write-bandwidth' ] } + +## +# @NumaHmatLBOptions: +# +# Set the system locality latency and bandwidth information +# between Initiator and Target proximity Domains. +# +# For more information about @NumaHmatLBOptions see +# the chapter 5.2.27.4: Table 5-146 of ACPI 6.3 spec. +# +# @initiator: the Initiator Proximity Domain. +# +# @target: the Target Proximity Domain. +# +# @hierarchy: the Memory Hierarchy. Indicates the performance +# of memory or side cache. +# +# @data-type: presents the type of data, access/read/write +# latency or hit latency. +# +# @latency: the value of latency from @initiator to @target proximity doma= in, +# the latency unit is "ns(nanosecond)". +# +# @bandwidth: the value of bandwidth between @initiator and @target proxim= ity +# domain, the bandwidth unit is "B(/s)". +# +# Since: 5.0 +## +{ 'struct': 'NumaHmatLBOptions', + 'data': { + 'initiator': 'uint16', + 'target': 'uint16', + 'hierarchy': 'HmatLBMemoryHierarchy', + 'data-type': 'HmatLBDataType', + '*latency': 'time', + '*bandwidth': 'size' }} + ## # @HostMemPolicy: # diff --git a/qemu-options.hx b/qemu-options.hx index 63f6b33322..929d275450 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -168,16 +168,19 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa, "-numa node[,mem=3Dsize][,cpus=3Dfirstcpu[-lastcpu]][,nodeid=3Dnode][,= initiator=3Dnode]\n" "-numa node[,memdev=3Did][,cpus=3Dfirstcpu[-lastcpu]][,nodeid=3Dnode][= ,initiator=3Dnode]\n" "-numa dist,src=3Dsource,dst=3Ddestination,val=3Ddistance\n" - "-numa cpu,node-id=3Dnode[,socket-id=3Dx][,core-id=3Dy][,thread-id=3Dz= ]\n", + "-numa cpu,node-id=3Dnode[,socket-id=3Dx][,core-id=3Dy][,thread-id=3Dz= ]\n" + "-numa hmat-lb,initiator=3Dnode,target=3Dnode,hierarchy=3Dmemory|first= -level|second-level|third-level,data-type=3Daccess-latency|read-latency|wri= te-latency[,latency=3Dlat][,bandwidth=3Dbw]\n", QEMU_ARCH_ALL) STEXI @item -numa node[,mem=3D@var{size}][,cpus=3D@var{firstcpu}[-@var{lastcpu}]= ][,nodeid=3D@var{node}][,initiator=3D@var{initiator}] @itemx -numa node[,memdev=3D@var{id}][,cpus=3D@var{firstcpu}[-@var{lastcpu= }]][,nodeid=3D@var{node}][,initiator=3D@var{initiator}] @itemx -numa dist,src=3D@var{source},dst=3D@var{destination},val=3D@var{di= stance} @itemx -numa cpu,node-id=3D@var{node}[,socket-id=3D@var{x}][,core-id=3D@va= r{y}][,thread-id=3D@var{z}] +@itemx -numa hmat-lb,initiator=3D@var{node},target=3D@var{node},hierarchy= =3D@var{hierarchy},data-type=3D@var{tpye}[,latency=3D@var{lat}][,bandwidth= =3D@var{bw}] @findex -numa Define a NUMA node and assign RAM and VCPUs to it. Set the NUMA distance from a source node to a destination node. +Set the ACPI Heterogeneous Memory Attributes for the given nodes. =20 Legacy VCPU assignment uses @samp{cpus} option where @var{firstcpu} and @var{lastcpu} are CPU indexes. Each @@ -256,6 +259,50 @@ specified resources, it just assigns existing resource= s to NUMA nodes. This means that one still has to use the @option{-m}, @option{-smp} options to allocate RAM and VCPUs respectively. =20 +Use @samp{hmat-lb} to set System Locality Latency and Bandwidth Information +between initiator and target NUMA nodes in ACPI Heterogeneous Attribute Me= mory Table (HMAT). +Initiator NUMA node can create memory requests, usually it has one or more= processors. +Target NUMA node contains addressable memory. + +In @samp{hmat-lb} option, @var{node} are NUMA node IDs. @var{hierarchy} is= the memory +hierarchy of the target NUMA node: if @var{hierarchy} is 'memory', the str= ucture +represents the memory performance; if @var{hierarchy} is 'first-level|seco= nd-level|third-level', +this structure represents aggregated performance of memory side caches for= each domain. +@var{type} of 'data-type' is type of data represented by this structure in= stance: +if 'hierarchy' is 'memory', 'data-type' is 'access|read|write' latency or = 'access|read|write' +bandwidth of the target memory; if 'hierarchy' is 'first-level|second-leve= l|third-level', +'data-type' is 'access|read|write' hit latency or 'access|read|write' hit = bandwidth of the +target memory side cache. + +@var{lat} is latency value, the possible value and units are NUM[ns|us|ms] +(nanosecond|microsecond|millisecond), the recommended unit is 'ns'. @var{b= w} is +bandwidth value, the possible value and units are NUM[M|G|T], mean that the +bandwidth value are NUM byte (or MB/s, GB/s or TB/s depending on used suff= ix). +Note that if NUM is 0, means the corresponding latency or bandwidth inform= ation +is not provided. And if input numbers without any unit, the latency unit w= ill be +'ns' and the bandwidth will be B/s. + +For example, the following options describe 2 NUMA nodes. Node 0 has 2 cpu= s and +a ram, node 1 has only a ram. The processors in node 0 access memory in no= de +0 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s; +The processors in NUMA node 0 access memory in NUMA node 1 with access-lat= ency 10 +nanoseconds, access-bandwidth is 100 MB/s. +@example +-machine hmat=3Don \ +-m 2G \ +-object memory-backend-ram,size=3D1G,id=3Dm0 \ +-object memory-backend-ram,size=3D1G,id=3Dm1 \ +-smp 2 \ +-numa node,nodeid=3D0,memdev=3Dm0 \ +-numa node,nodeid=3D1,memdev=3Dm1,initiator=3D0 \ +-numa cpu,node-id=3D0,socket-id=3D0 \ +-numa cpu,node-id=3D0,socket-id=3D1 \ +-numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D5ns \ +-numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D200M \ +-numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D10ns \ +-numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D100M +@end example + ETEXI =20 DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd, --=20 2.20.1