From nobody Mon Feb 9 17:59:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1573805244; cv=none; d=zoho.com; s=zohoarc; b=Dyw+sxdMMBR0AB2quSFW+5bA0cleepSYkmvqD0AQV/j76p6w463hyXituGCzDFktzVcmL7n1DrCttcfih8on/C7RhYbhKAshEL0sMXEh15u4D03ThYMt1lmIPkGbLDGUgEFFnmlv46GfQMQZHpuy8ZPf1XwD5OpKAc6UHsrh3aE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1573805244; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XVojVwugliBuJ5divkyg67E1MEnCKJvEgGRrwR13GzY=; b=ZyP2F8pk9qmO0qhE3f6eLBMKiKQVZoEru9SPWlYrZ92SN68c99sa9S0Kq4XKxCX6kBcP5Ch0xrrcWXPq5ix213KcPdphsxsgqrQGJlTsQRpJknpK88A6+3ExV+W3ENNmmFYa+F2/sLOz8TaD+umjDZFQMcYbGH6aM9LjC20b5sw= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1573805244582246.70065865148786; Fri, 15 Nov 2019 00:07:24 -0800 (PST) Received: from localhost ([::1]:36456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iVWdX-0001dR-5r for importer@patchew.org; Fri, 15 Nov 2019 03:07:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39166) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iVWQy-0005yD-HM for qemu-devel@nongnu.org; Fri, 15 Nov 2019 02:54:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iVWQv-0002qg-15 for qemu-devel@nongnu.org; Fri, 15 Nov 2019 02:54:24 -0500 Received: from mga07.intel.com ([134.134.136.100]:48001) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iVWQt-0002Zs-02 for qemu-devel@nongnu.org; Fri, 15 Nov 2019 02:54:20 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Nov 2019 23:54:18 -0800 Received: from tao-optiplex-7060.sh.intel.com ([10.239.159.36]) by fmsmga002.fm.intel.com with ESMTP; 14 Nov 2019 23:54:16 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,307,1569308400"; d="scan'208";a="235987268" From: Tao Xu To: mst@redhat.com, imammedo@redhat.com, eblake@redhat.com, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, armbru@redhat.com, mdroth@linux.vnet.ibm.com, thuth@redhat.com, lvivier@redhat.com Subject: [PATCH v16 09/14] numa: Extend CLI to provide memory side cache information Date: Fri, 15 Nov 2019 15:53:47 +0800 Message-Id: <20191115075352.17734-10-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191115075352.17734-1-tao3.xu@intel.com> References: <20191115075352.17734-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, Daniel Black , jonathan.cameron@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Liu Jingqi Add -numa hmat-cache option to provide Memory Side Cache Information. These memory attributes help to build Memory Side Cache Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Reviewed-by: Daniel Black Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu --- Changes in v16: - Add cross check with hmat_lb data (Igor) - Drop total_levels in struct HMAT_Cache_Info (Igor) - Correct the error table number (Igor) Changes in v15: - Change the QAPI version tag to 5.0 (Eric) Changes in v13: - Drop the total_levels option. - Use readable cache size (Igor) --- hw/core/numa.c | 73 ++++++++++++++++++++++++++++++++++++++++ include/sysemu/numa.h | 26 +++++++++++++++ qapi/machine.json | 78 +++++++++++++++++++++++++++++++++++++++++-- qemu-options.hx | 16 +++++++-- 4 files changed, 189 insertions(+), 4 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 47c7a96863..4d7af60bfd 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -359,6 +359,66 @@ void parse_numa_hmat_lb(NumaState *numa_state, NumaHma= tLBOptions *node, g_array_append_val(hmat_lb->list, lb_data); } =20 +void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp) +{ + int nb_numa_nodes =3D ms->numa_state->num_nodes; + NodeInfo *numa_info =3D ms->numa_state->nodes; + HMAT_Cache_Info *hmat_cache =3D NULL; + + if (node->node_id >=3D nb_numa_nodes) { + error_setg(errp, "Invalid node-id=3D%" PRIu32 ", it should be less= " + "than %d", node->node_id, nb_numa_nodes); + return; + } + + if (numa_info[node->node_id].lb_info_provided !=3D (BIT(0) | BIT(1))) { + error_setg(errp, "The latency and bandwidth information of " + "node-id=3D%" PRIu32 " should be provided before config= ure " + "memory side cache attributes", + node->node_id); + return; + } + + if (node->level >=3D HMAT_LB_LEVELS) { + error_setg(errp, "Invalid level=3D%" PRIu8 ", it should be less th= an or " + "equal to %d", node->level, HMAT_LB_LEVELS - 1); + return; + } + assert(node->assoc < HMAT_CACHE_ASSOCIATIVITY__MAX); + assert(node->policy < HMAT_CACHE_WRITE_POLICY__MAX); + if (ms->numa_state->hmat_cache[node->node_id][node->level]) { + error_setg(errp, "Duplicate configuration of the side cache for " + "node-id=3D%" PRIu32 " and level=3D%" PRIu8, + node->node_id, node->level); + return; + } + + if ((node->level > 1) && + ms->numa_state->hmat_cache[node->node_id][node->level - 1] && + (node->size >=3D + ms->numa_state->hmat_cache[node->node_id][node->level - 1]->si= ze)) { + error_setg(errp, "Invalid size=3D0x%" PRIx64 ", the size of level= =3D%" PRIu8 + " should be less than the size(0x%" PRIx64 ") of " + "level=3D%" PRIu8, node->size, node->level, + ms->numa_state->hmat_cache[node->node_id] + [node->level - 1]->size, + node->level - 1); + return; + } + + hmat_cache =3D g_malloc0(sizeof(*hmat_cache)); + + hmat_cache->proximity =3D node->node_id; + hmat_cache->size =3D node->size; + hmat_cache->level =3D node->level; + hmat_cache->associativity =3D node->assoc; + hmat_cache->write_policy =3D node->policy; + hmat_cache->line_size =3D node->line; + + ms->numa_state->hmat_cache[node->node_id][node->level] =3D hmat_cache; +} + void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) { Error *err =3D NULL; @@ -410,6 +470,19 @@ void set_numa_options(MachineState *ms, NumaOptions *o= bject, Error **errp) goto end; } break; + case NUMA_OPTIONS_TYPE_HMAT_CACHE: + if (!ms->numa_state->hmat_enabled) { + error_setg(errp, "ACPI Heterogeneous Memory Attribute Table " + "(HMAT) is disabled, enable it with -machine hmat= =3Don " + "before using any of hmat specific options"); + return; + } + + parse_numa_hmat_cache(ms, &object->u.hmat_cache, &err); + if (err) { + goto end; + } + break; default: abort(); } diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index 70f93c83d7..b415550678 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -76,6 +76,27 @@ struct HMAT_LB_Info { }; typedef struct HMAT_LB_Info HMAT_LB_Info; =20 +struct HMAT_Cache_Info { + /* The memory proximity domain to which the memory belongs. */ + uint32_t proximity; + + /* Size of memory side cache in bytes. */ + uint64_t size; + + /* Cache level described in this structure. */ + uint8_t level; + + /* Cache Associativity: None/Direct Mapped/Comple Cache Indexing */ + uint8_t associativity; + + /* Write Policy: None/Write Back(WB)/Write Through(WT) */ + uint8_t write_policy; + + /* Cache Line size in bytes. */ + uint16_t line_size; +}; +typedef struct HMAT_Cache_Info HMAT_Cache_Info; + struct NumaState { /* Number of NUMA nodes */ int num_nodes; @@ -91,6 +112,9 @@ struct NumaState { =20 /* NUMA nodes HMAT Locality Latency and Bandwidth Information */ HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES]; + + /* Memory Side Cache Information Structure */ + HMAT_Cache_Info *hmat_cache[MAX_NODES][HMAT_LB_LEVELS]; }; typedef struct NumaState NumaState; =20 @@ -98,6 +122,8 @@ void set_numa_options(MachineState *ms, NumaOptions *obj= ect, Error **errp); void parse_numa_opts(MachineState *ms); void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node, Error **errp); +void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp); void numa_complete_configuration(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); extern QemuOptsList qemu_numa_opts; diff --git a/qapi/machine.json b/qapi/machine.json index 67f5910400..999235bc1b 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -428,10 +428,12 @@ # # @hmat-lb: memory latency and bandwidth information (Since: 5.0) # +# @hmat-cache: memory side cache information (Since: 5.0) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] } =20 ## # @NumaOptions: @@ -447,7 +449,8 @@ 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', 'cpu': 'NumaCpuOptions', - 'hmat-lb': 'NumaHmatLBOptions' }} + 'hmat-lb': 'NumaHmatLBOptions', + 'hmat-cache': 'NumaHmatCacheOptions' }} =20 ## # @NumaNodeOptions: @@ -647,6 +650,77 @@ '*latency': 'time', '*bandwidth': 'size' }} =20 +## +# @HmatCacheAssociativity: +# +# Cache associativity in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheAssociativity see +# the chapter 5.2.27.5: Table 5-147 of ACPI 6.3 spec. +# +# @none: None +# +# @direct: Direct Mapped +# +# @complex: Complex Cache Indexing (implementation specific) +# +# Since: 5.0 +## +{ 'enum': 'HmatCacheAssociativity', + 'data': [ 'none', 'direct', 'complex' ] } + +## +# @HmatCacheWritePolicy: +# +# Cache write policy in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheWritePolicy see +# the chapter 5.2.27.5: Table 5-147: Field "Cache Attributes" of ACPI 6.3 = spec. +# +# @none: None +# +# @write-back: Write Back (WB) +# +# @write-through: Write Through (WT) +# +# Since: 5.0 +## +{ 'enum': 'HmatCacheWritePolicy', + 'data': [ 'none', 'write-back', 'write-through' ] } + +## +# @NumaHmatCacheOptions: +# +# Set the memory side cache information for a given memory domain. +# +# For more information of @NumaHmatCacheOptions see +# the chapter 5.2.27.5: Table 5-147: Field "Cache Attributes" of ACPI 6.3 = spec. +# +# @node-id: the memory proximity domain to which the memory belongs. +# +# @size: the size of memory side cache in bytes. +# +# @level: the cache level described in this structure. +# +# @assoc: the cache associativity, none/direct-mapped/complex(complex cach= e indexing). +# +# @policy: the write policy, none/write-back/write-through. +# +# @line: the cache Line size in bytes. +# +# Since: 5.0 +## +{ 'struct': 'NumaHmatCacheOptions', + 'data': { + 'node-id': 'uint32', + 'size': 'size', + 'level': 'uint8', + 'assoc': 'HmatCacheAssociativity', + 'policy': 'HmatCacheWritePolicy', + 'line': 'uint16' }} + ## # @HostMemPolicy: # diff --git a/qemu-options.hx b/qemu-options.hx index 929d275450..ad0e5aa190 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -169,7 +169,8 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa, "-numa node[,memdev=3Did][,cpus=3Dfirstcpu[-lastcpu]][,nodeid=3Dnode][= ,initiator=3Dnode]\n" "-numa dist,src=3Dsource,dst=3Ddestination,val=3Ddistance\n" "-numa cpu,node-id=3Dnode[,socket-id=3Dx][,core-id=3Dy][,thread-id=3Dz= ]\n" - "-numa hmat-lb,initiator=3Dnode,target=3Dnode,hierarchy=3Dmemory|first= -level|second-level|third-level,data-type=3Daccess-latency|read-latency|wri= te-latency[,latency=3Dlat][,bandwidth=3Dbw]\n", + "-numa hmat-lb,initiator=3Dnode,target=3Dnode,hierarchy=3Dmemory|first= -level|second-level|third-level,data-type=3Daccess-latency|read-latency|wri= te-latency[,latency=3Dlat][,bandwidth=3Dbw]\n" + "-numa hmat-cache,node-id=3Dnode,size=3Dsize,level=3Dlevel[,assoc=3Dno= ne|direct|complex][,policy=3Dnone|write-back|write-through][,line=3Dsize]\n= ", QEMU_ARCH_ALL) STEXI @item -numa node[,mem=3D@var{size}][,cpus=3D@var{firstcpu}[-@var{lastcpu}]= ][,nodeid=3D@var{node}][,initiator=3D@var{initiator}] @@ -177,6 +178,7 @@ STEXI @itemx -numa dist,src=3D@var{source},dst=3D@var{destination},val=3D@var{di= stance} @itemx -numa cpu,node-id=3D@var{node}[,socket-id=3D@var{x}][,core-id=3D@va= r{y}][,thread-id=3D@var{z}] @itemx -numa hmat-lb,initiator=3D@var{node},target=3D@var{node},hierarchy= =3D@var{hierarchy},data-type=3D@var{tpye}[,latency=3D@var{lat}][,bandwidth= =3D@var{bw}] +@itemx -numa hmat-cache,node-id=3D@var{node},size=3D@var{size},level=3D@va= r{level}[,assoc=3D@var{str}][,policy=3D@var{str}][,line=3D@var{size}] @findex -numa Define a NUMA node and assign RAM and VCPUs to it. Set the NUMA distance from a source node to a destination node. @@ -282,11 +284,19 @@ Note that if NUM is 0, means the corresponding latenc= y or bandwidth information is not provided. And if input numbers without any unit, the latency unit w= ill be 'ns' and the bandwidth will be B/s. =20 +In @samp{hmat-cache} option, @var{node-id} is the NUMA-id of the memory be= longs. +@var{size} is the size of memory side cache in bytes. @var{level} is the c= ache +level described in this structure. @var{assoc} is the cache associativity, +the possible value is 'none/direct(direct-mapped)/complex(complex cache in= dexing)'. +@var{policy} is the write policy. @var{line} is the cache Line size in byt= es. + For example, the following options describe 2 NUMA nodes. Node 0 has 2 cpu= s and a ram, node 1 has only a ram. The processors in node 0 access memory in no= de 0 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s; The processors in NUMA node 0 access memory in NUMA node 1 with access-lat= ency 10 nanoseconds, access-bandwidth is 100 MB/s. +And for memory side cache information, NUMA node 0 and 1 both have 1 level= memory +cache, size is 10KB, policy is write-back, the cache Line size is 8 bytes: @example -machine hmat=3Don \ -m 2G \ @@ -300,7 +310,9 @@ nanoseconds, access-bandwidth is 100 MB/s. -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D5ns \ -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D200M \ -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D10ns \ --numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D100M +-numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D100M \ +-numa hmat-cache,node-id=3D0,size=3D10K,level=3D1,assoc=3Ddirect,policy=3D= write-back,line=3D8 \ +-numa hmat-cache,node-id=3D1,size=3D10K,level=3D1,assoc=3Ddirect,policy=3D= write-back,line=3D8 @end example =20 ETEXI --=20 2.20.1