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Fri, 8 Nov 2019 14:26:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1573223242; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rgCcQxWE/c9r5thmfIml1bcg46hlbRTbC2CJgE1AG/w=; b=V2dYoStL67yo7c/fiKlSoymkz6xqbHSb/N55QK9mM9lbb4ElmvELTPXOmXxbm8Xnd1nx0I jyJxeJCKenbgBAMy+/5fUVkZrqCKSPc6YiJCxlHbRyMhwIMjmE559sU9quTKan1wS8v8Ia 5JY949wzsx8QzFwSrRfyfbTgFeJYgKQ= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Eric Blake Subject: [PATCH 1/3] hw/block/pflash: Remove dynamic field width from trace event Date: Fri, 8 Nov 2019 15:26:11 +0100 Message-Id: <20191108142613.26649-2-philmd@redhat.com> In-Reply-To: <20191108142613.26649-1-philmd@redhat.com> References: <20191108142613.26649-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: jo8QY7REPuypO4t6XkvhhQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stefan Hajnoczi , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Aleksandar Markovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. Reported-by: Eric Blake Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/pflash_cfi01.c | 8 ++++---- hw/block/pflash_cfi02.c | 8 ++++---- hw/block/trace-events | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 566c0acb77..787d1196f2 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -276,7 +276,7 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwad= dr offset, DPRINTF("BUG in %s\n", __func__); abort(); } - trace_pflash_data_read(offset, width << 1, ret); + trace_pflash_data_read(offset, width << 3, ret); return ret; } =20 @@ -389,7 +389,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr of= fset, =20 break; } - trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wc= ycle); + trace_pflash_io_read(offset, width << 3, ret, pfl->cmd, pfl->wcycle); =20 return ret; } @@ -414,7 +414,7 @@ static inline void pflash_data_write(PFlashCFI01 *pfl, = hwaddr offset, { uint8_t *p =3D pfl->storage; =20 - trace_pflash_data_write(offset, width << 1, value, pfl->counter); + trace_pflash_data_write(offset, width << 3, value, pfl->counter); switch (width) { case 1: p[offset] =3D value; @@ -453,7 +453,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offse= t, =20 cmd =3D value; =20 - trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); + trace_pflash_io_write(offset, width << 3, value, pfl->wcycle); if (!pfl->wcycle) { /* Set the device in I/O access mode */ memory_region_rom_device_set_romd(&pfl->mem, false); diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 4baca701b7..f2993cdfaa 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -260,7 +260,7 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwad= dr offset, { uint8_t *p =3D (uint8_t *)pfl->storage + offset; uint64_t ret =3D pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); - trace_pflash_data_read(offset, width << 1, ret); + trace_pflash_data_read(offset, width << 3, ret); return ret; } =20 @@ -385,7 +385,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset= , unsigned int width) } break; } - trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wc= ycle); + trace_pflash_io_read(offset, width << 3, ret, pfl->cmd, pfl->wcycle); =20 return ret; } @@ -432,7 +432,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, uint8_t *p; uint8_t cmd; =20 - trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); + trace_pflash_io_write(offset, width << 3, value, pfl->wcycle); cmd =3D value; if (pfl->cmd !=3D 0xA0) { /* Reset does nothing during chip erase and sector erase. */ @@ -542,7 +542,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, } goto reset_flash; } - trace_pflash_data_write(offset, width << 1, value, 0); + trace_pflash_data_write(offset, width << 3, value, 0); if (!pfl->ro) { p =3D (uint8_t *)pfl->storage + offset; if (pfl->be) { diff --git a/hw/block/trace-events b/hw/block/trace-events index 13d1b21dd4..b9e195e172 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -8,10 +8,10 @@ fdc_ioport_write(uint8_t reg, uint8_t value) "write reg 0= x%02x val 0x%02x" # pflash_cfi01.c pflash_reset(void) "reset" pflash_timer_expired(uint8_t cmd) "command 0x%02x done" -pflash_io_read(uint64_t offset, int width, int fmt_width, uint32_t value, = uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x cm= d:0x%02x wcycle:%u" -pflash_io_write(uint64_t offset, int width, int fmt_width, uint32_t value,= uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x wcycle:%u" -pflash_data_read(uint64_t offset, int width, uint32_t value) "data offset:= 0x%04"PRIx64" value:0x%0*x" -pflash_data_write(uint64_t offset, int width, uint32_t value, uint64_t cou= nter) "data offset:0x%04"PRIx64" value:0x%0*x counter:0x%016"PRIx64 +pflash_io_read(uint64_t offset, int width, uint32_t value, uint8_t cmd, ui= nt8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%04x cmd:0x%02x wcycle= :%u" +pflash_io_write(uint64_t offset, int width, uint32_t value, uint8_t wcycle= ) "offset:0x%04"PRIx64" width:%d value:0x%04x wcycle:%u" +pflash_data_read(uint64_t offset, int width, uint32_t value) "data offset:= 0x%04"PRIx64" width:%d value:0x%04x" +pflash_data_write(uint64_t offset, int width, uint32_t value, uint64_t cou= nter) "data offset:0x%04"PRIx64" width:%d value:0x%04x counter:0x%016"PRIx64 pflash_manufacturer_id(uint16_t id) "Read Manufacturer ID: 0x%04x" pflash_device_id(uint16_t id) "Read Device ID: 0x%04x" pflash_device_info(uint64_t offset) "Read Device Information offset:0x%04"= PRIx64 --=20 2.21.0 From nobody Wed May 8 04:18:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Fri, 08 Nov 2019 09:27:56 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-194-liEGjmKnOZmJABZ5k_ffgQ-1; Fri, 08 Nov 2019 09:27:52 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 77B76477; Fri, 8 Nov 2019 14:27:51 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.206.29]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 28CE710027B0; Fri, 8 Nov 2019 14:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1573223276; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3+LGeTEi1/ybmzvAWogQzi1swRDkl4lqqo1txwkGk8A=; b=FVEEH0xwxOgf472metfw998ze/Lq25xwlH8uK/Gh8l8y+X8NXatLEf9haGHBe4nSacGuzA VS/M1P/+Na6jp0euTG03043yPUs3hpXoG17JM6jikgiYkvmS5IAXIJU/30WLO7rR9P9cR4 eXVMoZebZICBl9pYe3rFS6NczhE7+RM= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Eric Blake Subject: [PATCH 2/3] hw/mips/gt64xxx: Remove dynamic field width from trace event Date: Fri, 8 Nov 2019 15:26:12 +0100 Message-Id: <20191108142613.26649-3-philmd@redhat.com> In-Reply-To: <20191108142613.26649-1-philmd@redhat.com> References: <20191108142613.26649-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: liEGjmKnOZmJABZ5k_ffgQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stefan Hajnoczi , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Aleksandar Markovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. Reported-by: Eric Blake Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/gt64xxx_pci.c | 34 +++++++++++++++++----------------- hw/mips/trace-events | 4 ++-- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 5cab9c1ee1..f427793360 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -464,7 +464,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; =20 /* CPU Sync Barrier */ @@ -474,7 +474,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; =20 /* SDRAM and Device Address Decode */ @@ -516,7 +516,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented device register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; =20 /* ECC */ @@ -529,7 +529,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; =20 /* DMA Record */ @@ -566,7 +566,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented DMA register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; =20 /* Timer/Counter */ @@ -579,7 +579,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented timer register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; =20 /* PCI Internal */ @@ -623,7 +623,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented timer register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; case GT_PCI0_CFGADDR: phb->config_reg =3D val & 0x80fffffc; @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] =3D ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |=3D !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size << 1, val); + trace_gt64120_write("INTRCAUSE", size << 3, val); break; case GT_INTRMASK: s->regs[saddr] =3D val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size << 1, val); + trace_gt64120_write("INTRMASK", size << 3, val); break; case GT_PCI0_ICMASK: s->regs[saddr] =3D val & 0x03fffffe; - trace_gt64120_write("ICMASK", size << 1, val); + trace_gt64120_write("ICMASK", size << 3, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] =3D val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size << 1, val); + trace_gt64120_write("SERR0MASK", size << 3, val); break; =20 /* Reserved when only PCI_0 is configured. */ @@ -683,7 +683,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Illegal register write " "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; } } @@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val =3D s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size << 1, val); + trace_gt64120_read("INTRCAUSE", size << 3, val); break; case GT_INTRMASK: val =3D s->regs[saddr]; - trace_gt64120_read("INTRMASK", size << 1, val); + trace_gt64120_read("INTRMASK", size << 3, val); break; case GT_PCI0_ICMASK: val =3D s->regs[saddr]; - trace_gt64120_read("ICMASK", size << 1, val); + trace_gt64120_read("ICMASK", size << 3, val); break; case GT_PCI0_SERR0MASK: val =3D s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size << 1, val); + trace_gt64120_read("SERR0MASK", size << 3, val); break; =20 /* Reserved when only PCI_0 is configured. */ @@ -960,7 +960,7 @@ static uint64_t gt64120_readl(void *opaque, qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Illegal register read " "reg:0x03%x size:%u value:0x%0*x\n", - saddr << 2, size, size << 1, val); + saddr << 2, size, size << 3, val); break; } =20 diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 75d4c73f2e..86a0213c77 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx.c -gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read= %s value:0x%0*" PRIx64 -gt64120_write(const char *regname, int width, uint64_t value) "gt64120 wri= te %s value:0x%0*" PRIx64 +gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read= %s width:%d value:0x%08" PRIx64 +gt64120_write(const char *regname, int width, uint64_t value) "gt64120 wri= te %s width:%d value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_le= ngth, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRI= x64 "@0x%08" PRIx64 --=20 2.21.0 From nobody Wed May 8 04:18:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 08 Nov 2019 09:28:11 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-423-zuoahBc_MPycoNJQw0dZ0A-1; Fri, 08 Nov 2019 09:28:07 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4EC49800C72; Fri, 8 Nov 2019 14:28:06 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.206.29]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2590F10631CE; Fri, 8 Nov 2019 14:27:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1573223291; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E/RURPPC+PX0XGwf6Gei0vsDMgKrYkulMKMaEFtT6vg=; b=hwNfxoCG20qK2+ccJEc8HDAQ0TmEqniqAm2sU6NgvM9SAYMXVoPxg59l3v0NGfm9LHpoXD vtbld74f0vG+AZ16E5j8LttXO27SKyOs8Sg+FITjmgA5XURFmbS55rzN5EKIJ6yEp/IVkr /fnLaXyZb94U6B6iZ1b0/Vcdkj89d3A= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Eric Blake Subject: [PATCH 3/3] trace: Forbid dynamic field width in event format Date: Fri, 8 Nov 2019 15:26:13 +0100 Message-Id: <20191108142613.26649-4-philmd@redhat.com> In-Reply-To: <20191108142613.26649-1-philmd@redhat.com> References: <20191108142613.26649-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: zuoahBc_MPycoNJQw0dZ0A-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stefan Hajnoczi , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Aleksandar Markovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since not all trace backends support dynamic field width in format (dtrace via stap does not), forbid them. Add a check to refuse field width in new formats: $ make [...] GEN hw/block/trace.h Traceback (most recent call last): File "scripts/tracetool.py", line 152, in main(sys.argv) File "scripts/tracetool.py", line 143, in main events.extend(tracetool.read_events(fh, arg)) File "scripts/tracetool/__init__.py", line 371, in read_events event =3D Event.build(line) File "scripts/tracetool/__init__.py", line 285, in build raise ValueError("Event format must not contain field width '%*'") ValueError: Error at hw/block/trace-events:11: Event format must not cont= ain field width '%*' Reported-by: Eric Blake Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- scripts/tracetool/__init__.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py index 44c118bc2a..e239be602b 100644 --- a/scripts/tracetool/__init__.py +++ b/scripts/tracetool/__init__.py @@ -206,6 +206,7 @@ class Event(object): "\s*" "(?:(?:(?P\".+),)?\s*(?P\".+))?" "\s*") + _DFWRE =3D re.compile(".*(%0?\*).*") =20 _VALID_PROPS =3D set(["disable", "tcg", "tcg-trans", "tcg-exec", "vcpu= "]) =20 @@ -280,6 +281,8 @@ class Event(object): if fmt.endswith(r'\n"'): raise ValueError("Event format must not end with a newline " "character") + if Event._DFWRE.match(fmt): + raise ValueError("Event format must not contain field width '%= *'") =20 if len(fmt_trans) > 0: fmt =3D [fmt_trans, fmt] --=20 2.21.0