From nobody Tue Feb 10 02:48:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1573113221; cv=none; d=zoho.com; s=zohoarc; b=eyQ89jk/jKdJQcbO30d3CB8tfafwziZCNlqtFCeWnllOmgFYFnojzuNwZjwgz6QaExNz9dMFtVNdILcg1hljkYBvNZ2aAyLgX8OP4vA6d5B5rMt27Nnw9AAVGlWxkz4qOH0yR9sPDadpEJxpe4VRoiBcUi3nqB90v0KkbeH+j9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1573113221; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yd8Obb0BNP4KB0131g416QLwd9Ww1p7iYkzEKtKr7hY=; b=i4o2A1gAXCKBFiZcOKu01Iuhqg2NcuivM5qYYsR+VoFxcc76LYOTyVuSLB9bCTblhDq6I8aaP8qb8dfBugdpuDsO+h8RwgC04Lxlr7vOidALIN4pJuDjywi9Sa5bVkHsVvfdMayqg0zp7YC+TcfjHwqV7ejoA03HWkqfGmmb1CU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1573113221749320.3967452788962; Wed, 6 Nov 2019 23:53:41 -0800 (PST) Received: from localhost ([::1]:39596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iScbs-0000Oj-Hb for importer@patchew.org; Thu, 07 Nov 2019 02:53:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45556) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iScUN-0001hA-5V for qemu-devel@nongnu.org; Thu, 07 Nov 2019 02:45:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iScUI-0006ac-3a for qemu-devel@nongnu.org; Thu, 07 Nov 2019 02:45:53 -0500 Received: from mga02.intel.com ([134.134.136.20]:5111) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iScUH-0006BP-NK for qemu-devel@nongnu.org; Thu, 07 Nov 2019 02:45:50 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2019 23:45:48 -0800 Received: from tao-optiplex-7060.sh.intel.com ([10.239.159.36]) by fmsmga006.fm.intel.com with ESMTP; 06 Nov 2019 23:45:45 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,277,1569308400"; d="scan'208";a="404016931" From: Tao Xu To: mst@redhat.com, imammedo@redhat.com, eblake@redhat.com, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, armbru@redhat.com, mdroth@linux.vnet.ibm.com, thuth@redhat.com, lvivier@redhat.com Subject: [PATCH v15 11/12] hmat acpi: Build Memory Side Cache Information Structure(s) Date: Thu, 7 Nov 2019 15:45:10 +0800 Message-Id: <20191107074511.14304-12-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191107074511.14304-1-tao3.xu@intel.com> References: <20191107074511.14304-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, Daniel Black , Jonathan Cameron Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Liu Jingqi This structure describes memory side cache information for memory proximity domains if the memory side cache is present and the physical device forms the memory side cache. The software could use this information to effectively place the data in memory to maximize the performance of the system memory that use the memory side cache. Reviewed-by: Daniel Black Reviewed-by: Jonathan Cameron Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu --- No changes in v15. Changes in v13: - rename level as cache_level --- hw/acpi/hmat.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c index 6ec1310e62..931aa60678 100644 --- a/hw/acpi/hmat.c +++ b/hw/acpi/hmat.c @@ -135,14 +135,63 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB= _Info *hmat_lb, } } =20 +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147= */ +static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cac= he) +{ + /* + * Cache Attributes: Bits [3:0] =E2=80=93 Total Cache Levels + * for this Memory Proximity Domain + */ + uint32_t cache_attr =3D hmat_cache->total_levels & 0xF; + + /* Bits [7:4] : Cache Level described in this structure */ + cache_attr |=3D (hmat_cache->level & 0xF) << 4; + + /* Bits [11:8] - Cache Associativity */ + cache_attr |=3D (hmat_cache->associativity & 0x7) << 8; + + /* Bits [15:12] - Write Policy */ + cache_attr |=3D (hmat_cache->write_policy & 0x7) << 12; + + /* Bits [31:16] - Cache Line size in bytes */ + cache_attr |=3D (hmat_cache->line_size & 0xFFFF) << 16; + + cache_attr =3D cpu_to_le32(cache_attr); + + /* Type */ + build_append_int_noprefix(table_data, 2, 2); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + /* Length */ + build_append_int_noprefix(table_data, 32, 4); + /* Proximity Domain for the Memory */ + build_append_int_noprefix(table_data, hmat_cache->proximity, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + /* Memory Side Cache Size */ + build_append_int_noprefix(table_data, hmat_cache->size, 8); + /* Cache Attributes */ + build_append_int_noprefix(table_data, cache_attr, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + /* + * Number of SMBIOS handles (n) + * Linux kernel uses Memory Side Cache Information Structure + * without SMBIOS entries for now, so set Number of SMBIOS handles + * as 0. + */ + build_append_int_noprefix(table_data, 0, 2); +} + /* Build HMAT sub table structures */ static void hmat_build_table_structs(GArray *table_data, NumaState *numa_s= tate) { uint16_t flags; uint32_t num_initiator =3D 0; uint32_t initiator_list[MAX_NODES]; - int i, hierarchy, type; + int i, hierarchy, type, cache_level, total_levels; HMAT_LB_Info *hmat_lb; + HMAT_Cache_Info *hmat_cache; =20 for (i =3D 0; i < numa_state->num_nodes; i++) { flags =3D 0; @@ -176,6 +225,27 @@ static void hmat_build_table_structs(GArray *table_dat= a, NumaState *numa_state) } } } + + /* + * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: + * Table 5-147 + */ + for (i =3D 0; i < numa_state->num_nodes; i++) { + total_levels =3D 0; + for (cache_level =3D 1; cache_level <=3D MAX_HMAT_CACHE_LEVEL; + cache_level++) { + if (numa_state->hmat_cache[i][cache_level]) { + total_levels++; + } + } + for (cache_level =3D 0; cache_level <=3D total_levels; cache_level= ++) { + hmat_cache =3D numa_state->hmat_cache[i][cache_level]; + if (hmat_cache) { + hmat_cache->total_levels =3D total_levels; + build_hmat_cache(table_data, hmat_cache); + } + } + } } =20 void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_st= ate) --=20 2.20.1