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Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Date: Wed, 6 Nov 2019 15:14:22 +0100 Message-Id: <20191106141424.27244-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191106141424.27244-1-edgar.iglesias@gmail.com> References: <20191106141424.27244-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Plug TCG temp leaks for loads/stores. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/translate.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 761f535357..ba143ede5f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) 10 -> 10 11 -> 00 */ TCGv low =3D tcg_temp_new(); + TCGv t3 =3D tcg_const_tl(3); =20 tcg_gen_andi_tl(low, addr, 3); - tcg_gen_sub_tl(low, tcg_const_tl(3), low); + tcg_gen_sub_tl(low, t3, low); tcg_gen_andi_tl(addr, addr, ~3); tcg_gen_or_tl(addr, addr, low); tcg_temp_free(low); + tcg_temp_free(t3); break; } =20 @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc) tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); =20 if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + TCGv_i32 t0 =3D tcg_const_i32(0); + TCGv_i32 treg =3D tcg_const_i32(dc->rd); + TCGv_i32 tsize =3D tcg_const_i32(size - 1); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), - tcg_const_i32(0), tcg_const_i32(size - 1)); + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); } =20 if (ex) { @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc) 10 -> 10 11 -> 00 */ TCGv low =3D tcg_temp_new(); + TCGv t3 =3D tcg_const_tl(3); =20 tcg_gen_andi_tl(low, addr, 3); - tcg_gen_sub_tl(low, tcg_const_tl(3), low); + tcg_gen_sub_tl(low, t3, low); tcg_gen_andi_tl(addr, addr, ~3); tcg_gen_or_tl(addr, addr, low); tcg_temp_free(low); + tcg_temp_free(t3); break; } =20 @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc) =20 /* Verify alignment if needed. */ if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + TCGv_i32 t1 =3D tcg_const_i32(1); + TCGv_i32 treg =3D tcg_const_i32(dc->rd); + TCGv_i32 tsize =3D tcg_const_i32(size - 1); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc) * the alignment checks in between the probe and the mem * access. */ - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), - tcg_const_i32(1), tcg_const_i32(size - 1)); + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); } =20 if (ex) { --=20 2.20.1