From nobody Fri Dec 19 03:59:16 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1572814785; cv=none; d=zoho.com; s=zohoarc; b=nZFVVvlNWJLkrMVL4e9h9mbcFBCdcpXEnaK5QaevJH0QBXnHVt3swEFq/h3iTAwrrasAr7/R/j+vIJZNxs6FwkgtTfye/3eLxRGvIogO32cCl6fRnEbjVs2fljUFuTPZjQoyQacXJRPQJFJo3sJkh3QXJmrqBzFZAxk4g10kf8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572814785; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PWJWVpkMju41ZM+2REGY3/Rc/6OlSN46+yBieqjiMAk=; b=Oe3Z3YOB+EBkXOQLwYDVOt0yScI1Nh4l0DaR5/dvpG7QY0Tj2dusdfSNo2ux3sBh5puKFrsl7svEo2f0GmW/Rtzpbthpb1Dkd/VLM5nJM+hmgeGwUXpI8wAu1fR8Qki2OXhj5RtNejJ91iLTAySpm5trGCghva6VH+vfThNLFGA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1572814785308953.1004049289969; Sun, 3 Nov 2019 12:59:45 -0800 (PST) Received: from localhost ([::1]:56214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iRMyK-0001hW-KW for importer@patchew.org; Sun, 03 Nov 2019 15:59:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iRMv3-0008JK-Qu for qemu-devel@nongnu.org; Sun, 03 Nov 2019 15:56:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iRMv2-0002JZ-3u for qemu-devel@nongnu.org; Sun, 03 Nov 2019 15:56:17 -0500 Received: from shroom.duncanthrax.net ([2a01:4f8:121:41fa::169]:51001 helo=smtp.duncanthrax.net) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iRMv1-0002I6-IL for qemu-devel@nongnu.org; Sun, 03 Nov 2019 15:56:16 -0500 Received: from hsi-kbw-046-005-233-221.hsi8.kabel-badenwuerttemberg.de ([46.5.233.221] helo=x280.stackframe.org) by smtp.duncanthrax.net with esmtpa (Exim 4.90_1) (envelope-from ) id 1iRMux-00059W-Po; Sun, 03 Nov 2019 21:56:12 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=duncanthrax.net; s=dkim; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=PWJWVpkMju41ZM+2REGY3/Rc/6OlSN46+yBieqjiMAk=; b=i2ZIjY0verEFkhblTfV2p0c7sW ZJYM1q6JENYIDMR3bEH61PBFl4YUBLMfI0ueZddkWz/xxEioVcZrj0cR8lcVKQJHV8aVp9W9ifwJg VfqPt3EopFz4dvELTKY2v5yUoeKy3NaGAYWUOchpFN+13lDZ18EUXgu/tq2Q9QnEPPS0=; From: Sven Schnelle To: Richard Henderson Subject: [PATCH v4 1/6] hw/hppa/dino.c: Improve emulation of Dino PCI chip Date: Sun, 3 Nov 2019 21:56:02 +0100 Message-Id: <20191103205607.6590-2-svens@stackframe.org> X-Mailer: git-send-email 2.24.0.rc2 In-Reply-To: <20191103205607.6590-1-svens@stackframe.org> References: <20191103205607.6590-1-svens@stackframe.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a01:4f8:121:41fa::169 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Helge Deller , Sven Schnelle , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Helge Deller The tests of the dino chip with the Online-diagnostics CD ("ODE DINOTEST") now succeeds. Additionally add some qemu trace events. Signed-off-by: Helge Deller Signed-off-by: Sven Schnelle Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 2 +- hw/hppa/dino.c | 97 +++++++++++++++++++++++++++++++++++++------- hw/hppa/trace-events | 5 +++ 3 files changed, 89 insertions(+), 15 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 92961faa0e..7f8abbddab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -874,7 +874,7 @@ F: hw/*/etraxfs_*.c =20 HP-PARISC Machines ------------------ -Dino +HP B160L M: Richard Henderson R: Helge Deller S: Odd Fixes diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index ab6969b45f..9797a7f0d9 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino.c @@ -1,7 +1,7 @@ /* - * HP-PARISC Dino PCI chipset emulation. + * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines * - * (C) 2017 by Helge Deller + * (C) 2017-2019 by Helge Deller * * This work is licensed under the GNU GPL license version 2 or later. * @@ -21,6 +21,7 @@ #include "migration/vmstate.h" #include "hppa_sys.h" #include "exec/address-spaces.h" +#include "trace.h" =20 =20 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" @@ -82,11 +83,28 @@ #define DINO_PCI_HOST_BRIDGE(obj) \ OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE) =20 +#define DINO800_REGS ((DINO_TLTIM - DINO_GMASK) / 4) +static const uint32_t reg800_keep_bits[DINO800_REGS] =3D { + MAKE_64BIT_MASK(0, 1), + MAKE_64BIT_MASK(0, 7), + MAKE_64BIT_MASK(0, 7), + MAKE_64BIT_MASK(0, 8), + MAKE_64BIT_MASK(0, 7), + MAKE_64BIT_MASK(0, 9), + MAKE_64BIT_MASK(0, 32), + MAKE_64BIT_MASK(0, 8), + MAKE_64BIT_MASK(0, 30), + MAKE_64BIT_MASK(0, 25), + MAKE_64BIT_MASK(0, 22), + MAKE_64BIT_MASK(0, 9), +}; + typedef struct DinoState { PCIHostState parent_obj; =20 /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */ + uint32_t config_reg_dino; /* keep original copy, including 2 lowest bi= ts */ =20 uint32_t iar0; uint32_t iar1; @@ -94,8 +112,12 @@ typedef struct DinoState { uint32_t ipr; uint32_t icr; uint32_t ilr; + uint32_t io_fbb_en; uint32_t io_addr_en; uint32_t io_control; + uint32_t toc_addr; + + uint32_t reg800[DINO800_REGS]; =20 MemoryRegion this_mem; MemoryRegion pci_mem; @@ -106,8 +128,6 @@ typedef struct DinoState { MemoryRegion bm_ram_alias; MemoryRegion bm_pci_alias; MemoryRegion bm_cpu_alias; - - MemoryRegion cpu0_eir_mem; } DinoState; =20 /* @@ -122,6 +142,8 @@ static void gsc_to_pci_forwarding(DinoState *s) tmp =3D extract32(s->io_control, 7, 2); enabled =3D (tmp =3D=3D 0x01); io_addr_en =3D s->io_addr_en; + /* Mask out first (=3Dfirmware) and last (=3DDino) areas. */ + io_addr_en &=3D ~(BIT(31) | BIT(0)); =20 memory_region_transaction_begin(); for (i =3D 1; i < 31; i++) { @@ -142,6 +164,8 @@ static bool dino_chip_mem_valid(void *opaque, hwaddr ad= dr, unsigned size, bool is_write, MemTxAttrs attrs) { + bool ret =3D false; + switch (addr) { case DINO_IAR0: case DINO_IAR1: @@ -152,16 +176,22 @@ static bool dino_chip_mem_valid(void *opaque, hwaddr = addr, case DINO_ICR: case DINO_ILR: case DINO_IO_CONTROL: + case DINO_IO_FBB_EN: case DINO_IO_ADDR_EN: case DINO_PCI_IO_DATA: - return true; + case DINO_TOC_ADDR: + case DINO_GMASK ... DINO_TLTIM: + ret =3D true; + break; case DINO_PCI_IO_DATA + 2: - return size <=3D 2; + ret =3D (size <=3D 2); + break; case DINO_PCI_IO_DATA + 1: case DINO_PCI_IO_DATA + 3: - return size =3D=3D 1; + ret =3D (size =3D=3D 1); } - return false; + trace_dino_chip_mem_valid(addr, ret); + return ret; } =20 static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, @@ -194,6 +224,9 @@ static MemTxResult dino_chip_read_with_attrs(void *opaq= ue, hwaddr addr, } break; =20 + case DINO_IO_FBB_EN: + val =3D s->io_fbb_en; + break; case DINO_IO_ADDR_EN: val =3D s->io_addr_en; break; @@ -227,12 +260,28 @@ static MemTxResult dino_chip_read_with_attrs(void *op= aque, hwaddr addr, case DINO_IRR1: val =3D s->ilr & s->imr & s->icr; break; + case DINO_TOC_ADDR: + val =3D s->toc_addr; + break; + case DINO_GMASK ... DINO_TLTIM: + val =3D s->reg800[(addr - DINO_GMASK) / 4]; + if (addr =3D=3D DINO_PAMR) { + val &=3D ~0x01; /* LSB is hardwired to 0 */ + } + if (addr =3D=3D DINO_MLTIM) { + val &=3D ~0x07; /* 3 LSB are hardwired to 0 */ + } + if (addr =3D=3D DINO_BRDG_FEAT) { + val &=3D ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */ + } + break; =20 default: /* Controlled by dino_chip_mem_valid above. */ g_assert_not_reached(); } =20 + trace_dino_chip_read(addr, val); *data =3D val; return ret; } @@ -245,6 +294,9 @@ static MemTxResult dino_chip_write_with_attrs(void *opa= que, hwaddr addr, AddressSpace *io; MemTxResult ret; uint16_t ioaddr; + int i; + + trace_dino_chip_write(addr, val); =20 switch (addr) { case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: @@ -266,9 +318,11 @@ static MemTxResult dino_chip_write_with_attrs(void *op= aque, hwaddr addr, } return ret; =20 + case DINO_IO_FBB_EN: + s->io_fbb_en =3D val & 0x03; + break; case DINO_IO_ADDR_EN: - /* Never allow first (=3Dfirmware) and last (=3DDino) areas. */ - s->io_addr_en =3D val & 0x7ffffffe; + s->io_addr_en =3D val; gsc_to_pci_forwarding(s); break; case DINO_IO_CONTROL: @@ -292,6 +346,10 @@ static MemTxResult dino_chip_write_with_attrs(void *op= aque, hwaddr addr, /* Any write to IPR clears the register. */ s->ipr =3D 0; break; + case DINO_TOC_ADDR: + /* IO_COMMAND of CPU with client_id bits */ + s->toc_addr =3D 0xFFFA0030 | (val & 0x1e000); + break; =20 case DINO_ILR: case DINO_IRR0: @@ -299,6 +357,12 @@ static MemTxResult dino_chip_write_with_attrs(void *op= aque, hwaddr addr, /* These registers are read-only. */ break; =20 + case DINO_GMASK ... DINO_TLTIM: + i =3D (addr - DINO_GMASK) / 4; + val &=3D reg800_keep_bits[i]; + s->reg800[i] =3D val; + break; + default: /* Controlled by dino_chip_mem_valid above. */ g_assert_not_reached(); @@ -323,7 +387,7 @@ static const MemoryRegionOps dino_chip_ops =3D { =20 static const VMStateDescription vmstate_dino =3D { .name =3D "Dino", - .version_id =3D 1, + .version_id =3D 2, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT32(iar0, DinoState), @@ -332,13 +396,14 @@ static const VMStateDescription vmstate_dino =3D { VMSTATE_UINT32(ipr, DinoState), VMSTATE_UINT32(icr, DinoState), VMSTATE_UINT32(ilr, DinoState), + VMSTATE_UINT32(io_fbb_en, DinoState), VMSTATE_UINT32(io_addr_en, DinoState), VMSTATE_UINT32(io_control, DinoState), + VMSTATE_UINT32(toc_addr, DinoState), VMSTATE_END_OF_LIST() } }; =20 - /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. = */ =20 static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned = len) @@ -362,14 +427,16 @@ static const MemoryRegionOps dino_config_data_ops =3D= { =20 static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned = len) { - PCIHostState *s =3D opaque; - return s->config_reg; + DinoState *s =3D opaque; + return s->config_reg_dino; } =20 static void dino_config_addr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { PCIHostState *s =3D opaque; + DinoState *ds =3D opaque; + ds->config_reg_dino =3D val; /* keep a copy of original value */ s->config_reg =3D val & ~3U; } =20 @@ -453,6 +520,8 @@ PCIBus *dino_init(MemoryRegion *addr_space, =20 dev =3D qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE); s =3D DINO_PCI_HOST_BRIDGE(dev); + s->iar0 =3D s->iar1 =3D CPU_HPA + 3; + s->toc_addr =3D 0xFFFA0030; /* IO_COMMAND of CPU */ =20 /* Dino PCI access from main memory. */ memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops, diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events index 4e2acb6176..f943b16c4e 100644 --- a/hw/hppa/trace-events +++ b/hw/hppa/trace-events @@ -2,3 +2,8 @@ =20 # pci.c hppa_pci_iack_write(void) "" + +# dino.c +dino_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx6= 4" is %d" +dino_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" +dino_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" --=20 2.24.0.rc2