From nobody Mon Feb 9 11:51:31 2026 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1572113149; cv=none; d=zoho.com; s=zohoarc; b=Rs9ZcS1MRjasAIANSsoJqVz1GgKk/MPHKw2mbigPne+2KolkAKjBsK5E4WmDBK5J4KFan06pMSX/0nv9+UR2ChJiiKMJ4GrJNTlfg5YaYScOGI0eQIvPmqJdXgbuJP1UH0t+PJQ4Z+YQhfPLw5G748Dw2Paqtw9i75sc6lv+0H8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572113149; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=A6SBM94EWy9OMFAUdd3OmDn18AmNBV0jT6Xv8rmAgBE=; b=npS7ODhNo8iIU/UVNTTnhYXYSofaknc1itTxo5ewrrDAtWa7oMjrZ4/uIuJlXwFaJ3dm2zgF4U4SRtYJ6AjV6sgzUbF5msRVC530RHX2rMB8i/WUPHpsWt6oFWfnHqqyBb5GEWkXwP1nmdOczjTfBPwppRzXu+Rep4qJv+8a3uI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=none (zoho.com: 192.237.175.120 is neither permitted nor denied by domain of lists.xenproject.org) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1572113149629582.4662284024135; Sat, 26 Oct 2019 11:05:49 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQQk-000683-QD; Sat, 26 Oct 2019 18:04:50 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQQj-00067N-Fe for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:04:49 +0000 Received: from us-smtp-1.mimecast.com (unknown [207.211.31.81]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 17490a32-f81b-11e9-94d7-12813bfff9fa; Sat, 26 Oct 2019 18:04:45 +0000 (UTC) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-257-qWviySrFN8a-Vf41-bibzQ-1; Sat, 26 Oct 2019 14:04:26 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 60CB0800D41; Sat, 26 Oct 2019 18:04:25 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5AB6B60F82; Sat, 26 Oct 2019 18:04:19 +0000 (UTC) X-Inumbo-ID: 17490a32-f81b-11e9-94d7-12813bfff9fa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572113084; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T2dLm2Xz1fiqAxTYOSPP2mDkuhzEl+Dho4NsPEDSoi8=; b=e3K20mIpScMZpQQgImxzUR3u+/qIdt0q/HDNDd+5HrurKWTvo6+TB/PAkMEZsQxWN8NlHR vhbM3Z7GULSKomOObq4Q7+BGCW92jbwu7+PL17bQycwESl3dESXIsO16v75jyfab1by3os Wmg34FK4xGYQN9EIi/tvA5pmS0VFzqY= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:37 +0200 Message-Id: <20191026180143.7369-15-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: qWviySrFN8a-Vf41-bibzQ-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 14/20] hw/pci-host/piix: Move RCR_IOPORT register definition X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 The RCR_IOPORT register belongs to the PIIX chipset. Move the definition to "piix.h", and prepend the PIIX prefix. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: prepend PIIX prefix (Aleksandar) --- hw/i386/acpi-build.c | 2 +- hw/isa/piix4.c | 2 +- hw/pci-host/piix.c | 7 ++++--- include/hw/i386/pc.h | 6 ------ include/hw/southbridge/piix.h | 6 ++++++ 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index b1b050d8e2..266d9b534b 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, Acp= iPmInfo *pm) =20 /* The above need not be conditional on machine type because the reset= port * happens to be the same on PIIX (pc) and ICH9 (q35). */ - QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT !=3D RCR_IOPORT); + QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT !=3D PIIX_RCR_IOPORT); =20 /* Fill in optional s3/s4 related properties */ o =3D object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index f3e21ea76d..86678e6829 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -166,7 +166,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), - RCR_IOPORT, &s->rcr_mem, 1); + PIIX_RCR_IOPORT, &s->rcr_mem, 1); =20 /* initialize i8259 pic */ i8259_out_irq =3D qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 3292703de7..6548d9a4b5 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -27,6 +27,7 @@ #include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" +#include "hw/southbridge/piix.h" #include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/sysbus.h" @@ -87,7 +88,7 @@ typedef struct PIIX3State { /* Reset Control Register contents */ uint8_t rcr; =20 - /* IO memory region for Reset Control Register (RCR_IOPORT) */ + /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; } PIIX3State; =20 @@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp) =20 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOP= ORT, - &d->rcr_mem, 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &d->rcr_mem, 1); =20 qemu_register_reset(piix3_reset, d); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2fd40ceebe..d6ff95e047 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -240,12 +240,6 @@ typedef struct PCII440FXState PCII440FXState; =20 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" =20 -/* - * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). - */ -#define RCR_IOPORT 0xcf9 - PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix_devfn, ISABus **isa_bus, qemu_irq *pic, diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index add352456b..e49d4a6bbe 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t s= mb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); =20 +/* + * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). + */ +#define PIIX_RCR_IOPORT 0xcf9 + extern PCIDevice *piix4_dev; =20 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, --=20 2.21.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel