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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r27sm42606124wrc.55.2019.10.24.09.28.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:28:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YX5kAV2V+51rIRAoIJH8dk7lXcJe17TkZW9vBLdbmdY=; b=zgdQDlmI2ot3n40f+DLOr+5xsOXSL/83GFPGtC7ZlYuqaVhTwCEN/nsMk+emHyS0Dc Ek6nzWFKjzxJRB14MvNmM3gcUHk1Wri1xIlBmHgvPLqkbk+7Qfvxnxk/YFRtRSUpxlWu /cMA+jm+Tds5TSuVuIMXMjskRctXVkIhXz60J5pPE1dDzOBxAGIjW6fPwZNsvTpccb6o SXb/oW2oflRqc4OA/MxBs557+2fTMfSR8OJ8OUvhRKDoDhs9u3tuZVnP9xlEiiuOeonN 1elnCEkS1rty0hBzNOFtrlalDlrHusd98zFdK1VOdE3c7x1GPp+cNvtGzdRlrSvh9MNa M1fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YX5kAV2V+51rIRAoIJH8dk7lXcJe17TkZW9vBLdbmdY=; b=hpzleNZ/Rp9F58OfivcQcisRnZeZO53fRwuixJ7RYyURYwSEMt0D3nwW+hLuecbpYO kYPQlaq6EydWnKhxqyUs9qGt58URE5WIlly0hjPX2tI3XRuMp3/SWG6RjxgT8hnMWK2k ebUQgiOJ9k7KstzbcjGhTcRQf6kLcrJ4lVs0nVBU19vF1DCqmp+2V+1eFOEHB8vWRCdD 1iblvweO7owbnWpiaHvpYR+u+/n5ze7VQltLDEGe/X9wFhi9hqQ/MM7aRV3wsx/S3zXF gX8kJYVgzjYkc8TqHoo5J5r5MMQh/0A9lJreoi2chNsP4qVP62/ZqN+R1RSnuoJLgqxA oLqA== X-Gm-Message-State: APjAAAVonriTWatGcBa4/vy24WoQmmSautAhhkI845HSfpEM20LLHSg1 XX2K5Lq5uwSbIjAJRLT4gwDuTpyr6VE= X-Google-Smtp-Source: APXvYqxfa0RjSE0fKc2ugPraEPK85a0Cgrck4/0stnzaaDlAznGAWeAssdKk6AdHEC5KkL2e03AFgw== X-Received: by 2002:a1c:5587:: with SMTP id j129mr5669423wmb.15.1571934492938; Thu, 24 Oct 2019 09:28:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/51] target/arm: Allow SVE to be disabled via a CPU property Date: Thu, 24 Oct 2019 17:27:10 +0100 Message-Id: <20191024162724.31675-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191024162724.31675-1-peter.maydell@linaro.org> References: <20191024162724.31675-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Andrew Jones Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via a CPU property") we can disable the 'max' cpu model's VFP and neon features, but there's no way to disable SVE. Add the 'sve=3Don|off' property to give it that flexibility. We also rename cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them to follow the typical *_get/set_ pattern. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Tested-by: Masayoshi Mizuma Reviewed-by: Beata Michalska Message-id: 20191024121808.9612-4-drjones@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 52 ++++++++++++++++++++++++++++++++++------ target/arm/monitor.c | 2 +- tests/arm-cpu-features.c | 1 + 4 files changed, 49 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ab3e1a03616..72a27ec4b0e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -200,7 +200,8 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |=3D CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] =3D cpu->sve_max_vq - 1; + env->vfp.zcr_el[1] =3D cpu_isar_feature(aa64_sve, cpu) ? + cpu->sve_max_vq - 1 : 0; env->vfp.zcr_el[2] =3D env->vfp.zcr_el[1]; env->vfp.zcr_el[3] =3D env->vfp.zcr_el[1]; /* diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a7..89a8ae77fe8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -256,15 +256,23 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 -static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - visit_type_uint32(v, name, &cpu->sve_max_vq, errp); + uint32_t value; + + /* All vector lengths are disabled when SVE is off. */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + value =3D 0; + } else { + value =3D cpu->sve_max_vq; + } + visit_type_uint32(v, name, &value, errp); } =20 -static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); Error *err =3D NULL; @@ -279,6 +287,34 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v= , const char *name, error_propagate(errp, err); } =20 +static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + bool value =3D cpu_isar_feature(aa64_sve, cpu); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + Error *err =3D NULL; + bool value; + uint64_t t; + + visit_type_bool(v, name, &value, &err); + if (err) { + error_propagate(errp, err); + return; + } + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); + cpu->isar.id_aa64pfr0 =3D t; +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -391,8 +427,10 @@ static void aarch64_max_initfn(Object *obj) #endif =20 cpu->sve_max_vq =3D ARM_MAX_VQ; - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_v= q, - cpu_max_set_sve_vq, NULL, NULL, &error_fatal); + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_m= ax_vq, + cpu_max_set_sve_max_vq, NULL, NULL, &error_fat= al); + object_property_add(obj, "sve", "bool", cpu_arm_get_sve, + cpu_arm_set_sve, NULL, NULL, &error_fatal); } } =20 diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 560970de7f5..2209b27b9a0 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -97,7 +97,7 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **err= p) * then the order that considers those dependencies must be used. */ static const char *cpu_model_advertised_features[] =3D { - "aarch64", "pmu", + "aarch64", "pmu", "sve", NULL }; =20 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c index c59fcf409c8..6342cd2e4ec 100644 --- a/tests/arm-cpu-features.c +++ b/tests/arm-cpu-features.c @@ -179,6 +179,7 @@ static void test_query_cpu_model_expansion(const void *= data) =20 if (g_str_equal(qtest_get_arch(), "aarch64")) { assert_has_feature(qts, "max", "aarch64"); + assert_has_feature(qts, "max", "sve"); assert_has_feature(qts, "cortex-a57", "pmu"); assert_has_feature(qts, "cortex-a57", "aarch64"); =20 --=20 2.20.1