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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r27sm42606124wrc.55.2019.10.24.09.27.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OcDwolq811QfFGrcusum3clsrtTFTFlEcKsQCy0b1II=; b=CWKNZRu50x3NXUtb5L3mJRGn3uqHj8atMRMa95upiM9i4WgIAwDPOX7j8qvdr7lTa8 h13k0I56j1ZnI5SMDUQpuFAvbywcLk7LnnwVnZvd0jCy44wrieXULyAUEZoZ1+RJm79S IpUtDw9RSzIKAldSCbfjRG8m08Vrqltu6lb6Oe4OfmsDdAu1TB2Bi1JxoHCbeK4TNd2J i4C0sb8+m8R2Hwd6sDVnTJDv97bWBw7wCtRPhw51TqebSbS6MZvh1beYcVeobKl0lYzu N+EFUpRbwZpkwSszCxfj4FOeq6XqQNCtd1ztCEPT4E7YbFoeacMKC692YUm1y/WAGH8D xn0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OcDwolq811QfFGrcusum3clsrtTFTFlEcKsQCy0b1II=; b=IrTVG3s+mYe1YJskhgkdX2wqcDD4rNjTakwzY6PB4W+J25+cna0QNvuRLSoasb2L0f edNZrf2kzp5nBdhCv/FTuOdf2maP2uttLqoX5A33Pb/QkprHQBHYZds9LIH0Qh/LeFjZ FqR2JfDmFBe1FOANYUOzo0Nau1huHD/dIMQoUKbvw7FDSvpCLUoaS3cyM4uvllD8cO5c 3MxtjQaW4xBkyVEod/5aHvUAydjYkk9NB6TlcLmINnBGN/vv/JKAN40Gi2xG0SVk32Ur +Vc5ityqWEcp0FZukvjnTbXhxKRywwB3XQ+cH0VnJN8jsoOzBomjMOXMRu8M2mRgvZlP fdIA== X-Gm-Message-State: APjAAAW7xjf7UTxZaTWg0X7d/KNmUw8P/BnT+PMh6VEA8EVmK/GbQyQ9 Pjkudm4UfJdL2IZ/+Tp2hgIe9U/++lk= X-Google-Smtp-Source: APXvYqycShgE8A0+nHVrrQ4vQr+m5eAkGPqLHnykvt+9i7KeT/BkpYw2ibwtC4+FBxXhUb37nhO8gQ== X-Received: by 2002:a05:6000:34f:: with SMTP id e15mr5073912wre.232.1571934470892; Thu, 24 Oct 2019 09:27:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/51] target/arm: Rebuild hflags at MSR writes Date: Thu, 24 Oct 2019 17:26:52 +0100 Message-Id: <20191024162724.31675-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191024162724.31675-1-peter.maydell@linaro.org> References: <20191024162724.31675-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20191023150057.25731-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 13 +++++++++++-- target/arm/translate.c | 28 +++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634c..d4bebbe6295 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { /* I/O operations must end the TB here (whether read or write) */ s->base.is_jmp =3D DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 96340520ee2..46a0bf51c95 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) ri =3D get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) } } =20 - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { - /* I/O operations must end the TB here (whether read or write)= */ - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb =3D ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && + (ri->type & ARM_CP_IO)); + + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb =3D true; + } + if (need_exit_tb) { gen_lookup_tb(s); } =20 --=20 2.20.1