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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r27sm42606124wrc.55.2019.10.24.09.27.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0MGAigKQQJD7cJXlO5y60b4rzDCDAg5e78HpKgtRa3w=; b=LZ+vNWj/BJfxz9mI3hKgvf6n5hrg8oPyhZbNbpQ34O670N+KLXCD7K6qRTjWuFJlbc G/4vT3El4dH6Y6UDEUmOdEgX5w/pf+WtmKWH3plgyyJPvPsYF1MIbnzlbXPHTlZrvLd4 bYxe4XTUPzV9ScQOC48kBHvN3UU3lOPs53Lx/iqHiB5V91HEWsuURLxEjzJ9i4E61NqD AQ7I259Yl4IWVzeM+hDWDh+EPUrt78lDRt2KTKvmAyeQBRMaSsB5gh/t6rFtRTqswS4m 0lsAAamj5se+pD5rJ3iSb4/EZqMDaBiOXSM1TX+VWVvIv43q3Se0y/J6g83rWL1uEDaA Cpdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0MGAigKQQJD7cJXlO5y60b4rzDCDAg5e78HpKgtRa3w=; b=OBcQnfmtnbYbG6KuFlhYAVxRfFDHjVtgrDPYyqhtZEk61T9/CH+LSJFWCcPzJcFeaK C8nuqUljx4JGolUsqEvZwZ0eNZOK6KAwFg/EGWBjU+lxjD7HpiCXTbDfy0wcYXJqEajj Wv/b2LAOk12qi3XhivciluCY068HDqaOi2/NrwFszMqnvMZotEsxQB4pGV0jWRBi8Y7K AWMlG9Zu5zmzIe6DjJc5Auo+ExlCiMV99srJ5tnPJm2n+CFRzbJXcbELjMcaeBfTg8Ot LvbNjy6IKKtW3b8k2R0182kDUOcCLBHAfD7xQTKV/jNcj3MEQybrICrcJH3bfMSYKOf9 4/Kg== X-Gm-Message-State: APjAAAX0jOOl02ScYLpflUvreOAI+CuBtspZ8J4rtj39XgUr8qrlOpGA AO/SZ58ojcIcZjojQbCSPvlbiOZzGvg= X-Google-Smtp-Source: APXvYqxkWzTPXGHkmJlrDBhwhsJXO8s4V5LL0ReXu+Xcj8aPfvW98r59dGfnTusXJ+N2keO8zAb8Hg== X-Received: by 2002:a05:600c:2948:: with SMTP id n8mr5497183wmd.128.1571934462548; Thu, 24 Oct 2019 09:27:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/51] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state Date: Thu, 24 Oct 2019 17:26:45 +0100 Message-Id: <20191024162724.31675-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191024162724.31675-1-peter.maydell@linaro.org> References: <20191024162724.31675-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Hoist the variable load for PSTATE into the existing test vs is_a64. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20191023150057.25731-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e2a62cf19a0..398e5f5d6df 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); int current_el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags, pstate_for_ss; =20 if (is_a64(env)) { *pc =3D env->pc; @@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + pstate_for_ss =3D env->pstate; } else { *pc =3D env->regs[15]; =20 @@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } + pstate_for_ss =3D env->uncached_cpsr; } =20 - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State * 0 x Inactive (the TB flag for SS is always 0) @@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && + (pstate_for_ss & PSTATE_SS)) { + flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } =20 *pflags =3D flags; --=20 2.20.1