From nobody Thu Dec 18 19:36:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1571751439; cv=none; d=zoho.com; s=zohoarc; b=BHdcKAp2hhEWJqpdzAakcKnKTtd7nZ9zBJ0Cw5AYVxJCHtknXyMqFdUIMRFC9++0fQmiEYDE7z5JerPufqh/E4bIfdT4Auxzro9P/ewMSFpI0EyJFjq18ftuQ/kHwVAguOIDm4NKkpbN8n2JpFm+VvJamA19ozwHSX3ZSa9Jl+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571751439; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=62R1pMICSQgalMj3UXUALVQERlO54EdusG7o+yE6TlY=; b=lHNRU0zwlQxnGBQRGpO69Ck/6TVhLhmxJhDCaj+CT6z/dL19MvhJrnswFvFm+0I2B3xw20ddGJ+/DLJSzMAgb2UyiHQiYax9NocKd8c9PB7WEy5y1hfUpHhsFh66ehAtQMwdN1YtFLz6h4R5YusLf6/F6J8jebNeEvy6Kk97vcw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1571751439310266.40411104419684; Tue, 22 Oct 2019 06:37:19 -0700 (PDT) Received: from localhost ([::1]:57442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuLd-0008Py-IL for importer@patchew.org; Tue, 22 Oct 2019 09:37:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36670) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuGX-0002OB-Dd for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:32:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iMuGW-0001Do-46 for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:32:01 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:39124) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iMuGV-0001DX-TT for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:32:00 -0400 Received: by mail-wm1-x343.google.com with SMTP id r141so6597270wme.4 for ; Tue, 22 Oct 2019 06:31:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=62R1pMICSQgalMj3UXUALVQERlO54EdusG7o+yE6TlY=; b=Z4vb/i3R6ex105D81hSYBBuA86o9BCOBOVC1weSVsW3O56iD+KGBAQW8DB/Mb6jefh jCKCMDbF7Z3MA2a/DkXZkPuOMHWPPeAERCwXy2e4YLNCtWzFnBQa7S4ubGr2JYxTqI4V 4UicT21g0dxnFaP6ZClIwR7c+7RaxpgF7nyt82ZNRrXfW8MPcKnlwHYKS1djxs3Nii2C p8h7jyAmZ49SolDLwlR2ZImF35Qm6iR+COQlO6v/Mhq8LMhESETkMAmuSlXVikFhQgLg Vl3pX7nyrFRJRr+KZiZ0I5XdBlHZCef1f5FP/uk3pSTeAwnAB8PNN6F3VqPIuJNcyEkN fvGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=62R1pMICSQgalMj3UXUALVQERlO54EdusG7o+yE6TlY=; b=O8ofZUb8c3dgd2OeiBtBq5HmQ0jweVVemnUrqerC5kkAyJ6gSji12BkxnqCB+dWUSG VExO356ESKBVPSeYRgXREXeAeGsQsbwPdlIbZJfSrc7T9S6gSapLyxZLRQFe02BYFPQz mMlbPQOYXYr/JIJtul4ARhWstPXEjGH4shGTCe7Lr3wpTaJ1XN0364C7U7Tn2wLImd4B mitc16QMwGejYbDo2W837w78zBdvQZlAI+Y0hh2zLgxrsXB/iR4o4+VN2igHbb5DsZeR YyxC7csAhCXySS7oMz5w4of+gnF65KcaVzymveftd67hfhUn2NNUdOwm5LYZjIsq1eCe vQmw== X-Gm-Message-State: APjAAAWsi+ulPMCenZoRLrI68IUs0gBMp/XgVOJTpfNOEwyh0KUkccxB zHKxAPDBeK6h+8F4KVvnKwKLrQpQeAI= X-Google-Smtp-Source: APXvYqy0zEg3x1lefwuCs0LcKZ2x9Qu3CHF12Yvp0lOmJI4JI6kkO8mHc4pH8NoUSZgud29oYSBMlQ== X-Received: by 2002:a05:600c:28d:: with SMTP id 13mr3286359wmk.100.1571751118316; Tue, 22 Oct 2019 06:31:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/41] hw/timer/lm32_timer: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:31:00 +0100 Message-Id: <20191022133134.14487-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Switch the lm32_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the ytimer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20191017132905.5604-4-peter.maydell@linaro.org --- hw/timer/lm32_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c index fabde760b2d..3fdecd09fe2 100644 --- a/hw/timer/lm32_timer.c +++ b/hw/timer/lm32_timer.c @@ -30,7 +30,6 @@ #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/module.h" =20 #define DEFAULT_FREQUENCY (50*1000000) @@ -63,7 +62,6 @@ struct LM32TimerState { =20 MemoryRegion iomem; =20 - QEMUBH *bh; ptimer_state *ptimer; =20 qemu_irq irq; @@ -119,6 +117,7 @@ static void timer_write(void *opaque, hwaddr addr, s->regs[R_SR] &=3D ~SR_TO; break; case R_CR: + ptimer_transaction_begin(s->ptimer); s->regs[R_CR] =3D value; if (s->regs[R_CR] & CR_START) { ptimer_run(s->ptimer, 1); @@ -126,10 +125,13 @@ static void timer_write(void *opaque, hwaddr addr, if (s->regs[R_CR] & CR_STOP) { ptimer_stop(s->ptimer); } + ptimer_transaction_commit(s->ptimer); break; case R_PERIOD: s->regs[R_PERIOD] =3D value; + ptimer_transaction_begin(s->ptimer); ptimer_set_count(s->ptimer, value); + ptimer_transaction_commit(s->ptimer); break; case R_SNAPSHOT: error_report("lm32_timer: write access to read only register 0x" @@ -176,7 +178,9 @@ static void timer_reset(DeviceState *d) for (i =3D 0; i < R_MAX; i++) { s->regs[i] =3D 0; } + ptimer_transaction_begin(s->ptimer); ptimer_stop(s->ptimer); + ptimer_transaction_commit(s->ptimer); } =20 static void lm32_timer_init(Object *obj) @@ -195,10 +199,11 @@ static void lm32_timer_realize(DeviceState *dev, Erro= r **errp) { LM32TimerState *s =3D LM32_TIMER(dev); =20 - s->bh =3D qemu_bh_new(timer_hit, s); - s->ptimer =3D ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer =3D ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT); =20 + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, s->freq_hz); + ptimer_transaction_commit(s->ptimer); } =20 static const VMStateDescription vmstate_lm32_timer =3D { --=20 2.20.1